18
Staggered PRT Algorithm Update Sebastian Torres and David Warde CIMMS/University of Oklahoma and NSSL/NOAA Data Quality MOU – Technical Interchange Meeting Norman, OK 1 December, 2009

Staggered PRT Algorithm Update

Embed Size (px)

DESCRIPTION

Staggered PRT Algorithm Update. Sebastian Torres and David Warde CIMMS/University of Oklahoma and NSSL/NOAA. Data Quality MOU – Technical Interchange Meeting Norman, OK 1 December, 2009. SPRT Algorithm Evolution. 2003 : 2/3 PRT ratio with DC filter NSSL Report 7 - PowerPoint PPT Presentation

Citation preview

Page 1: Staggered PRT  Algorithm Update

Staggered PRT Algorithm Update

Sebastian Torres and David WardeCIMMS/University of Oklahoma

and NSSL/NOAA

Data Quality MOU – Technical Interchange Meeting

Norman, OK

1 December, 2009

Page 2: Staggered PRT  Algorithm Update

SPRT Algorithm Evolution

• 2003: 2/3 PRT ratio with DC filter– NSSL Report 7

• 2005: SACHI filter (standalone)– NSSL Report 9

• 2008: Any PRT ratio with DC filter– NSSL Report 12

• 2009: 2/3 PRT ratio with SACHI filter– Separate document delivered on 03/09

• 2009: 2/3 PRT ratio with SACHI filter and overlaid echo recovery

– Separate document delivered on 07/09– NSSL Report 13

Page 3: Staggered PRT  Algorithm Update

2009 SPRT AEL (07/09)

• Notation standardization• Clutter filtering update– SACHI on Segments I and II

• Functionality same as in Report 11• Adapted to “fit” signal processing pipeline• Steps described in algorithmic form

– DC removal on Segment III

• Recovery of overlaid echoes– Segment III data reconstruction– Overlaid echo determination

Page 4: Staggered PRT  Algorithm Update

Recap: Squeezing SACHI in

• Strong-point clutter canceling– Inputs: P, R1, and R2

– Outputs: P, R1, and R2

• SACHI needs to return P, R1, and R2

– Derived from SACHI’s outputs: S, v, and v

– In the absence of SPC, the spectral moment computations should produce S, v, and v again!SACHI

SPC Remov

al

Spectral moment

computations

VConversio

nSvv

PR1

R2

PR1

R2

Sv1, v2v

Page 5: Staggered PRT  Algorithm Update

• Segments I and II– SACHI

• Output: “manufactured” P, R1, and R2

• Segment III– DC removal

• Output: a dwell of time-series data

– Power and correlation computations• Output: P1, P2, R1, and R2

– Combined power computation• Output: P

Recap: Clutter Filtering Logic

Page 6: Staggered PRT  Algorithm Update

Further AEL Updates

• Handling overlaid echoes– Better performance from using short PRTs

• Algorithm modifications– Segment-III data “reconstruction”

• R1 and R2 are computed for all range gates

– Handling overlaid echoes• Detecting and flagging

– Ground clutter filtering• Rules to handle overlaid clutter

– Overlaid power correction for SACHI

ra,2

ra,1

rmax

Page 7: Staggered PRT  Algorithm Update

Segment-III Data Reconstruction

T1 T2

I II I II III

I II III

Segment I Segment II Segment III

1

2

3

4

S1+S3 S2 S3

M 1

M

S1 S2

S1+S3 S2 S3

S1 S2

S1+S3 S2 S3

S1 S2 R1

R2

S1+S3

S1+S3

S1+S3Available only

within ra1

Available within ra2

ra1

ra2

I II III

Page 8: Staggered PRT  Algorithm Update

Handling Overlaid Echoes

• Segments I and III may contain overlaid echoes

– Overlaid echoes appear on every other pulse• Correlations are not biased

– Overlaid echoes do not contaminate reflectivity• Combined powers use only “clean” data

– Moment-specific overlaid power thresholds are used to recover velocity and width for the strong trip

• Segment II does not contain overlaid echoes

Segment I Segment II Segment III

T1

T2 S1+S3 S2 S3

S1 S2 S1+S3

Page 9: Staggered PRT  Algorithm Update

S3

S1

• Algorithm assumes no clutter beyond ra1

– No clutter in Segment III

• Segment I gates– Segment I clutter (C1): SACHI

– Overlaid power correction (S3): computed from T2 pulses

• Segment II gates– Segment II clutter (C2): SACHI

• Segment III gates– Segment I clutter (C1): DC removal on T1 pulses

S1+S3

S1+S3

Clutter Filtering LogicSegment I Segment II Segment III

T1

T2 S3

S1+C1

S1+C1+S3

S2

S2S2+C2

S2+C2 S1+C1+S3

S1+S3+C3

S1+S3+C3

S1+C1+S3

S1+C1+S3

Page 10: Staggered PRT  Algorithm Update

Overlaid Correction for SACHI

• SACHI is not designed to handle overlaid echoes

– After perfect filtering, it would return S = S1+S3/2

– Need to remove S3/2

– S3 is computed from the T2 pulses

• S3/2 is subtracted from the power estimates that are used to produce the manufactured outputs

Segment I Segment II Segment III

T1

T2 S1+C1+S3 S2 S3

S1+C1 S2 S1+C1+S3

Page 11: Staggered PRT  Algorithm Update

Final SPRT AEL (I)

Page 12: Staggered PRT  Algorithm Update

Final SPRT AEL (II)

Page 13: Staggered PRT  Algorithm Update

Computational Complexity (I)

• The most computationally intensive step in the SPRT algorithm is SACHI

• For SACHI, complexity is mainly driven by– DFT of the extended time series

• O(Mx2) = 6.25 O(M 2)

– Matrix multiplications• Two complex matrix multiplications

– 5-by-5 times 5-by-Mp : 2x5x5xM real multiplications ≈ O(M )

• One real matrix multiplication– 5-by-5 times 5-by-Mp : 5x5xM/2 real multiplications ≈ O(M )

– SACHI is not recursive and other steps involve routine computations performed in the FFT mode

• The GMAP notchwidth computation does not require an additional DFT nor the recursive part of GMAP

Page 14: Staggered PRT  Algorithm Update

Computational Complexity (II)• VCP 221 vs. VCP 222

• DFT for SPRT compared to DFT for Batch

– Mx = (5/2) MSPRT = (5/2) (MSPRT /MBATCH) MBATCH

– O(Mx2) = [(5/2) (MSPRT /MBATCH)]2 O(MBATCH

2)

Elev. (deg

)

Batch Sample

s

SPRT Sample

s

Addt’l DFT

Complexity

2.4 61 46 3.56

3.35 61 56 5.27

4.3 61 62 6.46

6 59 80 11.49

Page 15: Staggered PRT  Algorithm Update

RVP-8 CPU Load• Extracted from Steve Smith’s presentation to the

SREC (Jun 2008)

Page 16: Staggered PRT  Algorithm Update

Computational Complexity (III)• Back of the envelope computations– Assume that CPU load in Batch mode is ~10%

• This includes GMAP for the short PRT pulses (all bins?)• Number should not depend on coverage

– Batch mode• Assume that DFT takes ~33% of total computations for

the Batch mode– DFT CPU load is ~3%

• “Other steps” CPU load is ~7%

– SPRT algorithm• Assume that DFT in the SPRT algorithm takes 10 times

longer– DFT CPU load is ~30%

• Assume “other steps” in the SPRT algorithm take 4 times longer than the “other steps” in the Batch mode

– Total CPU load of ~30% + 4x7% ≈ 60%

Page 17: Staggered PRT  Algorithm Update

Conclusions

• Provided a new AEL for staggered PRT with updates in the following areas:

– Notation standardization– Incorporation of SACHI– Handling of overlaid echoes

• Computational complexity of SACHI is predicted to be within current processing capabilities

– SPRT should not require new hardware– Could it be “the straw that breaks the camel’s back”?

• Final version of the algorithm is complete!– Will support ROC’s implementation

and validation

Page 18: Staggered PRT  Algorithm Update

Questions?

Batch ModeVCP 11

Staggered PRT( = 2/3, same DT)

ra = 147 km, va = 28.8 m/s ra = 184 km, va = 45.1 m/s

March 3, 20042.5 deg