3.Field-Effect Transistor (FET)

Junction Field-Effect Transistor (JFET)

n-channel JFET

VGS = 0 V and VDS positive value

When VGS=0V and C some positive value,the upper region of the p-type material will be reverse biased higher than the lower region(the greater the reverse bias,the wider the depletion region).

As the voltage VDS is increased from 0 to a few volts,the current will increase as determined by Ohm’s law and The depletion region will widen,causing a noticeable reduction in channel widht.If VDS is increased to a level where it appears that the two depletion regions would “touch”, a condition referred to as pinch-off will result.The level of VDS that establishes this condition is referred to as pinch-off voltage Vp (when VGS=0V and VDS>Vp IDSS).

Input resistance > 108Ω

VGS < 0V

Voltage-Controlled Resistor:

where ro is the resistance with VGS _ 0 V and rd the resistance at a particular level of VGS.

Power dissipation:

p-channel JFET

PD = |VD|ID

Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) Or Insulated-Gate FET (IGFET)

Depletio-Type MOSFET (D-MOSFET) n-channel D-MOSFET

When VGS=0V,the drain current is IDSS.The negative potential at the gate will tend to pressure electrons toward the p-type substrate and attract holes from the p-type substrate.The drain current is therefore reduce with increasing negative bias for VGS.The positive potential at the gate will draw additional electrons (free carrier) from the p-type substrate due to the reverse leakage current,reveals that the drain current will increase.

Input resistance > 1010Ω

p-channel D-MOSFET

Enhachement-Type MOSFET (E-MOSFET)n-channel E-MOSFET

If VGS = 0V,the absence of an n-channel will result in a current of effectively zero amperes.

p-channel E-MOSFET

Complementary MOSFET (CMOS)A very effective logic circuit can be established by contructing a p-channel and an n-channel MOSFET on the same substrate.

FET BiasingFor de analysis,the coupling capacitors are open cicuits.Fixed-Bias Configuration

Graphical Approach:

Self-Bias Configuration Graphical Approach:

Voltage-Divinder Biasing Graphical Approach:

Depletion-Type MOSFETGraphical Approach:

Enhancement-Type MOSFET

Graphical Approach:

p-channel FET

V GS=V DS=V DD−I D RD=12 V−I D(2 K Ω)I D=0→V GS=12VV GS=0→ ID=6 mA

I DQ=2 .75 mAV GS=V DSQ

=6. 4 V

Graphical Approach:

→V GS=V G+ I D RS=−4 . 55V + I D(1.8 K Ω)I D=0→V GS=−4 .55VV GS=0→I D=2 .53 mA

FET Small-Signal Model

I D=I DSS (1−V GS

V P )2

gm= y fs=ΔI D

ΔV GS|V DS=const=

2 I DSS

|V P| (1−V GS

V P )=gmo(1−V GS

V P )

Input Impedance of the FET:

(the typical values: JFET

Output impedance of the FET:

rd=ΔV Ds

ΔI D= 7 V

0.5 mA=14 kΩ

Zi (FET )=∞

¿109Ω , MOSFET≃1012−1015Ω)

Zo( FET )=rd=1

yos

FET Small-Signal AnalysisCommon-Source Circuit

Zi=R1||R2

V o=−( gmV gs )( RD||rd )=−( gm V i )(RD||rd )→Av=V o

V i=−gm( RD||rd )

rd=∞

V gs=V i−gmV gs Ralignl¿ s ¿¿

¿→V i=V gs (1+gm Rs ) ¿V o=−( gmV gs ) RD ¿ Av=V o

V i=−

gm RD

1+gm R s¿ ¿

rd≠∞

V gs=V i−I o R s

I o=gmV gs+V o−V s

r d=gm V gs+

−I o RD−I o R s

rd

¿gm(V i−I o R s )+−I o RD−I o R s

rd

→ I o=gmV i

1+gm R s+(RD+R s )r d

V o=−I o RD=−gm RD V i

1+gm R s+( RD+R s )rd

→ Av=V o

V i=−

gm RD

1+gm R s+(RD+R s )r d

Common-Drain (Source-Follower) Circuit

Zi=RG

V i=0→Z o=RS||rd||1gm

Common-Gate Circuit

V o=−( gmV gs) RD=−gm(−V i )RD→ AV =V o

V i=gm RD

Zi=RS||1gm

V i=0→Z o=RD||rd

Enhancemen MOSFET Amplifier

V o=gmV gs( RS||r d )=gm(V i−V o )( RS||rd )→Av=V o

V i=

gm( RS||rd )2+g

m( RS||r d)

V o=( I 1−gmV gs)( RD||r d )=(V i−V o

RG−gm V i)( RD||rd )

→AV=VoVi

=(1−gm RG)( RD||rd )RG+RD||r d (for gm RG>>1 )

(for RG >>RD or rd

¿−gm RG(RD||r d )RG+RD||rd

=−gm(RG||RD||rd )

¿−gm( RD||r d )

I i=V i−V o

RG=

V i (1−V o

V i)

RG→Z i=

V i

I i=

RG

1−AV=

RG

1−(−gm( RD||rd ))=

RG

1+gm( RD||rd ))V i=0→RD||rd||RG≃RD||rd

System Approach-Effects of RS and RL

Bypassed Source Resistance

Unbypassed Source Resistance

Source Follower

Common Gate