Stability Analysis of Two-Stage PFC PowerSupplies

Octavian Dranga*, Grace Chu, Chi K. Tse, and Siu-Chung WongDepartment of Electronic and Information Engineering, Hong Kong Polytechnic University, Hong Kong

*Now with School of Engineering, James Cook University, Northern Queensland, Australia

Abstract- Power-factor-correction (PFC) power supplies arerequired to provide high input power factor and tight outputvoltage regulation. The usual configuration takes a two-stage

PFCdc/dc

cascade structure, consisting of a PFC preregulator and a dc/dc ac buckconverter. Previous studies of the dynamical behaviour mainly pre-regulator converterfocused on the boost PFC preregulator, assuming that it is mainsbeing terminated by a resistive load. However, in practice, asthe PFC preregulator is terminated by a dc/dc converter whosecharacteristics differ from resistive load's, the assumption of average voltageresistive load termination gives rather inaccurate information cabout the stability of the system. In this paper we study mode fdthe complete two-stage PFC power supply and show that the one controlinteraction between the PFC stage and the dc/dc converter stageplays an important role in determining the stability of the system.

Fig. 1. Two-stage PFC power supply

I. INTRODUCTION II. Two-STAGE PFC POWER SUPPLIES

A power supply with input power factor correction (PFC) A block diagram of the two-stage PFC power supply istypically consists of a preregulator for PFC, cascaded with depicted in Fig. 1. The objective of active PFC is to makea dc/dc converter stage for output regulation [1], [2], [3]. the input to the power supply look like a simple resistorThe two stages can be separately controlled to achieve PFC and the PFC preregulator does this by programming the inputand tight output regulation. Moreover, for ease of controller current in response to the input voltage. In practice, a boostintegration, the control of the two stages can be merged converter has been a favorable and popular choice for the PFCin a combo integrated circuitry, e.g., Fairchild ML8424 [4]. preregulator. Although the discontinuous conduction modeSuch combo control, characterized by a shared frequency (DCM) has the obvious advantage of simplicity since noand possible synchronization of the switching period, causes additional control is required, it is limited to relatively lowerstability problem which is not predicted with the usual analysis power ranges. The CCM considered in the present study isthat assumes the cascading dc-dc converter being a resistive more suited for applications in higher power ranges. For CCM,load [5], [6]. moreover, feedback is necessary to program the input current

Previous studies have mainly focused on the dynamical to follow the input voltage waveform. Typically a peak currentbehaviour and stability boundaries of the boost PFC pre- mode control or average current mode control may be used.regulator operating in continuous conduction mode (CCM) Peak current mode control gives rise to problems such asand revealed both slow-scale [5], [6] and fast-scale [7], [8] poor noise immunity, need for slope compensation, poor factorinstabilities. In this paper, we show however that extending the correction due to significant errors between the programmingresults concerning the stability of the boost PFC preregulator signal and the input current. Average current mode (ACM)with a resistive load to the practical two-stage circuit can be control eliminates these problems, is commonly available onmisleading, particularly with the combo control. Specifically, monolithic control ICs and is therefore the control methodwe will show by computer simulations that it is possible for considered here.the complete two-stage PFC power supply, with both the boost The boost PFC preregulator typically gives a high outputPFC preregulator and the buck output regulator designated to voltage which is greater than the highest expected peak inputoperate in CCM, to suffer from slow-scale instability even voltage and provides very crude regulation. Consequently, awhen the control parameters assure the individual stability of buck converter (in the form of a transformer-isolated forwardeach of the two constituent stages. The results point to the converter) is needed to step this voltage down to a useablenecessity of investigating thoroughly the detailed dynamical level and to provide tight output regulation. The buck converterbehaviour and the stability boundaries of the two-stage PFC may operate in either modes, and is controlled via a voltagepower supply and the importance of treating it as a whole in feedback loop. The CCM case is considered in this study,doing so. since this operation mode, at the expense of a larger inductor,

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LI DI VPFC S2 L2

Vi. SI2 C, T2X2 R2

PWM Y"~~~~~~~~~~~~~~orefsignal PWM signal

+ TF2~~~~+GF[11

Fig. 2. Schematic of a two-stage PFC power supply, with CCM boost preregulator under ACM control and a CCM buck converter under voltage feedbackcontrol.

TABLE I

CIRCUIT PARAMETERS USED IN SIMULATIONS.I __

k~ ++

Parameters Values JRectified line voltage vi 70 Vrms, 50 H4z El()IS/ 1 |R VFBoost stage inductance L1 1 mH vBoost stage capacitance Ci 60sp Mpnl 1a 1Boost switching period §111 10 ,usD' ,,,,Reference PFC P Msga

output voltage VPFC,ref 240V/\PI current controller gain k 5.12P current controller time constantTi 0.12 ms IBoost stage gain GF1 (nominal) 8.0 7 IBoost stage feedback Te

time constant TF1 (nominal) 8.6 ms ____1 -Buck stage inductance L2 1 mHBuck stage capacitance C2 60 ,uF iL+Buck switching period TI2 5 ,uS VPwassefReferenceoutput voltage Vo,ref 24 V

iS usually more efficient and the current stress on the activeswitch is lower. Fig. 3. Circuit schematic used in previous studies assuming the PFC stage

The circuit schematic of the two-stage PFC power suppiy being terminated by an equivalent resistive load.under study is shown in Fig. 2. Here, we omit the isolationtransformer for simplicity. The power circuit of the boost PFC output p of the voltage error amplifier is divided by the squarestage is the same as that of a boost converter. Its control of the RMS value of the input voltage before it is multipliedcircuitry must control both the input current LLI and the PFC by the rectified line voltage. The output of the multiplier is theoutput voltage VpFC. Accordingly, the average current mode current programming signal, which hereby has the shape of the(ACM) control used is a two-loop system [9]. The current input voltage and an average amplitude which controls the PFCloop, employing a PI controller and generating the switching output voltage. The squarer and divider circuits keep the gainsignal through a pulse-width modulation (PWM) scheme, is of the voltage loop constant; without it the gain of the voltageprogrammed by the rectified line voltage vPFso that the input loop would change as the square of the RMS value of theto the converter will appear to be resistive. The PFC output input voltage. The circuits which keep the loop gain constantvoltage is controlled by changing the average amplitude of make the output of the voltage error amplifier a power control,the current programming signal,refe In this voltage loop the since it actually controls the power delivered to the output

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200- - ----- T F BUCK CONTROLLER: Pi150 ....-T.. ---^---- S ABLE OPERATION

10 26 G~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~F2=lOO5 ~~~~~~~~~~~~~~j 1/ - _______________~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

2

&9 091 0~92 0093 094 095 0,9 097 09 0~90 1 F~~230 slow-scale

AkAk~~~~~~~~~~~~~> period-doubling

~~~~~~~~~ 1( ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1.8-

ii9O~1 092 U3 0;4 OQ .9 0 XOM9 9 1.6-

"N~~~~~10 60 70 80 90 100 110 120 130 140 15040c --- power(W )395 ----..-- ---BUCK CONTROLLER: PI

38B ~~ ~ ~ I I2.2-~J9 0.91 OM~ 0.9. 0.94 0,95 0.9 0 7 O.9 0.M 1 STABLE OPERATIONthme (§ec) 2.1-'

Fig. 4. Simulated waveforms from boost PFC stage with resistive terminationin stable operation. Upper: input voltage; middle: inductor current; lowr 9 C-3ncapacitor voltage. .8period-doubling

200

1.6

1.5____ ____ ___ ____ ___ ____ ____ ___ ____ ___ ____ ___U STA BLE PERA TIOT9 0.91 O~92 0A.3a94 0~95 0.96 a97 O~98 O~99 1 50 60 70 80 90 1100 1110 1120 130 1140 150

power (W)

BUCK CONTROLLER:.Pi19

UNSTABLE OPERATION1~~~~~~~~~7420 slow-scale-

period-doubling --

400 m ~~~~~~~~~~~~~~~~~~~~~~~~~~~~14-

0. 04 09 098 09~~~~~~~~~~~~~~~~~~~~~~~~~~4 13

0.90.91 - ~~~~~~~~~~ tune (sec) - F2=6 G F2 80

4 I I I ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~10--9

47.8 STABLE OPERATION GF2=0%O 60 70 80 90 100 1 10 120 130 140 150

~4T6 power (W)47A ~~~~~~~~~~~~~~~~~~BUCKCONTROLLER: Pi

18-

4 ________ _ _ _ UNSTABLE OPERATION-W9 0.91 0.92 09 0194 095 0% 097 ;8 9 17-

16-

48____- slow-scale-

period-oubling ---4T8 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~14-

12

11 - - t~~~~ ~ ~~~~~~~~~~~~~~~~~~~~~~~F23 tF22

10

;.9 U19 0.92 OM 194 0A5 06 U~97 0~98 OM 19timie (sc _____ STABLE OPERATION F2

%O 60 70 80 90 100 110 120 130 140 150power (W)

Fig. 5. Simulated waveforms from the two-stage PFC power supply showing"unstable" slow-scale period-doubling phenomenon. From top to bottom: Fig4. 6. Stability boundaries for boost PFC converter assuming resistive

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BUCK CONTROLLER: PI than that deduced previously in [5], [6] for the PFC stage19 ,- terminated with resistive load. This is more readily seen from18-

17 -, Fig. 6, which compares the stability boundaries of the boost17 .-,916 UNSTABLE OPERATION ,, PFC assuming resistive termination and the two-stage circuit~15 m m ,,"'in the parameter space defined by various parameters and the14 ,"' output power, for a few sets of feedback parameters of the13 buck converter. Also, Fig. 7 shows the stability boundaries for

~~12- -- - ~~~~~~slow-scaledifrnduynthspc12 , pisod-li different steady-state duty cycles in the parameter space of0 ---/ period-doublingDbk2°

D11 / GF1 versus output power.10 ,

8_____________ STABLE OPERATION Dbuck=5% IV. EXPERIMENTAL VERIFICATIONS5060 70 80 90 100 110 120 130 140 150

power (W)

An experimental circuit has been constructed for verificationFig. 7. Stability boundaries for boost PFC converter assuming resistivetermination (dashed line) and terminated by buck converter under PI control purposes. The PFC stage is a boost converter under average(solid line) for different steady-state duty cycles. current-mode control, which is then cascaded with a forward

converter. The PFC control of the boost stage is accomplishedThe same parameters are indicated for the feedback circuit by UC3854A and the forward converter is controlled by a

of the buck converter, whose output voltage v0 is regulated at standard UC3825N PWM controller with a simple PI com-its desired value VO,ref by voltage-mode PWM control. Table I pensator. The circuit is thus exactly as the one analyzed inlists the operating parameters used in the present study. Both the previous section. The experimental PFC power supply isthe boost PFC preregulator and the buck regulator are designed shown in Fig. 8.to operate in CCM. For comparison, we show here the measured stability

boundary curves corresponding to variation of the PFC stageIII. STABILITY ANALYSIS BY SIMULATIONS feedback gain and the VpFc/Vi4 conversion ratio. The input

The detailed investigation of the dynamical behaviour of the voltage is 70 V rms, the output of the PFC stage is set at 240practical two-stage PFC power supply can be challenging due V DC, and the output voltage is 9 V. Figure 9 (a) comparesto the complex interaction between the two stages. A way of the boundary curves of the resistor terminated PFC stage andreducing complexity is to replace the tightly regulated dc/dc the complete two-stage power supply in the parameter spacebuck converter by a resistive load with same power dissipation. of GF1 versus output power, and Fig. 9 (b) compares theMost previous studies analysed the phenomena in the boost boundary curves of the complete two-stage power supply forPFC converter feeding a purely resistive load and operating in different values of the duty cycles. Figure 10 compares theCCM, as depicted in Fig. 3. Consequently, some results are the boundary curves of the resistor terminated PFC stage andavailable for this circuit [5], [6]. The main objective of the the complete two-stage power supply in the parameter space ofpresent study is to investigate to what extent can these results VPFC/1i, versus output power. Here, the value of Vh, actuallybe considered still valid when applied to the actual two-stage changes in order to vary VPFC/Vn4. All results verify the basiccircuit. phenomenon that the PFC stage loaded by a forward stage is

Fig. 4 shows the simulated waveforms for a stable operation less stablewith GF1 = 225 and T= 8.5 ms for the boost PFC converter(Fig. 3) with the resistive load R1 = 100 Q at the same V. CONCLUSIONSpower level. The CCM input current (middle waveform) isprogrammed by the input voltage (upper waveform) to be a In analysing PFC power supplies, previous studies havehalf sine wave, achieving a near unity power factor. The PFC assumed a resistive load termination for the PFC boost stage.output voltage (lower waveform) is a sine wave at twice the However, in practice, the PFC boost preregulator is almostAC line voltage, as expected. always cascaded with a voltage regulator. In this paper, a

In order to verify whether the two-stage circuit exhibits comparative study has been performed for the two circuitthe same stable operation, the buck converter is reinstated models, allowing the identification of the effects of the inter-in the second stage, achieving a tight output regulation for action between the two stages on the stability findings. It hasgain GF2 = 10 and bandwith 1.6 kHz (TF2 = 0.1 ms). been shown that the assumption of resistive load terminationHowever, the simulation results in Fig. 5 show a slow-scale for the PFC stage produces inaccurate stability information.period-doubling phenomenon in the dynamics of the boost The actual two-stage PFC power supply is more prone toPFC preregulator (upper three waveforms), the period of the instability. Intuitively such a result is expected since the dc/dcwaveforms becomes equal to the mains period, which can also converter stage represents a constant power load when itsbe detected in the waveforms of the buck output regulator output is perfectly regulated. This is equivalent to a negative(lower two waveforms). resistance presented to the PFC stage in the small-signal sense,

The stability operation of the actual circuit is more restricted which jeopardizes the overall system stability.

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ImH IRFL460

I M STW26NM60STW26N VPFC

460 ~ APT15D60B O-lmil VoSTW26N VPFC ~~~~~~3:1M60~~~~~54ttF load

5OHz 60lUttFA ' t _460 ~~~~~APT1 5D60B

0.125) fSTW26NM60I~~~~~~~~~~~PFC Control sycple PWM Control_UC3854A sync pulse UC3825N _

Fig. 8. Experimental circuit of the resistor terminated PFC boost stage. For the complete power supply, resistor R is removed and the PFC stage is connectedto a standard forward converter.

12 l3 .6STABLE

11- OPERATION1UNSTABLE Resistance terminated 3.410 OPERATION PFC stage

3.2 Complete two-stage PFC9 power supply

E-O 3v8-

2.8-

2.6-62 > UNSTABLEComplete two-stage PFC OPERATION

5P power supply 2.4

4STBL

2.2-~/ S~~~~~~~~~~PRTABLE Resistance terminated3 2- PFC stage

20 22 24 26 28 30 32 34 36 38 40 42 4445 IC8PFC Output power/W 30 32 34 36 38 40 42 44 46 48 50PFC Output power /W

(a)Fig. 10. Measured stability boundaries in the space of VPFC/Vin vs power.

12

11 UNSTABLEOPERATION

10 0, 582, 1994.30% Duty cycle [2] C.K. Tse, "Circuit theory of power factor correction in switching

9 20%Dutycycle- converters," nt. J Circuit Theory Appl., vol. 31, no. 1, pp. 157-198,11% Duty cycle11% Duty cycle\

OPSTABLE [3] V.J. Thottuvelil, D. Chin, and G. Verghese, "Hierachical approaches

to modeling high-power-factor ac-dc converters," IEEE Trans. Power6- Electron., vol. 6, no. 2, pp. 179-187, March 1991.

[4] "ML4824, A novel method for an off-line PFC-PWM combo controller,"5- ;/rt -Application Note 42045 Rev. 1.0, Fairchild Semiconductor, pp. 1-12,4 _J* 2000.

[5] S.C. Wong, C.K. Tse, M. Orabi, and T. Ninomiya, "The method of3- 0 0 0double averaging: an approach for modeling power-factor-correction2 2 2 2 2 3 3 3 3 3 4 42 power converters," IEEE Transactions on Circuits and Systems I, vol. 53,20 22 24 26 28 30 32 34 36 38 40 42 4445 no. 2, pp. 454-462, Feb. 2006.PFCOutputpower /W [6] M. Orabi and T. Ninomiya, "Nonlinear dynamics of power-factor-

(b) correction converter," IEEE Trans. Ind. Electron., vol. 50, no. 6,pp. 1116-1125, Dec. 2003.

Fig. 9. Measured stability boundaries in the space of GF1 vs power. (a) [7] 0. Dranga, C.K. Tse, H.H.C. Iu, and I. Nagy, "Bifurcation behavior ofComparison of resistor terminated PFC stage and 2-stage power supply; (b) a power-factor-correction boost converter," Int. J Bifur. Chaos, vol. 13,comparison of 2-stage power supply for various duty cycles, no. 10, pp. 3107-3114, 2003.

[8] H.H.C. Iu, Y. Zhou, and C.K. Tse, "Fast-scale instability in a pfc boostconverter under average current-mode control," Int. J Circuit Theory

REFERENCES Appl., vol. 31, no. 6, pp. 611-624, Nov. 2003.[9] L.H. Dixon, "High power factor preregulator for off-line supplies,"

[1] R. Redl, "Power factor correction in a single-stage switching-mode Untrd Poe Supl DeinSmnrMna.E60 98power supplies an overview," Int. A Electron., vol. 77, no. 5, pp. 555-

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