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4882 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 12, DECEMBER 2009

An Improved ACDC Single-Stage Full-BridgeConverter With Reduced DC Bus Voltage

Pritam Das, Shumin Li, and Gerry Moschopoulos,Member, IEEE

AbstractA new acdc single-stage voltage-fed pulsewidth-modulation (PWM) full-bridge converter is proposed in this paper.The converter can simultaneously perform input power factorcorrection and dcdc conversion using conventional phase-shiftPWM and can maintain a primary-side dc bus voltage of lessthan 450 V even at a high input line voltage of 265 Vrms. Thisis a combination of features that few, if any, other converters ofthe same type have. The proposed converter has these featuresdue to the novel implementation of an asymmetrical auxiliarytransformer winding that is placed in series with the input in-ductor and acts as a boost switch. In this paper, the operationof the proposed converter is explained in detail, its outstanding

features are discussed, and a detailed design procedure is givenand demonstrated with an example. Experimental results thatconfirm the feasibility of the converter and its ability to meetIEC1000-3-2 Class D standards for electrical equipment are alsopresented in this paper.

Index TermsACDC power conversion, full bridge, magneticswitch, power factor correction (PFC), single-stage converters.

I. INTRODUCTION

ACDC rectifiers are usually implemented with a boost

converter that performs power factor correction (PFC)

as the front-end converter and an isolated dcdc converter

that produces the required output voltage. The dcdc converter

is typically a flyback or a forward converter for low-powerapplications and a full-bridge converter for higher power appli-

cations. ACDC rectifiers can be used as stand-alone converters

or can be used as paralleled modules.

Due to the cost and complexity involved in implementing two

separate switch-mode converters, there has been considerable

interest by power electronics researchers to try to combine

both acdc PFC and isolated dcdc conversion into a single

converter. As a result, there have been numerous publications

on the topic of single-stage acdc converters, particularly for

low-power (


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DAS et al.: IMPROVED ACDC SINGLE-STAGE FULL-BRIDGE CONVERTER WITH REDUCED VOLTAGE 4883

control, which makes it difficult to optimize their de-

sign as they must be able to operate over a wide range

of switching frequency. For example, the characteris-

tics of the voltage-fed resonant converters proposed in

[20][24] with respect to the dc bus capacitor voltage

are dependent on the fine tuning of the resonant tank

components.4) They are current-fed converters with a boost inductor

connected to the input of the full-bridge circuit [24]

[26]. They can achieve a near-unity input pf but lack

an energy-storage capacitor across the primary-side dc

bus. The absence of such a capacitor can result in the

appearance of high voltage overshoots and ringing across

the dc bus whenever a converter switch is turned off,

unless some preventative measure is implemented, which

results in a loss of efficiency. It also causes current-fed

single-stage converters to have an output voltage with a

large low-frequency 120-Hz ripple that restricts their use

to applications where a tightly regulated output voltage is

not required.

In [27], a promising single-stage voltage-fed PWM full-

bridge converter was proposed, but its characteristics were not

well known, and thus, its strengths were not properly taken

advantage of; this topology will be the focus of this paper.

In this paper, the operation of the converter is explained and

analyzed in detail, its outstanding features are discussed, and

a detailed design procedure is given and demonstrated with

an example. Experimental results that confirm the feasibility

of the converter and its ability to meet IEC1000-3-2 Class D

standards for electrical equipment [30] are also presented in

this paper. The proposed single-stage voltage-fed PWM full-bridge converter has none of the aforementioned drawbacks

and is, thus, superior to other previously proposed converters of

the same typeincluding converters such as the ones proposed

in [11], [16], [18], and [19] in previous editions of these

transactions.

II. CONVERTERO PERATION

The converter shown in Fig. 1 operates like a standard PWM

full-bridge converter. Energy is transferred from the dc bus

capacitorCb whenever a pair of diagonally opposed switches

is on. No energy is transferred when the converter is in afreewheeling mode of operation, where the two top switches or

the two bottom switches are both on and the voltage across the

transformer primary is zero. By appropriately alternating the se-

quence of energy transfer and freewheeling modes, an ac square

voltage is impressed across the transformer primary winding,

which is then stepped down by the transformer, rectified by

the output diodes, then filtered by the output inductorcapacitor

(LC)filter to produce an output dc voltage.While it is performing dcdc conversion, the converter is

also performing input PFC due to the transformer winding

Naux, which is an auxiliary winding taken from the main powertransformer. A voltage is impressed across the main transformer

primary winding whenever switches S2 and S3 are on. Thepolarity of this voltage is such that it causes a voltage with a

Fig. 1. Proposed single-stage full-bridge converter.

Fig. 2. Discontinuous input current waveform.

polarity that counteracts the dc bus voltage to appear across the

auxiliary winding so that a net positive voltage is impressed

across the input inductor and the input current rises. When the

converter operates in a freewheeling mode of operation so that

the voltage across the main primary transformer winding is zero

or when switches S1 and S4 are on so that this voltage is ofdifferent polarity, then the net voltage across the input inductor

is negative, and the input current falls.

The rise and the fall of the inductor current during a converter

switching cycle are analogous to that of the inductor current in

a boost converter. Activating the asymmetric auxiliary winding

will counteract the dc bus capacitor voltage, which is the same

as turning the boost-converter switch on in a boost converter.

Deactivating the asymmetric auxiliary winding will impress

the dc bus capacitor voltage at the right-hand end of the input

inductor in Fig. 1, and this is the same as turning the boost-

converter switch off. The winding is asymmetric, as the input

current rises only when switchesS2

andS3

are on. The inputcurrent in the proposed converter can be shaped to improve

the input pf, as can be done in a standard acdc boost PFC

converter. If the input current is made discontinuous, as shown

in Fig. 2, then an excellent input pf can be achieved.

The proposed converter goes through several modes of op-

eration during a switching cycle. Typical converter waveforms

for a single switching cycle with a discontinuous output current

and a discontinuous input current are shown in Fig. 3, and

the equivalent circuit diagrams for each mode of operation are

shown in Fig. 4. The converter goes through the following

modes of operation during a switching cycle.

Mode 1 (t0t1): In this mode, S2 and S3 are on, and

auxiliary diodeDaux1 and output diodeD1are forward biased.The current in the output inductor is rising and so does the input


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Fig. 3. Typical waveforms describing the modes of operation.

current ifvs,k > NxVbus(Nx = Naux : N1); otherwise, therewill be no current in the input inductor. The slope of the risinginput current can be expressed as

diin,kdt

= vs,k+ (Nx 1) Vb

Lin. (1)

At the end of this mode, the input current reaches a peak of

Iin,k(t1) = [vs,k+ (Nx 1) Vb] D Tsw

2Lin(2)

where vs,k is the magnitude of the rectified input voltage atthek th switching period, Nx= Naux : N1, whereNaux is the

number of turns on the auxiliary winding andN1is the numberof turns on the primary winding,Vbis the dc bus voltage acrossenergy-storage capacitor Cb, D is the duty ratio, and Tsw isthe switching period. The slope of the output current can be

described by

diout,kdt

=VbN VoLo

(3)

and it reaches its peak value at the end of the interval when

t= t1. The output current is discontinuous, and its peak valuecan be expressed by

Iout,k(t1) = 12 V

bN Vo

DTswLo

(4)

where N is the turns ratio of the primary winding N1 to thesecondary windingN2,Vo is the regulated output voltage, andLois the output filter inductance current.

Mode 2 (t1t2): At t1, S2 is turned off, and the primarycurrent starts to charge and discharge switch capacitors Cs2andCs1; this mode ends with fully charging and discharging ofCs2

andCs1.Mode 3(t2t3): At the start of this mode, the output current

starts freewheeling through D1 andD2 and so does the inputcurrent through Daux2 and Daux1, charging up the dc buscapacitor. In this mode, the input and the output currents are

decreasing, and the transformer primary current freewheels

throughS1 and S3. Sometime during this mode, S1 is turnedon with zero-voltage switching (ZVS). This mode ends with the

output current reducing to zero. The negative voltage vs,k Vbacross inductor Lin forces the current to fall linearly with aslope of

diin,k

dt =

vs,k Vb

Lin . (5)

The input currentIin,k(t2)att = t3is

Iin,k(t3) =Iin,k(t2) +(vs,k Vb)(1 D)Tsw

2Lin. (6)

Also, during this interval, the output inductor current Iout,kfallswith a slope of

diout,kdt

= VoLo

. (7)

Mode 4(t3t4): In this mode, the input current continues todecrease, freewheeling through Daux1 andDaux2. This modeends with the turning off ofS3.

Mode 5(t4t5): This mode begins with the primary currentcharging and discharging switch capacitors Cs3 and Cs4 andends with the full charging and discharging of these capacitors.

Mode 6 (t5t6): During this mode, the primary currentflows through the body diodes of S1 and S4, and the inputcurrent continues to flow throughDaux2 due to the asymmetryof the transformer auxiliary winding. This mode ends with the

turning on of S4 with ZVS. The slope of the input current,which is still decreasing in this mode, is given by

diin,kdt

= vs,k VbLin

. (8)

Mode 7(t6t7): The primary current flows through switchS1 and the body diode of S4 during this mode, while theinput current decreases as it flows through Daux2. This modeends with the body diode current in S4 reducing to zero andeventually flowing through the switch. The output capacitor

feeds energy to the output load fromt3to t7.Mode 8(t7t8): During this mode, the output current rises

again, flowing throughD2, and the input current still decreasesas it flows through Daux2. This mode ends with the inputcurrent reducing to zero.

Mode 9 (t8t9): The output current continues to increaseduring this mode, and there is no current flowing in the input


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Fig. 4. Equivalent circuit diagrams for the modes of operation.


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Fig. 5. Single-stage voltage-fed PWM converter proposed in [11].

section of the converter. This mode ends with the turning

off ofS1.Mode 10(t9t10): This mode begins with the transformer

primary current charging and discharging switch capacitors Cs1andCs2 and ends with the complete charging and dischargingofCs1 and Cs2.

Mode 11(t10t11): The output current freewheels throughD1 andD2 during this mode. This mode ends with the outputand the transformer primary currents reducing to zero. S2 isturned on with ZVS sometime during this mode.

Mode 12 (t11t12): There is no current flowing in theconverters input section, the full-bridge circuit, and the output

diodes during this mode; the output capacitor feeds the load.

Sometime during this mode,S4 is turned off with zero-currentswitching (ZCS). This mode ends with S3 getting turned onwith ZVZCS, and a new switching cycle is commenced.

III. CONVERTERC HARACTERISTICS

The concept of using an auxiliary transformer winding to

simulate a boost switch so that the input current can rise

and fall appropriately to ensure a very good input factor has

been proposed for use in a number of low-power single-stage

acdc flyback and forward converters [2], [4], [10]. It has,

however, never been implemented in a single-stage voltage-

fed PWM full-bridge converter with the sole exception of the

one proposed in [11]. It is the use of an auxiliary winding as a

magnetic switch that allows standard phase-shift PWM control

to be used, and the converter in [11] has been the only single-

stage full-bridge converter that can operate with this control.

The converter that was proposed in that paper, which is shown

in Fig. 5, can only operate with a very high dc bus voltage thatwas almost 600 V under high-line conditions. The differences

between these two converters will be explained in this section.

A. Difference in Number of Auxiliary Windings

The auxiliary windings in both the proposed converter and

the converter proposed in [11] can be considered to be like

switches that conduct current during the time that a voltage

of appropriate polarity is impressed across the transformer

primary.

Consider the operation of the dcdc full-bridge section

of both converters during a single switching cycle. In bothconverters, a voltage of one polarity is impressed across the

transformer; then, a freewheeling mode occurs when no voltage

is impressed; thereafter, a voltage of the opposite polarity

is impressed across the transformer primary; finally, another

freewheeling mode occurs.

For the proposed converter, the sequence of events from the

point of view of the converters input section that matches this

sequence is as follows: The auxiliary winding switch Naux ison, the auxiliary winding switch is off, the auxiliary winding

switch is off, and the auxiliary winding switch is off.

For the converter proposed in [11], the sequence of events

from the point of view of the converters input section that

matches the sequence at the dcdc full-bridge section is as

follows: The auxiliary winding switch Naux1 is on, bothauxiliary winding switches are off, the auxiliary winding

switchNaux2 is on, and both auxiliary winding switchesare off.

By referring to the typical waveforms shown in Fig. 3, it

can be seen that the rise and the fall of the input current

in the proposed converter occur once during a full switching

cycle due to the fact that the converter has only one auxiliary

winding switch. The rise and the fall in the current in the

output inductor, however, occur twice during a switching cycle.

For each rise and fall of the input inductor current, energy is

transferred from the ac source to the dc bus capacitor, whereas,

for each rise and fall of the output inductor current, energy is

transferred from the dc bus capacitor to the output load. During

each switching cycle, energy is transferred from the ac source

to the dc bus once, whereas energy is transferred from the dc

bus capacitor twice. It is a fact that there is only one auxiliary

winding that causes this 1 : 2 ratio of energy input to the dc bus

capacitor to energy output to exist.

By comparison, the converter proposed in [11] has twoauxiliary windings so that the rise and the fall of the input

current will occur twice in a switching cycle, just as the rise

and the fall of the output inductor current does. It is a fact that

there are two auxiliary winding switches that cause this 2 : 2

(or 1 : 1) ratio of energy input to the dc bus capacitor to energy

output to exist.

The dc bus voltage in single-stage converters is uncontrolled,

as these converters have only one controller that is used to

regulate the output voltage. This voltage is, instead, depen-

dent on the energy equilibrium that must exist at the dc bus

capacitorthe amount of energy or charge that is fed into this

capacitor must be equal to the amount of energy or charge thatis removed from the capacitor during a half line cycle (half of

a 60-Hz cycle because the input line is rectified by the diode

rectifier).

The fact that the proposed converter has a 1 : 2 ratio of energy

input to the dc bus capacitor to energy output instead of a 1 : 1

ratio, which is what the converter proposed in [11] has, means

that this capacitor is allowed to discharge more frequently than

it is allowed to be charged. This affects its energy equilibrium

so that its voltage is lower than that of the converter proposed in

[11]. In summary, the use of a single auxiliary winding, instead

of the two that are used in the converter proposed in [11], helps

reduce the dc bus voltage so that it is easier to ensure that it

does not exceed the 450-Vdcstandard that has been accepted inthe literature.


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Fig. 6. Input voltage waveform and input current envelope showing the deadangle .

B. Difference in Auxiliary Winding/Transformer Primary

Winding Turns Ratio

Unlike the converter proposed in [11], the auxiliary winding

in the proposed converter is designed so that it does not com-

pletely cancel out the voltage across the dc bus capacitor. This

means that some, but not all, of the diode bridge rectifier output

voltage is placed across the input inductor. This can reduce the

amount of energy placed in the input inductor when switches S2and S3are on, which, in turn, reduces the amount of energy thatis transferred to the dc bus capacitor during the time when both

these switches are not on. The reduction in energy placed into

the input inductor affects the energy equilibrium of the dc bus

capacitor in a way that reduces the dc bus voltage and makes it

lower than what it is in the converter proposed in [11].

The input section of the converter is made to operate indiscontinuous current mode so that a high pf is achieved.

Making the number of auxiliary winding turns different from

the number of transformer primary winding turns, however,

introduces deadband regions in the zero-crossing sections of the

input current waveform, as shown in Fig. 6. This is because the

diode-bridge diodes are reverse biased when the input voltage

is low, and current is not allowed to flow in the input inductor

as the dc bus voltage is not fully cancelled out by the auxiliary

winding.

This means that a compromise must therefore be made

between the input pf and the dc bus voltage reductionthe dc

bus voltage of the proposed converter can be kept lower than450 Vdc but with some current distortion. The converter can

be designed to operate with a near-unity pf but with a dc bus

voltage which may be greater than 450 Vdc yet still lower than

that of the converter proposed in [11].

C. Transformer Primary Current DC Offset

The fact that the proposed converter has a single auxiliary

winding means that its transformer primary current will have

some dc offset. Current can flow through the auxiliary winding

when the voltage across the transformer forward biases Daux1and reverse biases Daux2, but current cannot flow through

the winding when the voltage across the transformer windingforward biasesDaux2 and reverse biasesDaux1.

When current flows through the auxiliary winding, the trans-

former primary current is the sum of the reflected current

from the secondary and that from the auxiliary winding. When

current does not flow through the auxiliary winding, the pri-

mary current is only the reflected current from the secondary.

The transformer should be designed to accommodate this dc

offset like any other transformer that must operate without fulldemagnetization.

Due to the presence of the auxiliary winding and the way it

is implemented, the proposed converter is currently the only

voltage-fed single-stage acdc full-bridge converter that can

operate with standard phase-shift PWM and with a dc bus

voltage that does not exceed the standard accepted voltage of

450 Veven if its input voltage is the maximum high line

voltage of 265 Vrms.

IV. CONVERTERD ESIGN

A procedure for the design of the converter is presented

in this section and is demonstrated with an example. For the

example, the converter is to be designed according to the fol-

lowing specifications: output voltageVo= 48V, input voltageVin = 90265Vrms, output power Po = 600W, and switchingfrequency fsw = 1/Tsw = 50kHz. The dc bus capacitor shouldnot exceed 450 V for any operating condition. Since the design

will follow IEC1000-3-2 Class D standards for harmonic con-

tent, a pf ranging between 0.88 and 0.95 and a total harmonic

distortion (THD) that is less than or equal to 45% will be

considered acceptable [2].

Step 1Establish Appropriate Value for Maximum

Converter Duty Cycle Dmax: The maximum duty cycles

Dmax that the converter can operate with are determined bythe switch and the controller that are used. A typical value of

Dmax would be 0.7, as many controllers for phase-shift PWMfull-bridge converters use current-sensing transformers that

require a certain amount of time to reset [2], [11], [29]. The

value ofDmaxthat will be used in this example is Dmax= 0.7.Step 2Determine Value for Output Inductor Lo: The

output inductor should be designed so that the output current is

made to be discontinuous under all operating conditions. This is

to avoid the possibility of the primary-side dc bus voltageVbusto exceed 450 V, which may happen under certain operating

conditionsparticularly if the input inductor is designed so

that the input current is made to be always discontinuous andthus bounded by a sinusoidal envelope. This phenomenon is

common to all voltage-fed single-stage acdc converters and is

explained in detail in [15].

The maximum value ofLo should be the value ofLo withwhich the converters output current will be on the boundary be-

tween being continuous and discontinuous when the converter

is operating with minimum input voltage, maximum duty cycle

(Dmax), and full load (Po,max). If this condition is met, thenthe output current will be discontinuous for all other converters

operating conditions. The maximum value ofLo can thereforebe determined to be

Lo,max= V2o

Po,max(1 Dmax)

2Tsw

2 . (9)


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Substituting Po,max= 600W, Vo = 48V, Tsw = 20 s, andDmax = 0.7 established in Step 1 gives Lo,max = 6 H. Thevalue ofLoshould be close to the maximum to try to minimizethe output peak current but slightly lower to provide some

margin; therefore, a value ofLo = 5H is chosen.Step 3Determine Values for Turns Ratio of Auxiliary

TransformerNx: Nx should be made to be less than one toavoid placing the full input voltage across Lin when energy isto be placed in this inductor. As was explained in the previous

section, not placing the full input voltage acrossLin results inan energy equilibrium at Cbthat results in a lower value ofVbus.IfNxis made to be too low, however, then the input current willbecome very distorted and unable to meet the desired harmonic

standards, as current cannot flow through L in when the inputvoltage is less than (1 Nx) Vbus. The input current willtherefore be a discontinuous waveform that will be confined to

an envelope with deadbands as shown in Fig. 6. The deadband

anglecan be written as

= sin1

(1 Nx)VbusVm

(10)

whereVmis the peak value of the input voltage andVbus is thedc bus voltage.

If it is assumed that the most significant input current har-

monics will be low-order harmonics that are dependent on the

shape of the envelope, then a Fourier series analysis of the

envelope waveform can be performed to derive the following

equations for input pf and THD, as was done in [28]:

pf=2 1

2sin 2

A2(11)

where

A=

2

3

2sin2 + ( 2)sin2 (12)

pf= 1THD100

2+ 1

. (13)

Graphs of the input pf and the THD versus Nx, such asthe ones shown in Fig. 7, can be generated for Vin = 100 and230 Vrms using (11)(13). Vin = 100 and 230 Vrms are thestandard voltages for which harmonic measurements are made

to confirm compliance with IEC1000-3-2 specifications. Thecurves in Fig. 7 will be valid no matter what the load is, as

theVbus in a single-stage voltage-fed converter will not changewith the load ifVin is fixed and if both the input and the outputinductor currents are discontinuous [11], [15].

The values of Vm= 100 1.414 = 141.14 V and Vbus =180 V are used for the 100-Vrms curves, and the values ofVm= 230 1.414 = 325V and Vbus = 360V are used for the230-Vrms curves for the graphs in Fig. 7. TheVbus values thatare used to generate the curves are estimated values but are valid

estimates, as the dc bus voltage must always be just slightly

higher (3040 V) than the input voltage if the Vbus < 450 Vcriterion is to be met over the universal input line range. The

actual values ofVbusmay be slightly higher or lower, and thus,the graphs in Fig. 7 will not be much different. A value of

Fig. 7. Variation of THD (in percent) and pf for different values of auxiliarywinding turns ratio at input voltages of 100 and 230 Vrms.

Nx= 0.7is chosen from these graphs, as it is the highest valueofNxthat ensures that the input current satisfies the harmonicstandard requirements.

Step 4Determine Value for Turns Ratio of Main

TransformerN: The value ofNaffects the primary-side dcbus voltage, as it determines how much reflected load current

is available at the transformer primary to discharge the bus

capacitor Cb. If N is high, then Vbus can be low, but theprimary current may be too high to be practicaldepending

on the switching and conduction losses. If a lower value ofNis used to reduce the primary current, then the primary current

that is available to discharge Cb may be low, and thus, Vbus

may become excessive under certain operating conditions (i.e.,high line).

The minimum value ofNcan be found by considering thecase when the converter must operate with minimum input line

and, thus, minimum primary-side dc bus voltage Vbus,min andmaximum duty cycle Dmax. If the converter can produce the re-quired output voltage and can operate with discontinuous input

and output currents in this case, then it can do so for all cases.

Since Lo was designed in Step 2 to make the output currentdiscontinuous but close to being continuous when the converter

is operating under these conditions, the following constraint

based on standard full-bridge operation can be placed on N:

N Vbus,min

VoDmax. (14)


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TABLE ICOMPONENTVALUES FOR PROPOSEDCONVERTER ANDCONVERTER IN [11]

A value ofVbus = 160 V can be estimated for Vin = 90Vrmsusing the reasoning described in Step 3. Substituting

Vbus = 160 V, Vo = 48 V, and Dmax= 0.7 into (14)results inN 2.3. A value ofN= 2.5is chosen.

With a value of N established, the actual value of Vbuscan now be determined more precisely by using the following

equation, which is based on standard full-bridge operation with

a discontinuous output current:

Vbus,min = NVo+

V2o +

16Po,maxLoTswD2max

2

. (15)

Substituting Vin = 90 Vrms, Po= 600 W, and Dmax = 0.7 intothis equation givesVbus,min = 166V.

Step 5Determine Value for Input InductorLin: The valuefor L in should be low enough to ensure that the input currentis fully discontinuous under all operating conditions, but not so

low as to result in excessively high peak currents. For the case

whereLin is such that the input current remains discontinuousfor all operating conditions, then the average input power can

be expressed as

Pin =

1

|vs,k|is,kdSut (16)

where is calculated from (10), |vs,k| =Vm| sin2fSutk| isthe magnitude of the rectified input voltage at the kth switchinginterval,fSu is the input ac frequency, and

tk= kTsw (17)

is,k=1

8

D2NxLinfsw

|vs,k| + (Nx 1)Vbus

1 |vs,k |Vbus

for |vs,k| >(1 Nx)Vbus = 0

for |vs,k|


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TABLE IIPERFORMANCE FACTOR C OMPARISON BETWEENPROPOSEDCONVERTER ANDCONVERTER IN [11]

Fig. 8. Typical input voltage and current waveforms.Vin = 110Vrms; Po =600W; scale: V = 75V/div., I = 10A/div., and t = 4ms/div.

over the full line cycle but would become continuous at

certain parts of the cycle. This would make the input cur-

rent even more distorted and would reduce the input pf.

4) The switches in the converter proposed in [11] operatewith greater rms currents because the reflected currents

from both the main and the auxiliary windings of the

transformer are higher due to the lower turns ratios of the

main and the auxiliary transformer windings.

5) The secondary output diodes in the converter proposed in

[11] operate with a higher peak voltage because of the

lower main transformer winding turns ratio.

V. EXPERIMENTALR ESULTS

An experimental prototype was built to verify the feasibility

of the proposed converter. It was designed for the follow-ing specifications: input voltage Vin = 90265 Vrms, outputvoltageVo = 48V, maximum output power Po,max = 600 W,and switching frequency fsw = 50 kHz. The converter wasimplemented with the following parameters: Lin = 16 H,Lo = 5H,N =N1 : N2 = 2.5, andNx= Naux : N1 = 0.7.IRFP460 MOSFETs were used for switches S1S4, andDaux1 and Daux2 are implemented with GaAs Schottky diodesDGSK40-025A, while output rectifier diodes are implemented

with GaAs Schottky diodes DGS20-018A. A standard UC3879

IC was used as the controller.

Fig. 8 shows the input voltage and the input current wave-

forms when the converter is operating with Vin = 110 Vrms

and Po = 600W. Fig. 9 shows the transformer primary voltagewaveform when the converter is operating with Vin = 110Vrms

Fig. 9. Typical transformer primary voltage, input inductor current, and outputcurrent at 110-Vrms input and 600-W output. Scale: Vpri = 100 V/div.,ILin = 10A/div., ILo = 5A/div., and t = 10

s/div.

Fig. 10. Typical transformer primary voltage and current waveform.Vin =110 Vrms; Po = 600 W; scale: V = 125 V/div., I = 15 A/div., and t =

5 s/div.

andPo = 600W, along with the input and the output inductorcurrent waveforms. From the waveforms in Fig. 9, it can be

seen that the frequency of the input inductor current is half that

of the output inductor current; this difference in frequency is

due to the asymmetrical auxiliary winding. Fig. 10 shows the

typical transformer primary voltage and current waveforms.

Fig. 11 shows a typical dc bus voltage waveform. Fig. 12

shows the typical auxiliary diode waveforms. Fig. 13 shows the

experimental converter efficiency, which is around 92% at full

load. This is comparable to that of a conventional two-stage

converter.

Fig. 14 shows the dc bus voltage Vbus versus the output loadfor various input voltages; it can be seen that the dc bus voltage


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Fig. 11. Typical dc bus voltage measured at 265-Vrms input and 100-Woutput (V = 60V/div. and t = 10ms/div.).

Fig. 12. (a) Typical voltage and current through auxiliary diode Daux1(V = 60V/div., I = 5A/div., and t = 5 s/div.) and (b) typical voltage andcurrent through auxiliary diode Daux2 (V = 60 V/div., I = 8 A/div., andt = 5 s/div) at 110-Vrmsinput and 600-W output.

Vbus can be kept below 450 V over the required range. Fig. 15shows the input current harmonics when Vin = 100V and Po =600W, which was determined to be the worst case condition forthe harmonic content. It can be seen that the converter can meet

the IEC1000-3-2 Class D standards for electrical equipment. It

was confirmed that the standards were met when Vin = 230V.

The range of the input pf was measured to be in the range of0.890.94 throughout the operating range.

Fig. 13. Experimental efficiency versus output power.

Fig. 14. Experimental dc bus voltage versus output power.

Fig. 15. Input current harmonics compared to IEC1000-3-2 Class D standardwith an output power of 600 W and an input voltage of 100 Vrms.

VI. CONCLUSION

A new acdc single-stage voltage-fed full-bridge converter

has been proposed in this paper. The converter can perform

input PFC using an auxiliary winding taken off of the main

power transformer that acts as a switch. This switch iseither on, causing the input current to rise, or off, causing the


11/12


input current to fall. The winding itself is asymmetrical and is

designed so that the input current frequency is half that of the

output current and so that the switch does not allow the full

input voltage to be impressed across the input inductor.

This novel winding scheme has made the proposed converter

to be the only known single-stage voltage-fed full-bridge con-

verter that can operate with standard phase-shift PWM control,meet the IEC1000-3-2 standards for electrical equipment, yet

maintains a primary-side dc bus voltage of less than 450 V,

regardless of line and load conditions.

In this paper, the operation of the converter has been de-

scribed in detail, and a procedure for the design of the converter

has been given and demonstrated with an example. Experi-

mental results obtained from a prototype have confirmed the

feasibility of the proposed converter.

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[30] Limits for Harmonic Current Emissions (Equipment Input Current

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