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SpW-10X ASIC (AT7910E) Characterisation
Gerald KempfSpaceWire Presentation
Days
ESTEC
25th
September 2008
Outline
Overall GoalsParameters Measured
/ Analysed
Analysis ResultsCharacterisation
Board /Measurement
Set-up
Measurement
ResultsConclusion
Goals of the
Characterisation
•
Board implementation
with
SpW-10X•
Basic functional
test over
full
operating
condition range•
Test of PLL over
full
operating
condition
range•
Characterisation
of electrical
parameters
•
Long time test of SpW LVDS links•
LVDS modes
testing
Parameters Measured
•
Power Consumption•
SpW Link Speed
•
Clock
Input Pulse Width
and Jitter•
PLL Function
•
PLL Cold Start•
SpW D/S Skew
and Eye Diagrams
•
LVDS modes
and long
term
function
Parameters Analysed
•
SpW Input D/S Separation•
Reset
Signal Pulse Width
and Recovery
Time
•
External
Port Timing•
Timecode
Interface Timing
•
Error / Status Interface Timing
Results
of Analysis (1)•
SpW Rx
front-end
D –
S edge
separation:
min. 2.06ns -> 3ns for
users
manual•
Reset
pulse width:
min. 0.71ns -> 5ns for
users
manual•
Reset
release
till
operation:
min. 18.67ns -> 20ns for
users
manual•
External
port
timing
for
users
manual:
input
setup
time: min. 5ns; hold time: min. 5ns
output
delay
from
clock: min. 5ns, max. 18ns
Results
of Analysis (2)•
Time Code port
timing
for
users
manual:
input
setup
time: min. 5ns; hold time: min. 5ns
EXTTIMEOUT delay
relatively
to EXTTICKOUT: ±5ns
EXTTICKIN, TIMECTRRST min. high/low
time: 1 CLK period
+ 5ns
EXTTICKOUT low
time: 3 CLK periods
±
5ns; min. high time: 4 CLK periods
±
5ns•
Error / Status interface
timing
for
users
manual:
output
delay
from
clock: min. 5ns, max. 25ns
output
delay
from
STATMUXADDR: min. 3ns, max. 20ns
STATMUXOUT input
stable
for
reset: inputs
need
to be
stable
from
end of reset
till
4 CLK periods
after
end of reset
Characterisation
Board
UUT2SpW_10X
SpW1
SpW2
SpW3
SpW4
SpW5
SpW6
SpW7
SpW8
EX0 EX1
TiCode StMux
UUT1SpW_10X
SpW1
SpW2
SpW3
SpW4
SpW5
SpW6
SpW7
SpW8
EX0 EX1
TiCode StMux
UUT3SpW_10X(socket)
SpW1
SpW2
SpW3
SpW4
SpW5
SpW6
SpW7
SpW8
EX0 EX1
TiCode StMux
Supply
Supply
Supply
SupplyPower
Measurement / Connection
Support FPGA
Meas point
Meas point
Meas point
Meas point
Meas point
Meas point
Meas point
Meas point
Meas point
PLL
Setting
PLL
Setting
PLL
Setting
30 MHz Clock
IF
to all SpW_10X ASICs and FPGA
Jumper
Jum
per
DIP SwDIP Sw
DIP Sw
DIP Sw DIP Sw
Meas point
Meas point
Meas point
Meas point
Meas point
Jumper
Reset to all SpW_10X ASICs and FPGA
SpWConn
SpWConn
SpWConn
SpWConn
SpWConn
SpWConn
SpWConn
SpWConn
SpWConn
SpWConn
SpWConn
SpWConn
SpWConn
SpWConn
Measurement
Set-up
SpW_10XChar Board
UUT2SpW_10X
SpW1
SpW2
SpW3
SpW4
SpW5
SpW6
SpW7
SpW8
EX0 EX1
TiCode StMux
UUT1SpW_10X
SpW1
SpW2
SpW3
SpW4
SpW5
SpW6
SpW7
SpW8
EX0 EX1
UUT3SpW_10X
(unpowered)
SpW1
SpW2
SpW3
SpW4
SpW5
SpW6
SpW7
SpW8
EX0 EX1
TiCode StMux
Supply
Supply
Supply
Support FPGA
(not mounted)
PLL
PLL
PLL/CLK
Power Supply
SpW USB Brick
Desktop
USB
StMuxTiCode
High Speed Oscilloscope
SpW Validation SW
SpW
SpW
TemperatureMeasurment
SpW1
SpW2
Test setting / PLL meas.
Sine Wave Generator (30MHz)
Clock IFadder
Noise
DMMs Voltage/Current
Power Measurements
•
All measurements
are
done
at -55°C (ambient), 25°C and 125°C•
All measurements
are
done
at 3.0V and 3.6V supply
voltage•
Dependency
on # of active
SpW links•
Dependency
on packet transfer•
Dependency
on bit
rate of SpW links•
Static
power without
clock
active•
Reset
active
and clock
active•
SpW LVDS driver
deactivation•
Dependency
on SpW Tx clock
divison
(TXDIV)
P vs. bit
rate and # of active
SpW3V6, port offset, active flow, +25°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
SpW
_10X
is id
le(n
o po
rt is
act
ive)
1 S
pW p
ort i
sac
tive
2 S
pW p
orts
are
activ
e
3 S
pW p
orts
are
activ
e
4 S
pW p
orts
are
activ
e
5 S
pW p
orts
are
activ
e
6 S
pW p
orts
are
activ
e
7 S
pW p
orts
are
activ
e
8 S
pW p
orts
are
activ
e
bitrate [Mbps]
tota
l pow
er c
onsu
mpt
ion
[W]
200Mbps100Mbps10Mbps2Mbps
P vs. # of active
SpW, packet flow
and T3V6, all ports active
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
2 10 100 200bitrate [Mbps]
tota
l pow
er c
onsu
mpt
ion
[W]
+25°C, no flow+125°C, no flow-55°C, no flow+25°C, active flow+125°C, active flow-55°C, active flow
Power Results
•
All measurements
are
done
at -55°C (ambient), 25°C and 125°C•
Static
power without
clock
active: max. 0.82W•
Reset
active
and clock
active: max. 1.32W•
SpW LVDS driver
deactivation: max. 0.06W / SpW link reduction•
Dependency
on SpW Tx clock
divison
(TXDIV): max. 0.3W reduction
for
1 to ½
division
@ 200MHz PLL
max. 0.2W reduction
for
½
to ¼
division
@ 200MHz PLL•
Dependency
on supply
voltage: measured
P at 3.0V was always
below
69.4% (resistive
model) of measured
P at 3.6V
Power Model has been
made
and included
in SpW-10X Users Manual
Link Speed
Measurements
•
All measurements
are
done
at -55°C (ambient), 25°C and 125°C•
All measurements
are
done
at 3.6V supply
voltage•
All measurements
are
done
for
200Mbps, 100Mbps, 10Mbps and 2Mbps
•
Period
of SpW bits
are
measured
and checked
for
length•
One Packet is
looping
and it
is
checked
that
another
packet at another
SpW link does
not
influence
the
looping
packet
Link Speed
Results
•
Periods
at all data
rates
are
OK•
Packets
are
not
influenced
by
packets
at other
SpW links Example
(200Mbps, 25°C): SpW1(Rx) to SpW2(Tx) looping
packet, start of a packet transmitted
from
SpW1
Clock
Input Measurements
•
All measurements
are
done
at -55°C (ambient), 25°C and 125°C•
All measurements
are
done
at 3.0V and 3.6V supply
voltage•
Noise
is
added
to sinusodial
clock
signal, which
converts
to jitter
at the
comparator
on the
board•
DC offset
is
added
to sinusodial
clock
signal, which
converts
to pulse width
changes
at the
comparator
on the
board•
30MHz clock
from
signal
generator
was used
as trigger
(reference)
Clock
Input Pulse Width
Results
•
PLL is
the
limitting
device
for
clock
pulse width
•
Oscilloscope
Waveforms:
SYN1 sync
signal
Clk30 (UUT1)
PLL_FB (UUT1)
PLL_LCK (UUT1)•
Measurements
show
limit
at pulse width
of 3.5ns
•
5ns for
users
manual
Clock
Input Jitter
Results
•
PLL is
very
robust to clock
jitter•
Functional interruption
due
to to
short
clock
periods
before
PLL fails
to lock•
Oscilloscope
Waveforms:
SYN1 sync
signal
Clk30 (UUT1)
SpW1 Din+ (UUT1)
SpW2 Dout+ (UUT1)•
Measurements
show
limit
at jitter
of 3.8ns•
2ns for
users
manual
Clock
Input Jitter
Results
•
PLL is
very
robust to clock
jitter•
Single missing
clock
pulses
are
only
causing
short
distortions
in PLL•
Oscilloscope
Waveforms:
SYN1 sync
signal
Clk30 (UUT1)
PLL_FB (UUT1)
PLL_LCK (UUT1)
PLL Locking
Time Results
•
Measured
at all PLL frequencies
•
Measured
from
PLL Reset
till
PLL lock•
Oscilloscope
Waveforms:
PLL_LCK (UUT1)
PLL:RST (UUT1)•
Max. lock time measured
10.4µs (20 measurements
for
each
setting)•
Users manual
value
max. 20µs
SpW Tx D / S Skew
and Eye Diagrams
•
All measurements
are
done
at -55°C (ambient), 25°C and 125°C•
All measurements
are
done
at 3.0V and 3.6V supply
voltage•
All measurements
are
done
for
200Mbps, 100Mbps, 10Mbps and 2Mbps
•
D / S at SpW-10X outputs
are
connected
to oscilloscope
with
coaxial
cables
(21:1 probe bouilt
onto
the
board) and differential signal
computed
with
oscilloscope•
30MHz clock
from
signal
generator
was used
as trigger
(reference)•
2 different data
patterns
(packets) were
sent
for
each
measurement
to cover
all D / S edge
combinations•
Persistant
mode of oscilloscope
with
a duration
of >10s for
each
pattern
SpW Tx D / S Skew
Results
•
SpW standards
has an example
for
200Mbps: budget
assumes
SpW Tx skew
and jitter
max. 1.22ns
•
Measurements
show
total skew
and jitter
of SpW Tx: max. 1.19ns
•
1.2ns for
users
manual
SpW Tx D / S Eye Diagrams
•
Big variation
in the
eye
diagrams
depending
on the
structure
of the
SpW LVDS connection
(straight
PCB connection, Via SpW connector
and SpW cable, with
jumpers
and ‚dead
ends‘)•
Example:
SpW2, 3.6V, 25°C, 200Mbps
SpW Tx D / S Eye Diagrams
•
Worst
case: SpW1, 3.6V, -55°C, 200Mbps There
is
negative margin
(signal
crossing
0V line) at one
measurement•
No error
occured
at SpW link during
this
measurement•
Additional long
term
measurement
added
to check function
SpW LVDS Long Term Measurements
•
All measurements
are
done
at -55°C (ambient) / 3.6V and 125°C / 3.0V
•
All measurements
lasts
for
at least 24 hours•
Two
scenarios
are
measured:1. Full operation of SpW-10X with packets flowing through all SpW links at 200Mbps2. SpW-10X SpW link with failsave resistors connected to a SpW-10X SpW LVDS output at deactivated mode
•
Success
criteria:1. No error occurs at any SpW LVDS link of UUT12. No wrong NULL is detected at the SpW receiver of the link connected to deactivated SpW LVDS drivers
•
Results:1. No error has occured at any measurement2. No wring NULL has been detected
SpW LVDS Modes
•
All measurements
are
done
at 25°C (ambient) / 3.3V•
Test the
Function
of all LVDS driver
modes:Active driverDeactivated driverUnpowered driver (cold sparing)
•
Each
mode was measured
at a LVDS link with
and an LVDS link without
failsave
resistors•
Results:All operarational modes are as expected (current/voltage measurements)Both with and without failsave resistorsDeactivated mode has a special behaviour, where both LVDS outputs areconnected to positive supply via resistors (~2850 Ω)
Conclusion
•
All Parameters wanted
from
Analysis / Measurement
could
be
obtained
•
No Problem / malfunction
has been
found during
the
activity
•
Board design
with
the
SpW-10X ASIC has no particular
difficulties
•
Information has been
included
into
the SpW-10X documentation