Spring 2006

Lillevik 437s06-l24 1University of Portland School of Engineering

EE 437

Advanced ComputerArchitecture

Lecture 24

Eight-node distributed computerRing router design

Spring 2006

Lillevik 437s06-l24 2University of Portland School of Engineering

EE 437

Distributed computer

No global or shared memory

Interconnect

P

M...

P

M

P

M

Spring 2006

Lillevik 437s06-l24 3University of Portland School of Engineering

EE 437

System schematic

Node

Spring 2006

Lillevik 437s06-l24 4University of Portland School of Engineering

EE 437

Ring router block diagramIn Out

D

In I/F

Out I/F

CPU I/F

Latch

Controller

Latch Driver

Driver

Driver

Spring 2006

Lillevik 437s06-l24 5University of Portland School of Engineering

EE 437

Ring router schematic (ROUTER.CKT)input buffer

write buffer

Spring 2006

Lillevik 437s06-l24 6University of Portland School of Engineering

EE 437

Router controller schematic

4 Inputs9 Outputs

FSM contains 4 inputs and 9 outputs

Spring 2006

Lillevik 437s06-l24 7University of Portland School of Engineering

EE 437

Simplified state diagram

0

Write mode

Read mode

Pass mode

Reset

Reset

WReq RReq

IReq

Hint: each mode requires 4 states

Spring 2006

Lillevik 437s06-l24 8University of Portland School of Engineering

EE 437

RTRFSM state diagram

0000

d l

e

g

kc

hf

i jab

Reset

WReq

RReq

IReq

WReq RReq

IReq

OAck

OAck

IReq IReq

OAckOAck

WBClk

WBEOReq

WAck

IBClk IBERBERAck

OReqIBClk

IBEOReq

IAck

Reset

IAck

WBEOReq

WReq

WReq

IBERBE

RReq

RReqIReq

IReq

IBE

Spring 2006

Lillevik 437s06-l24 9University of Portland School of Engineering

EE 437

PS RBE WBE WBClk IBE IBClk WAck RAck OReq IAck

a

b

c

d

e

f

g

h

i

j

k

l

Find the output table?

Spring 2006

Lillevik 437s06-l24 10University of Portland School of Engineering

EE 437

FSM timing: write

Spring 2006

Lillevik 437s06-l24 11University of Portland School of Engineering

EE 437

FSM timing: read

Spring 2006

Lillevik 437s06-l24 12University of Portland School of Engineering

EE 437

FSM timing: pass

Spring 2006

Lillevik 437s06-l24 13University of Portland School of Engineering

EE 437

Eight-node example

0

4

6

1

3

7

5

2

Write

WriteWrite

Pass

PassRead

Read

Read

Spring 2006

Lillevik 437s06-l24 14University of Portland School of Engineering

EE 437

System timing

Spring 2006

Lillevik 437s06-l24 15University of Portland School of Engineering

EE 437

Message format

• Header: routing and control information

• Payload: data

• Trailer: error checking code (ECC)

HeaderPayloadTrailer

time

Spring 2006

Lillevik 437s06-l24 16University of Portland School of Engineering

EE 437

Unidirectional ring router

Ring

Router

IReqIAck

In

OReqOAck

Out

RR

eq

WR

eq

RA

ck

WA

ck

D

Link input Link output

Processor

Spring 2006

Lillevik 437s06-l24 17University of Portland School of Engineering

EE 437

Changes for DMA interface?

Spring 2006

Lillevik 437s06-l24 18University of Portland School of Engineering

EE 437

Changes for header?

Spring 2006

Lillevik 437s06-l24 19University of Portland School of Engineering

EE 437

Changes for fixed length message?

Spring 2006

Lillevik 437s06-l24 20University of Portland School of Engineering

EE 437

Changes for trailer?

Spring 2006

Lillevik 437s06-l24 21University of Portland School of Engineering

EE 437

Changes for interference?

Spring 2006

Lillevik 437s06-l24 22University of Portland School of Engineering

EE 437

Spring 2006

Lillevik 437s06-l24 23University of Portland School of Engineering

EE 437

PS RBE WBE WBClk IBE IBClk WAck RAck OReq IAck

a 1 1 1

b 1 0 1 1 1

c 1 0 1 1

d 1 1 1 1

e 1 1 1

f 1 1 1

g 0 1 0 1

h 0 1 0 1 1

i 1 1 1

j 1 1 0 1 1

k 1 1 0 1

l 1 1 1 1

Find the output table?

Spring 2006

Lillevik 437s06-l24 24University of Portland School of Engineering

EE 437

Changes for DMA interface?

• CPU writes a word count

• CPU writes a memory address

• CPU writes a start command

• CPU does other useful work

• DMA responds with interrupt

• CPU acknowledges interrupt

• CPU processes message

Spring 2006

Lillevik 437s06-l24 25University of Portland School of Engineering

EE 437

Changes for header?

• Router looks at first byte

• If destination address is to CPU, then routes data to processor port (buffer)

• If address is not to CPU, then passes data to correct link based on destination address

Spring 2006

Lillevik 437s06-l24 26University of Portland School of Engineering

EE 437

Changes for fixed length message?

• Header byte resets counter

• Each new byte processed decrements counter

• When counter zero, message complete

Spring 2006

Lillevik 437s06-l24 27University of Portland School of Engineering

EE 437

Changes for trailer?

• Each new data byte added to checksum calculation

• Calculated checksum compared to message checksum, error results in CPU interrupt

Spring 2006

Lillevik 437s06-l24 28University of Portland School of Engineering

EE 437

Changes for interference?

• Design must support all possible concurrency modes

• Router checks for interference

• Possible responses– Block a message (deadlock possible), requires

arbitration algorithm– Time multiplex (n-way) the link