SPF BAND 345 CONTROL FUNCTION DESIGN DOCUMENT ...ska-sdp.org/sites/default/files/attachments/317-030000...Figure 16: (Left) Internal block diagram of the AD7616 ADC chip (from Analog

SPF BAND 345 CONTROL FUNCTION

DESIGN DOCUMENT

Document Number ..............................................................................317-030000-007 Revision ...................................................................................................................... A AuthorM. Jones, J. Leech, A. Aminaei, J. Saunders, A. Hector, A. Taylor, A. Born, R. Watkins ..................................................................................................................................... Date ............................................................................................................ 2019-02-28 Status .................................................................................................................... Draft

Name Designation Affiliation Signature and Date

Compiled by:

J. Leech SPF Band 345 Lead Engineer

University of Oxford

Approved by:

A.C. Taylor SPF Band 345 Project Manager

University of Oxford

I.P. Theron SPF Lead Engineer

EMSS Antennas

Document No.: Revision: Date:

317-030000-007 A 2019-02-28

Author: M. Jones et. al.

Page 2 of 41

DOCUMENT HISTORY Revision Date Of Issue Engineering Change

Number Comments

A 2019-02-28 - First draft for DDR

DOCUMENT SOFTWARE Package Version Filename

Word processor MsWord Word 2016 317-030000-007_RevA_SPFB345_ControlFunctionDesign.docx

Block diagrams

Other

ORGANISATION DETAILS Name SKA Organisation

Registered Address Jodrell Bank Observatory Lower Withington Macclesfield Cheshire SK11 9DL United Kingdom Registered in England & Wales Company Number: 07881918

Fax. +44 (0)161 306 9600 Website www.skatelescope.org


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TABLE OF CONTENTS 1 INTRODUCTION ......................................................................................... 8

1.1 Purpose of Document ......................................................................................................... 8

1.2 Scope of Document ............................................................................................................ 8

2 DOCUMENTS ............................................................................................ 8

2.1 Applicable Documents ........................................................................................................ 8

2.2 Reference Documents ........................................................................................................ 8

3 DESIGN DESCRIPTION .................................................................................. 8

3.1 System Overview ................................................................................................................ 8 3.2 Context .............................................................................................................................. 9

3.3 Functional Architecture .................................................................................................... 10

3.4 Product Breakdown Structure .......................................................................................... 11

3.5 System Architecture Overview ......................................................................................... 12

3.5.1 Preventing Digital Interference ................................................................................. 12

3.5.2 Common Subsystems for Different SKA Feeds ........................................................... 13

4 MAJOR COMPONENT DESIGN ....................................................................... 13

4.1 Overview .......................................................................................................................... 13

4.2 Power supplies ................................................................................................................. 14

4.2.1 Mains conditioning ................................................................................................... 14

4.2.2 Lightning surge protection (LSP) ............................................................................... 15

4.2.3 Relay Control ............................................................................................................ 16

4.2.4 DC Power Supplies .................................................................................................... 17

4.2.5 Grounding Architecture ............................................................................................ 20

4.3 Digital control system ....................................................................................................... 20

4.3.1 FPGA Controller board .............................................................................................. 20

4.3.2 ADC / DAC digital motherboard ................................................................................ 21

4.4 Analogue motherboard .................................................................................................... 23

4.4.1 Pressure Monitoring ................................................................................................. 24

4.4.2 LNA Bias daughter boards ......................................................................................... 25

4.4.3 Temperature monitoring circuit ................................................................................ 26

4.4.4 Noise diode driver .................................................................................................... 28

4.4.5 LNA heater driver ..................................................................................................... 28

4.4.6 Warm RF plate control .............................................................................................. 29


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4.5 Coldhead stepper motor controller .................................................................................. 29

4.6 FPGA firmware ................................................................................................................. 31

4.6.1 Overview .................................................................................................................. 31

4.6.2 Safety state machine ................................................................................................ 31

4.6.3 Serial communications .............................................................................................. 34

4.6.4 SPI interface controller ............................................................................................. 35 4.6.5 Temperature monitoring .......................................................................................... 35

4.6.6 Pressure monitoring ................................................................................................. 35

4.6.7 Coldhead motor control............................................................................................ 35

4.6.8 LNA temperature control firmware ........................................................................... 35

4.6.9 LNA bias monitoring/control firmware ...................................................................... 35

4.6.10 Firmware updates ..................................................................................................... 36

4.6.11 Current state of development and remaining work. .................................................. 36

4.7 Enclosure and physical layout ........................................................................................... 36

4.8 Interfaces, harnesses and connectors ............................................................................... 37

4.8.1 Exposed Interfaces.................................................................................................... 37

4.8.2 Internal Interfaces .................................................................................................... 37

4.8.2.1 Filtered Connectors .............................................................................................. 37

4.8.2.2 Hermetic Connectors ............................................................................................ 38

4.8.2.3 Optical fibre .......................................................................................................... 39

5 SAFETY .................................................................................................. 39

6 CONCLUSIONS .......................................................................................... 41

LIST OF FIGURES Figure 1: Control function context within the Band 345 SPF. .............................................................. 9

Figure 2: Major functional decomposition of the FPC. ...................................................................... 10

Figure 3: SKA band 345 PBS (overview). ........................................................................................... 11

Figure 4: The FPC345 block diagram. ............................................................................................... 12

Figure 5: The Amphenol connector for the mains input, the chassis-mounted mains EMI filter and its circuit diagram. ...................................................................................................................... 14

Figure 6: Dehnguard Lightning Surge Protection Unit and its circuit diagram ................................... 16

Figure 7: Solid-state relay and its wiring diagram. ............................................................................ 17

Figure 8: Vacuum valve relay control circuit. ................................................................................... 17

Figure 9: The custom-made transformer for the PSU with 8 voltage outputs.................................... 19


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Figure 10: The architecture of the DC-PSU for FPC345. .................................................................... 19

Figure 11: The FPGA controller board, showing the top side with the FPGA and other devices, and the underside with the stacking multi-way connectors. The overall board size is 40 x 50 mm. ...... 20

Figure 12: Block diagram of TE0720-03 FPGA board (from Trenz Electronics) ................................... 21

Figure 13: Digital control board........................................................................................................ 22

Figure 14: Digital control board mounting arrangement. ................................................................. 22 Figure 15: (Left) Internal block diagram of the AD5380 DAC chip (from Analog Devices) (Right) AD5380

evaluation board.................................................................................................................... 23

Figure 16: (Left) Internal block diagram of the AD7616 ADC chip (from Analog Devices) (Right) AD7616 evaluation board.................................................................................................................... 23

Figure 17: Block diagram of the FPC345 analogue motherboard. ..................................................... 24

Figure 18: Active Pirani vacuum gauge and its voltage-pressure response curve. ............................. 25

Figure 19: Prototype LNA bias card. ................................................................................................. 26

Figure 20: Cryogenic temperature sensor monitoring circuit. ........................................................... 26

Figure 21: LNA Bias Circuit ............................................................................................................... 27

Figure 22: Prototype temperature monitoring circuit hardware. ...................................................... 28

Figure 23: Constant-current drive circuit for the noise diode. .......................................................... 28

Figure 24: Control and monitoring of the temperature of cryogenic LNAs using heater driver and temperature sensors.............................................................................................................. 29

Figure 25: Stepper motor controller prototype board. ..................................................................... 30

Figure 26: Stepper motor controller schematic. ............................................................................... 30

Figure 27: States and modes of the FPC. .......................................................................................... 31

Figure 28: Structure of firmware modules within the FPGA. ............................................................. 32

Figure 29: Band 345 enclosure mechanical model (Left, exploded view; Right, attached to the rear of the B345 cryostat body). The internal partitions of the enclosure are not shown; these will be detailed once all the PCB sizes are finalised. .......................................................................... 37

Figure 30: Typical Amphenol D38999 connectors (left) and ODC-4 fibre connector (right). .............. 37

Figure 31: Series 700 D-Sub filtered connector (50 Pins/Sockets) and its filter characteristics (see trace E in the upper plot and trace D in the lower plot.) .................................................................. 38

Figure 32: FFTP Samtec twisted pair cable assembly (socket) for connection between D-Sub connectors. ............................................................................................................................ 38

Figure 33: The FPC345 cryostat flange with hermetic connectors. .................................................... 39

Figure 34: SC fibre interface. ........................................................................................................... 39


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LIST OF TABLES Table 1: Specifications of the Schaffner AC EMI Filter proposed for the FPC AC unit. ........................ 15

Table 2: Specifications of the proposed lightning surge protection for the FPC345 ........................... 16

Table 3: Nominal voltages and maximum currents for FPC components........................................... 18

Table 4: Bits of the FPGA state register ............................................................................................ 32


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LIST OF ABBREVIATIONS

AC .................... Alternating Current ADC .................. Analogue to Digital Converter AI ..................... Analogue Interface BGA.................. Ball Grid Array BTL ................... Bridge-Tied Load DAC .................. Digital to Analogue Converter DC .................... Direct Current DDR ................. Detail Design Review EEPROM ........... Electrically Erasable Programmable Read-only Memory FFTP ................. Fifty by Fifty Twisted Pair FPC .................. Feed Package Controller EMI .................. Electromagnetic Interference ESD .................. Electrostatic Discharge ETC .................. Elapsed Time Counter FPC .................. Feed Package Controller FPGA ................ Field Programmable Gate Array IIR .................... Infinite Impulse Response LE ..................... Logic Elements LED .................. Light Emitting Diode LNA .................. Low Noise Amplifier MISO ................ Master In Slave Out MOSI ................ Master Out Slave In NRC .................. National Research Council NTC .................. Negative Temperature Coefficient OMT................. Ortho-mode Transducer Op-amp ............ Operational Amplifier PCB .................. Printed Circuit Board PID ................... Proportional-Integral-Derivative PN .................... Part Number POR .................. Power On Reset PSRR ................ Power Supply Rejection Ratio PSU .................. Power Supply Unit QFN ................. Quad Flat No-leads RCMU .............. Receiver Control and Monitoring Unit RF .................... Radio Frequency RFI ................... Radio Frequency Interference Si-Do ................ Silicon Diode SKA .................. Square Kilometre Array SPD .................. Surge Protection Device SPF ................... Single Pixel Feed SPFC ................. Single Pixel Feed Controller SPI.................... Serial Protocol Interface SRAM ............... Static Random Access Memory SSR ................... Solid State Relay UART ................ Universal Asynchronous Receiver-Transmitter VHDL ................ Virtual Hardware Description Language


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1 INTRODUCTION

1.1 Purpose of Document

The purpose of this document is to record the detailed design of the control function of the single pixel feed (SPF) Band 345 which forms part of the SPF sub-element of the dish element for the SKA1 MID telescope. Most of the control function is represented by the feed package controller (FPC) of the cryostat and control assembly of the SPF Band 345.

1.2 Scope of Document

This document is the design justification for the SKA Band 345 FPC, specified in [AD1]. It summarises selected design notes, calculations, concept and prototype designs, as well as calculated and measured results for various components. The information provided aims to capture the current state of development.

2 DOCUMENTS

2.1 Applicable Documents

The following documents are applicable to the extent stated herein. In the event of conflict between the contents of the applicable documents and this document, the applicable documents shall take precedence.

[AD1] A. Born, “SPF Band 345 Development Specification” SKA-TEL-DSH-0000085 Rev 1, 2018-09-25

[AD2] P.C. van Niekirk, “SPF Controller to SPF Band 345 Data Exchange ICD”, SKA-TEL-DSH-0000095, Rev. 1, 2018-09-05.

2.2 Reference Documents

The following documents are referenced in this document. In the event of conflict between the contents of the referenced documents and this document, this document shall take precedence.

[RD1] J. Leech et al, “SPF Band 345 Signal Path Design Document”, 317-030000-008, Rev. A, 2019-02-28.

[RD2] J. Leech et al, et al., “SPF Band 345 Cryogenic Function Design Document”, 317-030000-006, Rev. A, 2019-02-28.

3 DESIGN DESCRIPTION

3.1 System Overview

The control function of the SPF band 345 is implemented in the FPC345 module. This is an FPGA-based data acquisition and control system that implements the low-level functions required for executing the commands received from the single pixel feed controller (SPFC). It monitors temperature and pressure sensors, and voltage and current bias signals, and controls all the critical feed components. It houses the power supply unit (PSU) that converts the AC mains supply to the DC voltages required


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by the various feed components. It also provides the drive circuit for the coldhead stepper motor, and provides control of the local Band 345 vacuum system, comprising the cryostat vacuum vessel gate valve, turbo pump and NEG pump. The FPC345 has a fibre optic interface that provides communication with the SPFC via a proprietary UART protocol [AD2], and a direct fibre drive from the SFPC to control the calibration noise source.

3.2 Context

The key elements of the Feed Package Control function are shown in Figure 1.

Figure 1: Control function context within the Band 345 SPF.


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3.3 Functional Architecture

A breakdown of the major functions of the FPC is shown in Figure 2. These major functions are performed jointly between the FPC hardware and FPGA firmware.

Figure 2: Major functional decomposition of the FPC.


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3.4 Product Breakdown Structure

Figure 3 shows a breakdown of the cryostat & control hardware. The FPC constitutes the control part of the hardware.

Figure 3: SKA band 345 PBS (overview).


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3.5 System Architecture Overview

Figure 4 shows a high-level block diagram of the FPC345. The FPC system is divided into the main units as follows:

● AC Mains input power and conditioning, including the surge protection ● Peripheral control, including vacuum valve and cooler motor ● DC Power supply unit ● Digital control unit, comprising the FPGA and its interfaces ● Analogue unit, including the interface boards, RF amplifier biasing and connectors

These subsystems are divided into separate compartments to prevent interference between digital and high-current analogue systems, and low-power and RF-sensitive systems.

Figure 4: The FPC345 block diagram.

3.5.1 Preventing Digital Interference

Due to the extremely tight RFI specifications imposed on the SKA feed systems (refer to [AD1]), the utmost care needs to be taken to ensure that the FPC does not radiate RFI that can affect the other components functionality, or contaminate its own output with digital interference. To this end, a number of precautions and design decisions were taken, and are listed below. Each of these will be discussed in more detail in the paragraphs that follow.


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• The sensitive analogue circuitry that interfaces with the amplifiers and other components within the cryostat has been totally separated from the digital unit.

• Several levels of low-pass filtering have been implemented between the digital unit and other units which have an interface with the digital unit.

• The digital unit is enclosed within multiple layers of RFI shielding.

• A linear power supply with low noise characteristics is used.

• The cryocooler motor is not driven with a switching motor driver. The drive waveforms for the motor are synthesised in the FPGA and heavily filtered to remove edges, before being amplified with a linear amplifier capable of providing the necessary drive currents.

3.5.2 Common Subsystems for Different SKA Feeds

The design for the Band 345 FPC is heavily influenced by the other FPC designs, particularly Band 2, which has many similar functions in the control and monitoring of a cryogenic system. However, due to the many detailed differences between Band 2 and Band 345, particularly in the number of channels that need to be controlled and monitored, few actual hardware components are re-used. For example, the Band 2 FPGA board does not have enough I/O lines to cope with all the monitoring and control needed by the five RF systems in the feed package. However, the many design similarities allow us to re-use many design concepts from Band 2, some in detail. These include the use of a multi-tap custom transformer for providing the multiple voltages required, the cryogenic temperature monitoring circuit, the use of an FPGA to provide the programmable functionality, the physical layout incorporating separate compartments within a machined box, and the filtered connectors and EMI gaskets used.

4 MAJOR COMPONENT DESIGN

4.1 Overview

The system block diagram of the FPC345 is illustrated in Figure 4. The AC unit provides the mains power, which is converted to the DC voltages needed to power the rest of the sub-modules. It also provides the AC power required by the relay for the solenoid vacuum valve. The AC Voltage (230 V, 50-60 Hz) is converted to DC voltage using a linear AC-DC power supply. The digital unit employs an FPGA board which monitors and controls system functions using ADCs and DACs on a digital motherboard. The analogue interface unit includes a main motherboard providing the temperature monitoring circuits, connectors and routing for analogue signals, and sockets for LNA-biasing daughter boards. Mounting the LNA biasing units as daughter boards allows for the use of specific biasing circuits for the Band 3, 4 and 6 LNAs when these are finalised. The daughterboards have interfaces with the ADC and DAC I/Os in the digital unit and the RF components in the cryostat. The drive circuits for the LNA heaters are also placed in the analogue unit. A current-stabilized power supply for the noise diodes in the cryostat is provided. The noise source is directly controlled via a fibre optic connection from the SPFC, which is used to operate an RF switch that connects the noise source to the noise-coupler port in the RF path. The FPC also provides control and switching for the NEG pump. The digital components are kept in a separate compartment to the analogue components and filtered D-connectors are used to minimise the transfer of digital noise on signal and power supply lines. The components of each unit and their functionality are presented in the following sections.


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4.2 Power supplies

A number of different DC supplies with various voltage levels are needed within the FPC. For these DC power supplies, both switch-mode and linear AC-DC power supply units (PSU) were considered and evaluated. Commercial switch-mode PSUs are compact, efficient (~80%) and can easily supply multiple voltage outputs. However, switch-mode noise levels can be as high as a few hundred millivolts, which would be unsuitable for powering analogue components such as LNAs and amplifiers. Linear PSUs, on the other hand, are less efficient (~40%) and occupy more space given the large physical sizes of the mains transformers and electrolytic smoothing capacitors. However, they are immune from the problem of switch-mode noise. Large toroidal mains transformers with custom windings are commercially available at reasonable cost in the volumes required for Band 345 production. Therefore, a linear PSU with a custom-made transformer similar to that used for the Band 2 PSU was decided upon for the baseline design. The DC PSU generates all the required DC voltages for the analogue and digital units, with separate windings used for the supplies to the analogue and digital circuit boards. This, together with the use of filtered interconnects, will avoid problems arising from noise induced on the analogue supply lines from the digital electronics. The linear DC power supply units are described in detail in Section 4.2.4.

4.2.1 Mains conditioning

The 230 V AC mains is supplied via a MIL spec. Amphenol circular connector (type D38999-20WC4PN). The current rating is 13 A and the shell material is aluminium. The connector is selected based on the ‘Physical ICD between the SPF B345 and the DC’ specified in the document SKA-TEL-DSH-0000060. The Amphenol connector is shown in Figure 5. Inside the FPC enclosure, a standard fuse will be used to protect the circuitry from short-circuit and over-rated currents. A Schaffner AC EMI filter prevents RFI leakage from inside the FPC to the outside world via the mains connection. The AC EMI filter, its schematics and its specs are shown in Figure 5 and Table 1.

Figure 5: The Amphenol connector for the mains input, the chassis-mounted mains EMI filter and

its circuit diagram.


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Parameter Value

Brand, Series Schaffner, FN2030M-6-06

Max. Current rating 30 A

Nominal Voltage rating 250 VAC, 250 VDC

Dimension, LWH 71x 46.6x22.3 mm

Weight 120 g

Capacitance Cx = 0.47 MicroF, Cy = 4.7 nF

Inductance 8 mH

Operating Temperature -25 to +100 deg. C

Resistance 680 kOhm

Operating Frequency DC to 400 Hz

Table 1: Specifications of the Schaffner AC EMI Filter proposed for the FPC AC unit.

4.2.2 Lightning surge protection (LSP)

Similarly to Band 2, a Dehnguard LSP part No. DG S 275 (see Figure 6) is proposed for the B345 FPC. It is a multi-purpose surge arrester consisting of a base element and a plug-in protection module. It has high discharge capacity because of the heavy-duty zinc oxide varistor, and high reliability due to thermo-dynamic control SPD monitoring device. Its specifications are shown in Table 2 below.

Parameter Value

SPD according to EN 61643-11/IEC 61643-11 Type 2/ Class II

Nominal AC Voltage 230 V (50-60 Hz)

Max. continuous operating voltage 275 V

Nominal discharge current 20 kA

Max. discharge current 40 kA

Voltage protection level =<1.5 kV


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Response time =<25 ns

Operating temperature -40 to +80 degree C

Weight 130 gr

Mounting on 35 mm DIN rails access to EN

Enclosure material Thermoplastic, red, UL 94

Installation Indoor

Degree of protection IP20

Table 2: Specifications of the proposed lightning surge protection for the FPC345

4.2.3 Relay Control

To switch the solenoid valve a mains voltage is required. The vacuum valve uses a relay for its on/off control. To reduce any RFI contributions from a mechanical contact, a solid-state relay (SSR) has been selected. This is the ASO series PCB mount relay (ASO241) from Crydom (see Figure 7). This relay is rated at 1.5 A and features either zero-crossing or random-fire outputs. The control lines are routed from the controller board via the power supply board and two filtered connectors (one entering and the other exiting the power supply cavity), to the SSRs in the mains input cavity. The control voltage is rated as 4 VDC to 8 VDC with a nominal input impedance of 300 Ω. The relay’s input is optically isolated from the output. The operating output voltage (load voltage) is in the range 12-280 Vac with a frequency range of 47-63Hz. In addition to the vacuum valve, the turbo pump and Non-Evaporable-Getter (NEG) pump power DC supplies also need to be switched by a solid-state relay. A Sensata / Crydom DC60S7 will be used which is capable of switching up to 60 V, 7A DC.

The relay control circuit (Figure 8), which is identical to that used for Band 2, uses a load switch (PN FDC6330L) from Fairchild. This device is rated for an input voltage between 3 V and 20 V and can switch up to 2.3 A. This device implements a P-channel MOSFET as the pass element and an N-channel

Figure 6: Dehnguard Lightning Surge Protection Unit and its circuit diagram


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MOSFET to control the former. RT1 is a 0ZCM-series resettable fuse from Belfuse, which protects the circuit in case the control lines get shorted in the mains input cavity. FB1 and FL4 form a low-pass filter between the digital and analogue circuits and D2 serves as ESD protection and is located as close as possible to the on-board connector.

Figure 7: Solid-state relay and its wiring diagram.

The vacuum-valve relay control circuit uses two opposite polarity control lines to control the load switch. The second line has to be low and the first line high to close the load switch. This dual polarity of the control lines ensures that the vacuum-valve relay does not get switched by accident during power up or power down of the FPC.

Figure 8: Vacuum valve relay control circuit.

4.2.4 DC Power Supplies

The DC voltage and current requirements of the main FPC 345 components including the digital and analogue modules are summarised in Table 3. Both the digital and analogue sub-systems are supplied by a linear PSU in which a custom-made transformer has been used.

The transformer is made by Tiger Toroids, Ltd, a UK-based company, and includes 8 separate secondary windings to generate 8 AC output voltages that are converted to regulated DC voltages. The weight of transformer is 8.05 kg and dimensions are outer radius 90 mm, height 70 mm.


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For the digital and analogue subsystems, separate windings are used to avoid the coupling of noise and EMI generated by the digital electronics to the sensitive analogue DC supplies. The AC outputs of the transformer are converted to DC voltages via bridge rectifiers and smoothing capacitors. We have selected the Vishay VS-26MB120A bridge rectifier module and EPCOS B41456 smoothing capacitors. Depending on the DC on the voltage levels, smoothing capacitors are selected in the range of 0.015 F to 0.068 F. The DC voltages are then regulated by voltage-regulator modules using LM338 and LT1083 voltage regulators and then supplied to the digital and analogue units via filtered connectors between the enclosure compartments. The architecture of the PSU is illustrated in Figure 10.

Type Nominal Voltage (V)

Maximum Current (A)

Application

Digital 5 5 FPGA module and DAC

Digital 3.6 0.5 DAC

Digital 7.5 1 ADC

Analogue -5 1 LNA bias and LNA temperature control

Analogue 5 1 LNA bias and LNA temperature control

Analogue 6.5 1 Warm RF chain temperature control boards

Analogue 7.5 3 2nd stage RF amplifiers

Analogue 28 0.2 Noise diode module(s)

Analogue - 30 3 Cold-head Motor control board

Analogue + 30 4 Cold-head motor control board Turbo Pump

Vacuum sensors

Analogue 12 V 4.5 NEG pump (regeneration).

Table 3: Nominal voltages and maximum currents for FPC components.


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Figure 9: The custom-made transformer for the PSU with 8 voltage outputs.

Figure 10: The architecture of the DC-PSU for FPC345.


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4.2.5 Grounding Architecture

It is necessary to ground each of the individual modules (analogue board, digital board etc) to the FPC enclosure in order to achieve good EMC screening. However this introduces the risk of noise coupling between the units by means of ground return currents through the enclosure. To avoid this, we ensure that the PSU board is not connected to the enclosure ground. This means that all supply and return currents travel separately to their respective modules via the power supply wiring only. The mains components are grounded to the enclosure for electrical safety.

4.3 Digital control system

The digital control system provides the control functionality of the FPC via an FPGA, and all the analogue and digital interfaces to the FPGA to allow this control to take place. It comprises a commercially-available miniature FPGA board plugged in to a custom motherboard providing additional ADC and DAC channels for control and monitoring functions. The digital control system is situated in its own shielded compartment of the FPC enclosure, separated from the PSU section and the analogue section. Multi-channel ADC chips and multi-channel DAC chip are used to provide the analogue inputs and outputs. These are connected to the FPGA via an SPI interface. The motherboard then provides connector sockets linking to the signals being controlled and monitored in the analogue compartment via filtered D-connectors.

Development of the digital control system has used evaluation boards for the ADC and DAC devices, connected to the FPGA board with cables (see Figure 15 and Figure 16). This has allowed development of the FPGA firmware to control these devices, and evaluation of their analogue performance. The production version of the control system will integrate both DAC and ADC devices on to the digital motherboard. While the layout of this board remains to be done, it is considered to be low risk, as it will be based on the available schematics and layouts of the evaluation boards.

4.3.1 FPGA Controller board

Figure 11: The FPGA controller board, showing the top side with the FPGA and other devices, and

the underside with the stacking multi-way connectors. The overall board size is 40 x 50 mm.

The FPGA board is a TE0720-03-1CFA from Trenz Electronics. This is a system-on-chip (SoC) module with industrial temperature range, integrating a Xilinx Zynq-7020 FPGA, a gigabit Ethernet transceiver, 1 GByte DDR3 SDRAM, 8 GByte e.MMC, 64 MByte Flash memory for configuration and operation, a


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USB2.0 transceiver and switch-mode power supplies for all on-board voltages. The Ethernet transceiver will not be used, as all communication with be via the serial interface. A large number (152) of configurable I/O's is provided via rugged high-speed stacking strips. It is designed for industrial applications with good resistance to shock, vibration and temperature extremes. The FPGA incorporates an ARM dual-core Cortex A9 processor core, allowing for straightforward programming and control.

Figure 12: Block diagram of TE0720-03 FPGA board (from Trenz Electronics)

4.3.2 ADC / DAC digital motherboard

The FPGA card plugs in to a motherboard which contains the ADC and DAC chips, and routes control and monitoring signals to the appropriate connectors to link to the other parts of the FPC system (see Figure 13). This board is mounted in its own machined compartment of the FPC enclosure, with filtered connectors to the other compartments containing the analogue motherboard, PSUs etc. The board will be mounted with the FPGA on the underside, creating an additional sealed cavity in which most of the digital electronics is contained (see Figure 14).

The AD5380 DAC provides the bias voltages for the LNA Bias circuit, the heater drive voltages for the LNA temperature stabilization, and the drive waveforms for the coldhead motor controller. These voltages are controlled from the SPI serial link, which connects the DAC to the FPGA. The AD5380 itself is a complete, single-supply, 40-channel, 14-bit DAC in a 100-lead LQFP package. All 40 channels have an on-chip output amplifier with rail-to-rail operation. The AD5380 includes a programmable internal 1.25 V/2.5 V, 10 ppm/°C reference, an on-chip channel monitor function that multiplexes the analogue outputs to a common MON_OUT pin for external monitoring, and an output amplifier boost mode that allows optimization of the amplifier slew rate. The control voltages generated by the DAC chip are 20 LNA bias voltages, 2 coldhead motor signals, 6 RF/noise warm electronics plate temperature set points and 5 LNA heater control voltages, a total of 33 signals, which can be produced by a single chip.


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Figure 13: Digital control board.

The AD7616 is a 16-channel, 16-bit, bipolar input ADC in an 80-lead LQFP package with independently selectable channel input ranges. This ADC operates from a single 5 V analogue power supply with a 2.3 V to 3.6 V drive. The AD7616 has a flexible parallel/serial interface that is SPI-/ QSPI-/MICROWIRE™-/DSP-compatible, and in our application is controlled by the SPI bus. The AD7616 device is used for the analogue monitoring functions, including LNA bias monitoring, pressure monitoring, and temperature monitoring. The total number of ADC monitoring channels needed is 30 for LNA bias monitoring, 15 for cryo temperature monitoring (on the horn, OMT and LNA of each band), 1 for ambient cryostat body temperature monitoring, 6 for RF/noise warm electronics plate monitoring, and 2 for pressure monitoring, totalling 54 channels. This is catered for by using four AD7616 chips, which provides a total of 64 channels.

Figure 14: Digital control board mounting arrangement.

SPI bus

AD5380DAC

Connector to analogue board

ADCAD7616

ADCAD7616

ADCAD7616

ADCAD7616

Trenz TE0720Xilinx Zynq 7020

Serial i/oFibre transceiver

PSU connection

heater control

to LNA bias control from LNA bias monitoringtemperature monitoring

7.0 V5.0 V3.5 V 0 V

Co

nn

ecto

r to

co

ldh

ead

dri

ve

bo

ard

SPI bus

Lid

FPGAThermal contact

Filtered feedthroughADC chips

FPC enclosure

FPGA boardStacking connector

Digital motherboard

DAC chip


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Figure 15: (Left) Internal block diagram of the AD5380 DAC chip (from Analog Devices) (Right)

AD5380 evaluation board.

Figure 16: (Left) Internal block diagram of the AD7616 ADC chip (from Analog Devices) (Right)

AD7616 evaluation board.

4.4 Analogue motherboard

The control and monitoring circuits are integrated in the analogue motherboard. This board occupies its own compartment within the FPC enclosure, connected to the PSU, digital and connector compartments via filtered D-type connectors in the compartment walls. It contains a number of distinct sections providing the various control and monitoring functions, described in the subsections below. The circuits in the analogue motherboard include readout circuit for vacuum gauges, cryostat body temperature monitor circuit, cryogenic temperature sensor, DAC voltage connectors for the LNA heater drivers and cryogenic LNA bias boards (daughter boards). The schematic of the analogue motherboard is shown in Figure 17. The motherboard is connected to the digital unit via filtered connectors. The current status of this board is that all the major functions have been prototyped on


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individual boards. The remaining design task is to integrate these functions and the appropriate connectors and signal routing in to a single board.

Figure 17: Block diagram of the FPC345 analogue motherboard.

4.4.1 Pressure Monitoring

The vacuum pressures are monitored using two BOC Edwards APGX Linear Active Pirani gauges. One gauge monitors the cryostat internal pressure, the other the pressure in the backing line outside the vacuum valve. This allows safe conditions for the opening and closing of the value to be monitored. The gauges are powered by a 24 V DC voltage supplied from the DC-PSU. The output analogue signal is a DC voltage of 2 to 10 V, corresponding to the vacuum pressure between 3.0E-4 mBar to 1333 mBar (see Figure 18) which is read by the readout circuit in the analogue motherboard. The signal line is connected to one channel of the ADC via a unity-gain op-amp buffer. The ADC input can be configured to read this voltage range directly.


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Figure 18: Active Pirani vacuum gauge and its voltage-pressure response curve.

4.4.2 LNA Bias daughter boards

The LNA bias circuits for each of the five bands are implemented as daughter boards connected to the main analogue motherboard, each board supplying both polarization channels. The boards for bands 5a and 5b are described below. Similar or identical circuits will be used for bands 3, 4 and 6.

The LNA bias circuit (see Figure 21) is based on a design supplied by Low Noise Factory, with modifications to allow the drain voltage and drain current to be set using outputs from the DAC on the digital board. The outputs are controlled by the two input voltages, VD_IN and ID_ADJUST; these two voltages are supplied by the DAC. VD_IN is fed into U1B, which has an emitter follower Q2 and R1 as part of its feedback loop. This emitter follower is responsible for delivering current through the output terminal VD_OUT; the feedback loop formed by Q2 and R1 ensure that VD_OUT is equal to VD_IN. VD_OUT is also fed to a buffer U1A which in turn drives one input of the differential amplifier U1C. The other input of this differential amplifier is taken from the emitter of Q2. The output of this differential amplifier is a voltage equal to that developed across R1, which is proportional to the output current. The input voltage ID_ADJUST is inverted by U1D and its output drives one of the inputs to the integrator U2A. The other input of this integrator is driven by the differential amplifier U1C. So, the output of this integrator is driven by the difference between the output of U1D (current demand) and the output of U1C (a measure of output current). When these two voltages are equal there is no change in the output of the integrator, which is essentially the gate voltage of the LNA. The gate voltage is monitored via U2B and U5C, and the output current is monitored via U5B and the output voltage VD_OUT is monitored from U5A.

This circuit has been implemented (see Figure 19) and tested with example LNAs, and controlled from the FPGA and DAC evaluation board. A final layout will incorporate suitable connectors for stacking on the analogue interface board.

Shop online at www.bocedwards.com

11PAGE

7

ME

AS

UR

EM

EN

T A

ND

CO

NT

RO

L

APG ACTIVE PIRANI GAUGESATMOSPHERE TO 10-4 mbar

The BOC Edwards Active Pirani Gauges (APG) combine the gauge head and controller in one compact active unit. The well proven, cost effective and reliable Pirani range has a substantial user base with a successful track record in the measurement of rough and backing pressures across a broad spectrum of applications.

Features & benefits• Wide range, regulated, internal power supply

- Runs from standard d.c. power supplies +20 to +36 V- Tolerant to voltage fluctuations

• Drive electronics combined in the gauge head- Reduces the system cost- Saves valuable rack space

• Medium and low pressure versions available- APG-M and -MP from atmosphere to 10-3 mbar- APG-L from atmosphere to 10-4 mbar

• Standard analog output 0 to 10 V d.c.- Easy to interface with a computer or plc- Fault output indication

• Adjustable set-point- For process control and interlocking- Provides vacuum status indication- Set-point level read visually or with voltmeter

• Low output impedance and integral Faraday shield- Provides high level of noise immunity- Permits long cable runs (up to 100 m)

• Corrosion resistant versions available• Two tube types (AI & St St) & numerous flange types to suit customer

applications

C = Allowance for cable and connector

TECHNICAL DATA

A B

NW16 22 mm/0.86 in 120 mm/4.72 inNW25 22 mm/0.86 in 124 mm/4.88 in15 mm OD 52 mm/2.05 in 150 mm/5.91 in

VA

S

98 (

3.86

)

56 (2.20) 34 (1.34)

B

A

(0.5

5)C

=14

Pressure rangeAPG-M & APG-MP Atmosphere to 10-3 mbar / TorrAPG-L Atmosphere to 10-4 mbar / Torr

Accuracy*APG-M & APG-MP Typically ±15% at <100 mbar / TorrAPG-L Typically ±15% at <10 mbar / Torr

Maximum over pressure 10 bar absolute (145 psi)Power supply +20 to +36 V d.c. (max 1 V ripple)Power consumption 1.5 W maxOutput signal 2 to 10 V d.c.Adjustments Set vacuum and set atmosphereSet-point Open collector transistor

Range of set-point 5% to 95% full-scale voltageFixed hysteresis 7% full-scale voltageLevel setting resolution ±2% full-scale voltageRating 40 V d.c., 100mA max

Temperature rangeOperating +5 to +60 °CStorage -30 to +70 °C

Materials exposed to vacuumAluminum tube Aluminum, nickel, fluoroelastomer,

PTFEStainless steel tube Stainless steel (316), nickel,

fluoroelastomer, PTFEFilament

APG-M, APG-L Gold-coated tungstenAPG-MP Platinum / rhodium (90/10)

Internal volume NW: 6 cm3 15 mm O.D.: 10 cm3

WeightAluminum 0.12 kgStainless steel 0.2 kg

External interface connector 8 way FCC68 / RJ45 socketVacuum fitting NW16, NW25 or 15 mm O.D.

tube

* Accuracy is reduced at the limits of the measuring range

10-5

1

2

3

4

5

6

7

8

9

10

11

-410

-310

-210

-110

010

110

210 10

3

APG-L

APG-M, APG-MP

V

10-3

10-2

10-1

100

101

102

103

104

105

APG

mbar

Pa

10-5

1

2

3

4

5

6

7

8

9

10

11

-410

-310

-210

-110

010

110

210 10

3

APG-L

APG-M, APG-MP

V

APG

Torr


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Figure 19: Prototype LNA bias card.

4.4.3 Temperature monitoring circuit

Cryogenic temperature sensing is done using TVO glass temperature sensors. We use a 4-wire scheme with separate wiring for current drive and voltage sensing. This method prevents voltage drops across the sensor wires from being included in the readings. The circuit is based on that used in Band 2, with some modifications to use 4-wire rather than 2-wire sensing, and to accommodate the different resistance range of the sensors. The constant current source is provided using an AD8226 integrated instrumentation amplifier (U1 in Figure 20). The voltage is then sensed using a 3-op-amp instrumentation amplifier circuit (U2.2, U3.1, U3.2). The voltages detected by this circuit are then connected to the ADC chip on the digital control board. A prototype of this board has been constructed and tested (see Figure 22). Sixteen channels of this design will be replicated on the analogue interface board. The same monitor circuit in the analogue motherboard will be used for the cryostat body temperature sensor. The proposed temperature sensor is an inexpensive transducer series NTC thermistor, NTCASCWE3, which will be mounted on the cryostat backplate. The monitor circuit uses one ADC channel in the digital unit to read the data from the sensor.

Figure 20: Cryogenic temperature sensor monitoring circuit.


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Figure 21: LNA Bias Circuit


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Figure 22: Prototype temperature monitoring circuit hardware.

4.4.4 Noise diode driver

The noise diode is driven by a 28V, 30 mA, current-stabilised supply. The noise diode itself is temperature controlled to maintain power output stability, but providing a current-stabilized rather than voltage-stabilized supply provides additional power stability. Figure 23 shows the drive circuit. The noise diode is controlled by a direct fibre connection from the SPFC, to ensure very low latency in the switching of the calibration source. Rather than switch the diode bias current, we keep the diode switched on all the time, and use an RF SPDT switch (Analog Devices HMC547) to switch the diode output on and off. This is because even with the diode mounted on a temperature-stabilized plate (the same kind as used for the warm RF electronics), the self-heating of the diode causes a drift in power output shortly after it switches on. Keeping the diode switched on permanently removes this source of instability. The SPDT switch is intrinsically very fast (it is based on GaAs FETs with a bandwidth of 20 GHz), and the switch-on rate is set by the Schmidt trigger which provides the control voltage to the switch, at approximately 1 µs.

Figure 23: Constant-current drive circuit for the noise diode.

4.4.5 LNA heater driver

The temperature of cryogenic LNAs is controlled using a cryogenic temperature sensor and heater mounted on the LNA carrier. The heater current is generated from the DAC, buffered by an op-amp on the analogue motherboard. The LNA heater itself is a 220 ohm resistor, and draws a maximum current of 10 mA. A proportional-integral (PI) controller in the FPGA module, taking temperature readings from the cryogenic temperature sensors, provides the heater voltage. Figure 24 shows the block diagram of the loop control and monitoring of the LNAs’ temperatures.


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Figure 24: Control and monitoring of the temperature of cryogenic LNAs using heater driver and

temperature sensors.

4.4.6 Warm RF plate control

The warm RF electronics and noise sources are mounted on temperature controlled plates in the vacuum volume. The temperature control is done locally with an analogue PID loop. The temperature set-point for each plate is controlled with a single analogue voltage generated by the DAC. Monitoring of the temperature is likewise via an analogue voltage read by the ADC. In addition, a digital TTL level signal indicates whether the voltage regulators on the board which power the second-stage amplifiers are producing the correct voltage. This signal is routed back to a digital I/O line on the FPGA board.

4.5 Coldhead stepper motor controller

The stepper motor controller circuit is show Figure 26. It produces two 48V-pp sinusoidal waves in phase quadrature, which drive the stepper motor. The data for these sinusoidal waves are derived from the serial motor drive input, which comes as a direct feed from the FPGA. This serial link is split between U4 (sine DAC) and U2 (cosine DAC), which both share the same clock input; the frequency of this clock determines the frequency of the sinusoidal waves. At any point in time, only one of these DACs is switched on; this is achieved by taking the respective active low sync input low. When this happens, a 14-bit word is clocked into that DAC and its analogue representation is produced at the output Vout; these 14 bit words are obtained from a lookup table in the FPGA. The phase difference between the DAC outputs is achieved by alternately accessing data which are spaced apart by π/2 radians. These outputs are then applied to a buffer/low pass filter combination, U6 and U8. Each combination is a 2nd order, low pass, Butterworth filter with a cut-off frequency of 300Hz. The outputs of each filter are then applied to simple high pass filters C2/R13 and C1/R14, which remove the CD component. The resulting sinusoidal waves are then fed to a dual power amplifier U3 which drives the stepper motor. The circuit has been prototyped (see Figure 25).


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Figure 25: Stepper motor controller prototype board.

Figure 26: Stepper motor controller schematic.


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4.6 FPGA firmware

4.6.1 Overview

The FPGA firmware implements the control and monitoring functions of the FPC. An FPGA is used rather than a microcontroller so that the safety-critical functions are implemented by a hardware state machine rather than by software, improving reliability and safety. However, our selected FPGA includes an ARM processor core so non-critical functions can also be implemented in software. Figure 27 shows the top-level states of the firmware architecture. When in application mode, a number of firmware modules implement the various control and monitoring functions which then run in parallel in different parts of the FPGA fabric (see Figure 28). A state machine controls the operation of safety-critical hardware such as the opening of the vacuum valve (see Section 4.6.2).

At the time of writing, the firmware is still under development, and not all functions have been implemented. However, key functions have been demonstrated – serial communications, LNA bias control, communication with DAC and ADC chips, coldhead stepper motor control – and completion of the complete control functionality is not considered to be a major risk.

Figure 27: States and modes of the FPC.

4.6.2 Safety state machine

On/off control functionality for the key components of the Band 345 feed package are controlled via a single 16-bit register within the FPGA, summarised in Table 4. These bits will be connected directly to digital I/O lines, buffering and switching electronics (e.g. solid state relays) to switch the required currents. Requests for changes in the states of each bit of this register are sent via serial commands from the SPFC. There are certain transitions between states of these 16 bits in the register which must be prevented for safety reasons, and in these cases the safety state machine will not update the state register, and an error message will be returned to the SPFC. The allowed and disallowed transitions of the stage register are summarised below.

OFF-LINE

ON-LINE*JA / 5s timeout

UPDATE

*FP

*JF

XModemEOT

*QI

*QI

*RU

MAINTENANCE APPLICATION

INITIALISE

Config Done

OFF

Power Up

Power Down

Power Down


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Figure 28: Structure of firmware modules within the FPGA.

Table 4: Bits of the FPGA state register

Channel Number Register bit [hex]

Description

1. 0x00 Vacuum Valve open/closed

2. 0x01 Cold Head Motor on/off

3. 0x02 Getter Activation Heater on/off

4. 0x03 Getter Regeneration Heater on/off

5. 0x04 Band Channel Select 3

6. 0x05 Band Channel Select 4

7. 0x06 Band Channel Select 5a

8. 0x07 Band Channel Select 5b

9. 0x08 Band Channel Select 5c

44UART

44

Command interpreter

44Safety statemachine

44ARM core

44LNA bias control

44Pressure monitor

44

44Cold head motor drive

44LNA|2nd

Temp PID

44

OUTPUTS

44

INPUTS

44SPI 1 44DAC

44ADC

44Flash memory

44D I/0

Requested State register

State register

Temperature monitor

44SPI 2

44ADC

Serial I/O

Vacuum valveTurbo pumpNEG pump


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10. 0x09 Turbopump on/off

11. 0x0A Band 3 H&V LNAs on/off

12. 0x0B Band 4 H&V LNAs on/off

13. 0x0C Band 5a H&V LNAs on/off

14. 0X0D Band 5b H&V LNAs on/off

15. 0x0E Band 6 H&V LNAs on/off

16. 0x0F (spare)

Channel No. 1 (Vacuum valve)

Vacuum valve closed (default, safe, startup state) = 0, Vacuum valve open = 1.

Background: There are two vacuum pressure sensors, (1) the interior vacuum sensor and (2) the pump-line sensor. If the interior is under vacuum, the valve should not be opened (to prevent a sudden in-rush of air the wrong way past the turbo pump).

Request to go from 0 to 1 (Opening the valve):

• If the pressure in the interior is equal to the pump-line pressure, we can go from 0 to 1 (opening the valve).

• If the pressure in the interior is lower than the pump-line pressure, we cannot go from 0 to 1 (valve remains closed and we send an ILLEGAL_OPENING_A error back to the SPFC).

• If the pressure in the interior is higher than the pump line, by less than some pressure, we can go from 0 to 1, opening the valve.

• If the pressure in the interior is higher than the pump line, by more than some pressure, we cannot go from 0 to 1, (valve remains closed and we send an ILLEGAL_OPENING_B error back to the SPFC).

Request to go from 1 to 0 (Closing the valve):

• There are no circumstances in which closing the valve can cause damage, so this is executed in all cases.

Channel No. 2 (Coldhead start/ stop)

Background: There is no point in running the coldhead to begin cooling unless the interior vacuum pressure is less than 3e-4 mBar (the lowest reading point of our Linear Active Pirani Gauge vacuum sensors). Doing so might lead to interior ice formation within the cryostat and would likely result in the vessel not becoming cold.

Request to go from 0 to 1 (from stop to start)

• If interior pressure is greater than 3e-4 mBar, we cannot go from 0 to 1 and we should send an ILLEGAL_COLDHEAD_REQ error.

• If interior pressure is less than 3e-4 mBar, we can go from 0 to 1.


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Request to go from 1 to 0 (from running to stop)

• This is safe to do in all cases so we can always go from 1 to 0.

Channels No. 3 and 4 (Getter activate / regeneration).

Background: Getter activation and regeneration must always occur under vacuum.

Request to go from 0 to 1 (from off to on)

• If interior pressure is greater than 3e-4 mBar, we cannot go from 0 to 1 and we should send an ILLEGAL_GET_ACT (bit 3) or ILLEGAL_GET_REGEN (bit 4) error.

• If interior pressure is less than 3e-4 mBar, we can go from 0 to 1.

Request to go from 1 to 0 (from on to off)


Channels 5 to 9 (Band channel selects)

These bit set request can always be honoured as there are no relevant safety issues.

Channel 10 (Turbo pump on/off)

Background: The turbo pump can be damaged if it is turned on while not under vacuum. There is no point in turning on the turbo pump unless the valve directly behind the turbo pump is open.

Request to go from 0 to 1 (from stop to start)

• If interior pressure is greater than 0.5 mBar, we cannot go from 0 to 1 and we should send an ILLEGAL_TURBO_POOR_VAC error.

• If vacuum valve is not open (i.e. bit 1 is zero), we cannot go from 0 to 1 and we should send an ILLEGAL_TURBO_CLOSED_VALVE error.

• If interior pressure is less than 0.5 mBar, we can go from 0 to 1.

Request to go from 1 to 0 (from running to stop)


Channel No. 11 to 15 (LNA PSUs on or off)

Background: The LNAs have two useful bias conditions: (1) Cold State Bias – gives best noise temperature when cold, but the LNAs will also run safely for these bias levels when they are warm. (2) Warm State Bias - gives best noise temperature when warm, but will lead to damage if set to these bias values when the amplifiers are cold.

• If the bias state voltages are within the warm ranges (defined by a look-up table within the FPGA) and 2nd stage central hub temperature is below 85K we cannot go from 0 to 1 and we should send an ILLEGAL_LNA_N_BIAS_STATE error (N refers to which particular bands LNAs).

• It should always be safe to turn the LNAs off, so a request from 1 to 0 can always be honoured.

4.6.3 Serial communications

The serial communications module controls the UART, which provides the serial connection to the SFPC. It also implements the command interpreter for the command language to the SFPC, and the XMODEM-1k interface for the exchange of binary files such as firmware updates. For requests which


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are simply for information (e.g. temperature monitoring values) the command interpreter sends requests directly to the relevant monitoring module, collects the information, creates the command response, and sends it via the UART to the SPFC. For commands involving a change of state, the request is passed to the safety state machine, which interprets the command in the light of the current state, either executing the change of state or returning an error code, which the command interpreter returns to the SPFC.

4.6.4 SPI interface controller

Both the ADC and DAC chips communicate with the FPGA via an SPI interface. Two separate instances of the SPI interface firmware are used to control these two interfaces in parallel. The SPI controllers repeatedly either poll the ADCs for new values, and update these to a shared memory register, or poll the DAC memory resister for new values and send these to the DAC. Other processes can access these registers asynchronously to either acquire new ADC data or send out new control values via the DAC.

4.6.5 Temperature monitoring

The cryogenic temperature sensors and the ambient temperature cryostat body sensor are controlled using the same bias/monitoring circuit (see Section 4.4.3). The sensor circuits are read out regularly by the ADC SPI-bus process and placed in to a shared register. The temperature monitoring process picks up these values and translates them using interpolation from look-up tables from raw ADC units to physical temperature units. These values are written in to another set of registers where they are available to the command interpreter for direct information requests, and to the state machine for checking if transition conditions are valid.

4.6.6 Pressure monitoring

The pressure monitoring functions in a very similar way to the temperature monitoring, translating raw ADC values to pressure units and making these available.

4.6.7 Coldhead motor control

The coldhead motor control generates the waveforms needed to drive the motor of the Oxford Cryosystems 6/30 coldhead (see Section 4.5). Sine and cosine waveforms are pre-calculated and loaded in to the DAC via the SPI serial interface. By varying the clock rate of the readout the drive speed of the coldhead can be varied.

4.6.8 LNA temperature control firmware

This firmware has not been written yet, but it will use a standard PID loop to control the current in a heater element, subject to the temperature measured by a cryogenic temperature sensor.

4.6.9 LNA bias monitoring/control firmware

The bias monitoring and control firmware is responsible for setting up the correct bias states, and providing monitored values of the bias voltages and currents when requested. The LNAs are controlled with a single drain voltage and gate voltage per LNA. Although the gate voltage is the parameter that is set, the target value is the drain current. In the ‘off’ state, the drain voltage is set to zero and the gate voltage set to a large negative value such that the drain current will remain zero even when the drain voltage is increased. To bias the LNA, the drain voltage is first increased to the correct value. The


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drain voltage set voltage is generated from the DAC, controlled by the FPGA, and the monitored drain voltage is read back by the ADC. Once the correct drain voltage is reached (within a narrow band around the nominal value) the gate voltage is increased while monitoring the drain current until the correct value of the drain current is achieved. Once the correct bias parameters have been reached the firmware goes in to monitoring mode, where the bias values are simply monitored and not updated, unless it is requested to re-set the biases. There are three allowed states for the biases: off, cold values, and warm values. The cold values give the optimum noise performance with the LNAs cold. The warm values give useful gain when the LNAs are warm, but have much higher drain currents which could damage the LNAs if cold. This state is therefore disallowed by the safety state machine if the cryostat is warm.

4.6.10 Firmware updates

The firmware image for the FPGA is stored in flash memory on the FPGA board. Updated images will be transmitted to the board using the XMODEM-1k protocol from the SPFC, and written to the flash memory under software control from the ARM processor embedded in the FPGA.

4.6.11 Current state of development and remaining work.

At present, the LNA bias board control, coldhead stepper motor controller and temperature monitoring circuit are all fully developed. However, the firmware contains a number of unfinished sections; these include the following:

1. The PID loop for controlling the temperature of the LNAs. 2. A cubic spline interpolation routine for temperature measurement of the LNA and for pressure

monitoring. 3. Serial communication with the SPF345. Although a link has been established with the FPGA,

there still remains development in the areas of the command/response and XMODEM protocols.

4.7 Enclosure and physical layout

The design of the B345 FPC enclosure is based on the Band 2/Meerkat FPC enclosure. A solid model of Band 345 enclosure is shown in Figure 29. On one side is a mains power supply compartment, a DC power supply compartment and a compartment for the coldhead motor controller board. The other side of the enclosure has two compartments, one for the digital components (FPGA board, ADC and DAC boards) and one for the analogue motherboard. RFI shielding is provided with a conductive elastomer RF gasket that runs along the walls of the compartments. Connection between compartments will be via shielded and filtered D-type connectors. An O-ring encircling both cavities provides an environmental seal. A cable management space which is sealed to the side of the cryostat is accessible with the side panel of the enclosure removed. This provides access to both the filtered connectors which connect to the internal spaces of the enclosure, and to the hermetic connectors which connect to the cryostat vacuum space. Short jumper cables bridge between the two. In this way the EMC filtering and vacuum hermetic functions are separated out.


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Figure 29: Band 345 enclosure mechanical model (Left, exploded view; Right, attached to the rear of the B345 cryostat body). The internal partitions of the enclosure are not shown; these will be

detailed once all the PCB sizes are finalised.

4.8 Interfaces, harnesses and connectors

4.8.1 Exposed Interfaces

The choice of exposed interfaces for B345 FPC will be the same as those used for Band 2. For connections exposed to the outside environment, MIL-DTL-38999 connectors will be used. The contacts are copper alloy and the connectors can operate in harsh environments and high vibration. The environmental protection is IP67 (total protection against dust) and they are EMI shielded. For the fibre interface, outdoor ODC-4 environmentally sealed connectors will be used. The outdoor ODC-4 fibre connectors are water and dust proof and EMI protected. Both proposed external connectors are shown in Figure 30.

Figure 30: Typical Amphenol D38999 connectors (left) and ODC-4 fibre connector (right).

4.8.2 Internal Interfaces

4.8.2.1 Filtered Connectors

We will use the same filtered connectors as the Band 2 FPC for all internal connections between sub-compartments of the FPC enclosure. These are Spectrum Control’s series 700 high performance filtered connectors. The connectors are rated for 150 V, 5 A (0.3 A RF) and are available in 25, 37 and 50 pins The D-Sub 700 series have various configurations including right angle and straight PCB for both pin and socket contact and as an adapter. Figure 31 shows a typical series 700 D-Sub connector with the insertion loss performance of the EMI filters. For connection between pins and filtered D-Subs, FFTP twisted pair cable assemblies from Samtec will be used.


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Figure 31: Series 700 D-Sub filtered connector (50 Pins/Sockets) and its filter characteristics (see

trace E in the upper plot and trace D in the lower plot.)

Figure 32: FFTP Samtec twisted pair cable assembly (socket) for connection between D-Sub

connectors.

4.8.2.2 Hermetic Connectors

All connections to the cryostat are via the analogue motherboard. The connections leave the analogue motherboard compartment of the FPC enclosure on filtered D connectors in to a cable management space that is accessible when the FPC enclosure lid is removed. Connections from this space through the cryostat wall use hermetic MIL-SPEC Amphenol connectors. A total of 143 pins will be needed and so we will use two connectors: one 66 way (shell size 19) and one 79 way (shell size 21). These are illustrated mounted on the cryostat flange in Figure 33.


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Figure 33: The FPC345 cryostat flange with hermetic connectors.

4.8.2.3 Optical fibre

Similar to Band 2, the HFBR-x4ExZ-series fibre-optic transmitters and receivers from Avago Technologies with SC connectors will be used for the controller communication as well as for the calibration source switching signal. The transmitter will use an 820 nm wavelength light source.

Figure 34: SC fibre interface.

5 SAFETY

The safety aspects of the B345 FPC have been developed in accordance with feedback from the SKA Dish Systems Engineering Group and the Central Electronics Group at Oxford. The appropriate safety regulations and standards will be fully applied so that no risk to personnel or equipment is expected when handling or installing the B345 FPC. In summary,

• For the mains entrance, the connector D38999-20WC4PN specified in the Physical ICD between the SPF B345 and the DS will be used.

• There will be no EMC filter external to the mains input, instead an internal AC EMC filter will be mounted in an EMC tight cavity separated from the FPC circuitry. This will prevent the radiated RFI from the FPC circuits leaking through the input wiring.

• The FPC is supplied with AC power from the Dish Structure electrical distribution system via a 2A Circuit Breaker (Trip Curve C) in the Indexer Power Distribution Box. The maximum let-through energy of this circuit is specified not to exceed 13225 A2t (this is a Dish Structure Requirement). For Trip Curve C this implies an electrical fault current level between 1 kA and


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2 kA at the circuit breaker. Therefore a short circuit up to 2 kA in the FPC needs to be protected against. For this, fuses in the primary AC circuit of the SPF B345 FPC with an AC rupturing capacity of less than 2kA will be added to the circuit. Also, all wiring before the fuse will have a short circuit current rating of more than 2kA.

• For the lightning and surge protection, a Dehnguard LSP will be connected from the AC live to ground. The LSP will be used with a “Mains-side over current protector” of less than 125 A. The existing 2A Circuit Breaker (Trip Curve C) in the Indexer Power Distribution Box meets this requirement and so no additional fuse before the LSP and internal to the FPC will be required. In addition, the LSP will be remotely monitored to indicate possible faults.

• The AC mains components will be IEC/UL safety rated.

• The AC mains wiring will be at least 500 VAC rated. The IEC 60950-1 testing will be achieved by disconnecting the Dehn SPD and internal connectors. Then an electrical survivability test at 1500 VAC and an electrical insulation test at 500 VDC will be conducted between Live and Neutral and also between Live and Earth and Neutral and Earth on the AC input connector pins.

The required numbering and labelling of components for safety compliance are summarised below:

• Connectors will be numbered and labelled on the final product.

• Terminal connectors in the AC unit will be identified as Live and Neutral, frequency range and the AC voltage value (“Live, 230 V AC, 50-60 Hz” and “Neutral”). Similarly, the DC outputs will be identified with +/- connectors and the DC voltage value.

• Maximum currents will be identified in the schematics and in actual units where appropriate.

• All wiring routes for AC and DC voltages are clearly identified in the schematics accompanied

with the photos which shows their actual positions in the FPC345.

• The AC parts, including mains Earth input, LSP and AC EMI filters will be earthed tightly to the chassis of metal enclosure. The insulation of earth wires will be clearly identified with

different colours. The main earth point will be marked with the IEC PE symbol .

• IEC Hazardous Voltage warning will be used for the AC unit of the B345 FPC.

• Operator accessible parts inside the FPC345 of which the surface temperature could exceed

hazardous levels will be identified with the symbol .


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• The type reference and serial number will be labelled for the final FPC345 product as “SKA1 Dish SPF B345 FPC - SN #001-XXXX”.

6 CONCLUSIONS

This document consists of the design details of the SKA Bands 3,4,5 Feed Package Controller (FPC345). The selected COTS items for system implementation have been identified and the remaining design decisions are specified. To minimise risk, the design of FPC345 closely follows that of the Band 2/Meerkat FPC wherever possible.