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Speaker: Tsung-Yi Wu
FPGA Design Flow (Part 2): Simulation
Documents
Documents– http://www.engr.newpaltz.edu/~bai/CSE45
208/ModelSim%20tutorial.pdf– http://www.ece.utexas.edu/projects/ee360
m/spring2005/lab_resources/modelsim_tutorial.doc
– ModelSimHelpPDF Document
Design Process
Design Process
Why Do You Do Simulation?
Functional Verification Timing Verification Sign-off RTL
SimulationVerification: Design Behave as Required? (Timing/Function)•Register-Transfer-Level•Logic-Level (Gates)•Transistor-Level (Electrical)
Synthesis
MapSpecification toImplementation
Why Do You Do Simulation?
Functional Verification – Multi-Level Simulation
RTL
GL Netlist
Layout
Synthesis
DesignImplementation
SIMULATOR
TranslateMap
Place&Route
TranslateMap
Place&Route
Logic Simulation Flow
Logic Simulation Flow
Simulator(Verilog/VHDL)
Testbench
Netlist
Simulation Models
SDFSDF extraction
Pass/Fail
Verilog Software Simulators
Mentor ModelSim Silos III Verilog Simulator Synopsys VCS Cadence
– Verilog-XL: Interpreter– NC-Sim: Compiler
• NC-Verilog• NC-VHDL• Co-Simulation
ModelSim Tutorial
Starting ModelSim– Start Programs ModelSim XE II ModelS
im
ModelSim Tutorial
Create Project– File New
Project – Keep Default Library
Name
ModelSim Tutorial
Create Project – After hitting OK, an
Add items to the Project dialog pops out
– We can add already existing files to the project
ModelSim Tutorial
Compiling– Select Compile Compile All
ModelSim Tutorial
Simulaion– Click on the Library tab of the main window and th
en click on the (+) sign next to the work library. You should see the name of the module of the code that we have just compiled one.
Library Tab
ModelSim Tutorial
Simulaion – Double-click on the module to load the file– Now select view All Windows
ModelSim Tutorial
Simulaion – Locate the signals window and select the sig
nals that you want to monitor for simulation purposes.
ModelSim Tutorial
Simulaion – Select SimulateRunRun -All
ModelSim Tutorial
Wave Window
ModelSim Tutorial
Wave Window
ModelSim Tutorial
Printing the Wave Window– Printing from the wave window is simple as
you only need to select: File Print
Invoking ModelSim from ISE
Open the Project Navigator by Double-clicking on the ISE Icon or Going to Start Programs Xilinx ISE 6 Project Navigator
Invoking ModelSim from ISE
Add exisiting sources by selecting Project menu Add Source... Select “your test-bench” and click Open.
In Choose Source Type Window, Select Verilog Test Fixture File
Invoking ModelSim from ISE
Test-bench Example: tb_myled.v
`timescale 1ns/1psmodule tb_led;reg reset,clk;wire[5:0] q;
proc u1 (reset,clk,q);
initial begin reset=1; clk=0; #8 reset=0; #400; $finish;end
always #10 clk=~clk;
endmodule
Invoking ModelSim from ISE
Click your Test-bench in “Sources in Project” Area– The simulation
models will be shown in “Process for Source” area
Click
Invoking ModelSim from ISE
Double-Click Simulate Behavioral Model– ModelSim will be invoked
Double-Click Simulate Post-Place & Route Verilog Model– ModelSim will be invoked
A *.tdo Is Created for ModelSim to Execute
