Spartan-3A DSP Starter Board · 7/11/2008 · exp1_se_io_19 exp1_se_io_18 exp1_se_io_17 exp1_se_io_16 exp1_diff_p12 exp1_diff_p13 exp1_diff_p14 exp1_diff_p15 exp1_diff_n1 exp2_se_io_33

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

Avnet, Inc. Engineering Services Copyright 2007

0381257 1

Spartan-3A DSP Starter Board

B

1Friday, July 11, 2008 17

Sheet 1 - Lead SheetTitle


Date: Sheet of


0381257 1


B


Sheet 1 - Lead SheetTitle


Date: Sheet of


0381257 1


B


Sheet 1 - Lead Sheet

10/100/1000 PHY

DDR2 Termination

http://www.xilinx.com/s3adspstarter

7

Function

www.em.avnet.com/xilinx

1Cover Sheet

6

4

9

Sheet Number

5

3

Avnet Engineering Services

8

10


2Block Diagram

11

12

13

14

15

16

DAC Out

Config/Flash Memory

FPGA Bank 0

FPGA Bank 1

FPGA Bank 2

FPGA Bank 3

FPGA Power

DDR2 Memory

PHY Power

EXP Connector (JX1)

EXP Connector (JX2)

Board Power

17Revision History

Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate

on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished,

downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical,

photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright

laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents,

copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the

Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx

assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any

liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.

THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS

WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR

ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER

EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY,

FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.

IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL

DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN,

EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN

CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT

EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT

THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE

AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY.

The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring failsafe

controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or

weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk

Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk.

© 2006–2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx,

Inc. All other trademarks are the property of their respective owners.

Xilinx Document Control Number 0381257

07/11/08

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Title


Date: Sheet of


0381257 1


B


Sheet 2 - Block DiagramTitle


Date: Sheet of


0381257 1


B


Sheet 2 - Block DiagramTitle


Date: Sheet of


0381257 1


B


Sheet 2 - Block Diagram

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

EXP1_SE_IO_23EXP1_SE_IO_22EXP1_SE_IO_21EXP1_SE_IO_20EXP1_SE_IO_19EXP1_SE_IO_18EXP1_SE_IO_17EXP1_SE_IO_16

EXP1_DIFF_p12EXP1_DIFF_p13EXP1_DIFF_p14EXP1_DIFF_p15

EXP1_DIFF_n1

EXP2_SE_IO_33

SWITCH_PB3

SWITCH_PB2

EXP1_SE_IO_15EXP1_SE_IO_14EXP1_SE_IO_13EXP1_SE_IO_12EXP1_SE_IO_11EXP1_SE_IO_10EXP1_SE_IO_9EXP1_SE_IO_8EXP1_SE_IO_7EXP1_SE_IO_6EXP1_SE_IO_5EXP1_SE_IO_4EXP1_SE_IO_3EXP1_SE_IO_2EXP1_SE_IO_1EXP1_SE_IO_0


EXP1_DIFF_n2EXP1_DIFF_n3

EXP1_DIFF_p20EXP1_DIFF_p21



EXP1_DIFF_n11


EXP1_DIFF_p0



EXP1_SE_IO_32

EXP1_DIFF_p1



EXP1_SE_IO_33

EXP1_SE_IO_31

EXP1_DIFF_p2

EXP1_SE_IO_30

EXP1_DIFF_p3

EXP1_SE_IO_29


EXP1_SE_IO_28


EXP1_SE_IO_27EXP1_SE_IO_26EXP1_SE_IO_25EXP1_SE_IO_24

EXP1_DIFF_p8EXP1_DIFF_p9

EXP1_DIFF_p11

EXP1_DIFF_n0

SWITCH_PB1

EXP1_SE_IO_1

EXP1_SE_IO_0

EXP1_DIFF_p12

EXP1_DIFF_p13

EXP1_DIFF_p14

EXP1_DIFF_p15

EXP1_DIFF_n1

EXP1_DIFF_p17

EXP1_DIFF_p18

EXP1_DIFF_p19

EXP1_DIFF_n2

EXP1_DIFF_n3

EXP1_DIFF_p20

EXP1_DIFF_p21

EXP1_DIFF_n6

EXP1_DIFF_n7

EXP1_DIFF_n4

EXP1_DIFF_n5

EXP1_DIFF_n11

EXP1_DIFF_n8

EXP1_DIFF_n9

EXP1_DIFF_p0

EXP1_DIFF_n14

EXP1_DIFF_n15

EXP1_DIFF_n12

EXP1_DIFF_n13

EXP1_DIFF_p1

EXP1_DIFF_n18

EXP1_DIFF_n19

EXP1_DIFF_n17

EXP1_DIFF_p2

EXP1_DIFF_p3

EXP1_DIFF_n20

EXP1_DIFF_n21

EXP1_DIFF_p4

EXP1_DIFF_p5

EXP1_DIFF_p6

EXP1_DIFF_p7

EXP1_DIFF_p8

EXP1_DIFF_p9

EXP1_DIFF_p11

EXP1_DIFF_n0

CLK_125MHz

EXP1_DIFF_p16EXP1_DIFF_n16

EXP1_SE_IO_23

EXP1_SE_IO_22

EXP1_SE_IO_21

EXP1_SE_IO_20

EXP1_SE_IO_19

EXP1_SE_IO_18

EXP1_SE_IO_17

EXP1_SE_IO_16

EXP1_SE_IO_14

EXP1_SE_IO_13

EXP1_SE_IO_12

EXP1_SE_IO_11

EXP1_SE_IO_10

EXP1_SE_IO_9

EXP1_SE_IO_8

EXP1_SE_IO_7

EXP1_SE_IO_6EXP1_SE_IO_5

EXP1_SE_IO_4

EXP1_SE_IO_3

EXP1_SE_IO_2

EXP1_SE_IO_32

EXP1_SE_IO_33

EXP1_SE_IO_31

EXP1_SE_IO_30

EXP1_SE_IO_29

EXP1_SE_IO_28

EXP1_SE_IO_27

EXP1_SE_IO_26

EXP1_SE_IO_25

EXP1_SE_IO_24

EXP1_SE_IO_15

CLK_125MHz

SWITCH_PB4

Vcco_0+3.3V

Vcco_0

Vcco_0

EXP2_SE_IO_[0:33]4,5,15

EXP1_SE_IO_[0:33]14

EXP1_DIFF_p[0:21]14

EXP1_DIFF_n[0:21]14

EXP1_SE_CLK_IN 14

EXP1_DIFF_CLK_OUT_p 14

EXP1_DIFF_CLK_IN_n 14EXP1_DIFF_CLK_IN_p 14

EXP1_DIFF_CLK_OUT_n 14

FPGA_PUDC 5

EXP1_SE_CLK_OUT 14

EXP1_DIFF_p10 14EXP1_DIFF_n10 14

Title


Date: Sheet of


0381257 1


C


Sheet 3 - FPGA Bank 0Title


Date: Sheet of


0381257 1


C




Date: Sheet of


0381257 1


C


Sheet 3 - FPGA Bank 0

DNP

R149

1K

R149

1K

RP391KRP391K

18

27

36

45

R147

1K

R147

1K

C240 0.1uFC240 0.1uF

SW8

SPST

SW8

SPST

314

2

R15649.9R15649.9

SW5

SPST

SW5

SPST

314

2

R15749.9R15749.9

SW7

SPST

SW7

SPST

314

2

SW3

SW DIP-8

SW3

SW DIP-8

BANK 0U6A

XC3SD1800AFG676_1

BANK 0U6A

XC3SD1800AFG676_1

IO_L51p_0A3

IO_L45p_0A4

IO_L38p_0A8

IO_L36p_0A9

IO_L33p_0A10

IO_L29p_0A12

IP_0A13

IO_L26n_0_GCLK7A14

IO_L23n_0A15

IP_0A17

IO_L18n_0A18

IO_L15n_0A19

IO_L14n_0A20

IO_L07n_0A22

IP_0H18

IO_L08p_0H17

IO_L51n_0B3

IO_L45n_0B4

IO_L41p_0B6

IO_L42p_0B7

IO_L38n_0B8

IO_L36n_0B9

IO_L33n_0B10

IO_L29n_0B12

IO_L28p_0_GCLK10B13

IO_L26p_0_GCLK6B14

IO_L23p_0B15

IO_L19n_0B17

IO_L18p_0B18

IO_L15p_0B19

IO_L14p_0_VREF_0B20

IO_L09n_0B21

IO_L07p_0B23

IO_L16n_0H15

IP_0H13

IO_L44p_0C5

IO_L41n_0C6

IO_L42n_0C7

IO_L40p_0C8

IO_L34p_0C10

IO_L32p_0C11

IO_L30n_0C12

IO_L28n_0_GCLK11C13

IO_L22n_0C15

IO_L21n_OC16

IO_L19p_0C17

IO_L17n_0C18

IO_L11n_0C20

IO_L09p_0C21

IO_L05n_0C22

IO_L06n_0C23

IO_L44n_0D6

IP_0_VREF_0D7

IO_L40n_0D8

IO_L37n_0D9

IO_L34n_0D10

IO_L32n_0_VREF_0D11

IP_0D12

IO_L30p_0D13

IP_0_VREF_0D14

IO_L22p_0D16

IO_L21p_0D17

IO_L17p_0D18

IO_L11p_0D20

IO_L10n_0D21

IO_L05p_0D22

IO_L06p_0D23

IO_L48n_0E7

IO_L37p_0E10

IP_0E11

IO_L31p_0E12

IO_L24p_0E14

IO_L20n_0_VREF_0E15

IO_L13n_0E17

IP_0E18

IO_L10p_0E21

IO_L48p_0F7

IO_L52p_0_VREF_0F8

IO_L31n_0F12

IO_L27p_0_GCLK8F13

IO_L24n_0F14

IO_L20p_0F15

IO_L13p_0F17

IO_L02n_0F19

IO_L01n_0F20

IO_L52n_0_PUDC_BG8

IO_L47p_0G9

IO_L46p_0G10

IP_0_VREF_0G11

IO_L35p_0G12

IO_L27n_0_GCLK9G13

IP_0G14

IO_L16p_0G15

IO_L02p_0_VREF_0G19

IO_L01p_0G20

IO_L47n_0H9

IO_L46n_0H10

IO_L35n_0H12

IP_0J10

IO_L43p_0J11

IO_L39p_0J12

IP_0J13

IO_L25n_0_GCLK5J14

IP_0J15

IO_L12p_0J16

IP_0_VREF_0J17

IO_L43n_0K11

IO_L39n_0K12

IO_L25p_0_GCLK4K14

IO_L12n_0K16

IO_L08n_0G17

IP_0A7

IP_0G16

IP_0E9

IP_0D15

IP_0D19

IP_0B24

IP_0A5

IP_0A23

IP_0F9

IP_0E20

IP_0A24

IP_0G18

IP_0F10

IP_0F18

IP_0E6

IP_0D5

IP_0C4

R150

1K

R150

1K

C20

0.1uF

C20

0.1uF

R33 33R0R33 33R0

R148

1K

R148

1K

U7

OSC_HC53x_125mhZ

U7

OSC_HC53x_125mhZ

E/D1

n/c2

GND3

OUT4

n/c5

VDD6

RP401K

RP401K

18

27

36

45

SW6

SPST

SW6

SPST

314

2

R1 0R0R1 0R0J1

SMA Connector

J1

SMA Connector

1

5

234

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

DAC_G0

FLASH_A17FLASH_A16

FLASH_A19FLASH_A18

FLASH_A21FLASH_A20

FLASH_A23FLASH_A22

FPGA_RS232_RxFPGA_RS232_Tx

CLK_25.175MHz

DAC_G1

EXP2_SE20EXP2_SE33EXP2_SE32

EXP2_SE24

DAC_G2DAC_G3

FLASH_A1

DBG_Rx_p

LED1

LED5LED6

DAC_B0DAC_B1DAC_B2DAC_B3

DBG_Rx_n

LED4

FLASH_A0

LED2

LED3

LED8LED7

DAC_R0DAC_R1DAC_R2DAC_R3

DBG_Tx_p

FLASH_A3FLASH_A2

LED1

FLASH_A5FLASH_A4

FLASH_A7FLASH_A6

LED5

LED6

DIGI1_1DIGI1_2DIGI1_3DIGI1_4

DBG_Tx_n

FLASH_A9FLASH_A8

FLASH_A11FLASH_A10

FLASH_A13FLASH_A12

FLASH_A15FLASH_A14


LED2

LED3

LED8

LED7

EXP2_SE20EXP2_SE33EXP2_SE32

EXP2_SE24



FLASH_A17FLASH_A16

FLASH_A19FLASH_A18

FLASH_A21FLASH_A20

FLASH_A23FLASH_A22

FLASH_A3FLASH_A2

FLASH_A5FLASH_A4

FLASH_A7FLASH_A6

FLASH_A9FLASH_A8

FLASH_A11FLASH_A10

FLASH_A13FLASH_A12

FLASH_A15FLASH_A14

FLASH_A1FLASH_A0

CLK_25.175MHz

FPGA_RS232_Rx

FPGA_RS232_Tx

LED4

EXP2_SE29EXP2_SE28EXP2_SE17EXP2_SE19

EXP2_SE29EXP2_SE28EXP2_SE17EXP2_SE19

+3.3V+3.3V

+3.3V

Vcco_2

+3.3V

+3.3V

+3.3V

SAM_D8 10

DAC_G[0:3] 13

SAM_D9 10SAM_D10 10

DAC_B[0:3] 13

SAM_D11 10

DAC_R[0:3] 13

SAM_D12 10SAM_D13 10SAM_D14 10

SPISEL_1 5

SAM_IRQ 10

SAM_D15 10

FLASH_CE# 10FLASH_OE# 10

FLASH_WE# 10

SPISEL_2 5SPISEL_3 5

SAM_A0 10SAM_A1 10

SPISEL_4 5

SAM_A2 10SAM_A3 10SAM_A4 10SAM_A5 10SAM_A6 10SAM_D0 10SAM_D1 10SAM_D2 10SAM_D3 10SAM_D4 10

SAM_OEn 10

SAM_D5 10

SAM_WEn 10

FLASH_Reset# 10

SAM_D6 10

DAC_HSYNC 13

SAM_CEn 10

SAM_D7 10

SAM_RESETn 10

EXP2_SE_IO_20 15EXP2_SE_IO_24 15


FLASH_A[0:23] 10

SAM_BRDY 10

DAC_VSYNC 13

SUSPEND 7



Title


Date: Sheet of


0381257 1


C




Date: Sheet of


0381257 1


C




Date: Sheet of


0381257 1


C



Place resistors as

close as possible to

the FPGA

R108 681R108 681

BANK 1U6B

XC3SD1800AFG676_1

BANK 1U6B

XC3SD1800AFG676_1

IP_L52n_1_VREF_1G25

IP_L40p_1K24

IP_L40n_1L23

IP_L36p_1_VREF_1M24

IP_L36n_1N23

IP_L32n_1N25

IP_L32p_1N26

IP_L28p_1_VREF_1R23

IP_L28n_1R24

IP_L65p_1_VREF_1B26

IP_L48n_1H24

IP_L44p_1_VREF_1H26

IP_L24n_1_VREF_1U26

IP_L20n_1_VREF_1V26

IO_L01p_1_HDCY20

IO_L01n_1_LDC2Y21

IO_L02p_1_LDC1AE26

IO_L02n_1_LDC0AD25

IO_L03p_1_A0AC23

IO_L03n_1_A1AC24

IO_L04p_1W20

IO_L04n_1W21

IO_L05p_1AD26

IO_L05n_1AC25

IO_L06p_1AC26

IO_L06n_1AB26

IO_L07p_1AB23

IO_L07n_1_VREF_1AB24

IO_L08p_1V18

IO_L08n_1V19

IO_L09p_1AA22

IO_L09n_1AA23

IO_L10p_1V21

IO_L10n_1U20

IO_L11p_1AA24

IO_L11n_1AA25

IO_L12p_1U19

IO_L12n_1U18

IO_L13p_1Y22

IO_L13n_1Y23

IO_L14p_1U21

IO_L14n_1T20

IO_L15p_1Y24

IO_L15n_1Y25

IO_L17p_1T18

IO_L17n_1T17

IO_L18p_1W23

IO_L18n_1V22

IO_L19p_1V24

IO_L19n_1V25

IO_L21p_1V23

IO_L21n_1U22

IO_L22p_1R19

IO_L22n_1R20

IO_L23p_1U23

IO_L23n_1_VREF_1U24

IO_L25p_1_A2R21

IO_L25n_1_A3R22

IO_L26p_1_A4T23

IO_L26n_1_A5T24

IO_L27n_1_A7R17

IO_L27p_1_A6R18

IO_L29p_1_A8R25

IO_L29n_1_A9R26

IO_L30p_1_RHCLK0P21

IO_L30n_1_RHCLK1P20

IO_L31p_1_RHCLK2P26

IO_L31n_1_TRDY1_RHCLK3P25

IO_L33p_1_RHCLK4P23

IO_L33n_1_RHCLK5N24

IO_L34p_1_RDY1_RHCLK6P18

IO_L34n_1_RHCLK7N19

IO_L35p_1_A10M26

IO_L35n_1_A11M25

IO_L37p_1P22

IO_L37n_1N21

IO_L38p_1_A12L24

IO_L38n_1_A13M23

IO_L39p_1_A14N18

IO_L39n_1_A15N17

IO_L41p_1K25

IO_L41n_1K26

IO_L42p_1_A16N20

IO_L42n_1_A17M20

IO_L43p_1_A18J26

IO_L43n_1_A19J25

IO_L45p_1M21

IO_L45n_1M22

IO_L46p_1K23

IO_L46n_1K22

IO_L47p_1M19

IO_L47n_1M18

IO_L49p_1J23

IO_L49n_1J22

IO_L50p_1L22

IO_L50n_1K21

IO_L51p_1G23

IO_L51n_1G24

IO_L53p_1L20

IO_L53n_1K20

IO_L54p_1F25

IO_L54n_1F24

IO_L55p_1L18

IO_L55n_1L17

IO_L56p_1E24

IO_L56n_1F23

IO_L57p_1K19

IO_L57n_1K18

IO_L58p_1_VREF_1F22

IO_L58n_1G22

IO_L59p_1J19

IO_L59n_1J20

IO_L60p_1E26

IO_L60n_1D26

IO_L61p_1D25

IO_L61n_1D24

IO_L62p_1_A20J21

IO_L62n_1_A21H21

IO_L63p_1_A22C26

IO_L63n_1_A23C25

IO_L64p_1_A24H20

IO_L64n_1_A25G21

IP_L16n_1Y26

IP_L44n_1H25

IP_L16p_1W25

IP_L24p_1U25

IP_L65n_1B25

IP_L20p_1W26

IP_L48p_1H23

IP_L52p_1G26

R103 681R103 681

R105 681R105 681

D7LED_GREEN

D7LED_GREEN

D10LED_GREEN

D10LED_GREEN

R9 49R9R9 49R9

R118.25KR118.25K

C29 0.1uFC29 0.1uF

1 2

R10 100R10 100

P2

CO

NN

EC

TO

R D

B9

P2

CO

NN

EC

TO

R D

B9

594837261

10

11

12

13

C1

0.1uF

C1

0.1uF

C30

0.1uF

C30

0.1uF

12

D12LED_GREEN

D12LED_GREEN

R107 681R107 681

D13LED_GREEN

D13LED_GREEN

R6 49R9R6 49R9

R39 10R0R39 10R0

1 2

R22 33R0R22 33R0

U10

MAX3221

U10

MAX3221

EN1

C1+2

V+3

C1-4

C2+5

C2-6

V-7

RIN8

ROUT9

INVALID10

DIN11

F_ON12

DOUT13

GND14

VCC15

F_OFF16

J7

J7

123456

D14LED_GREEN

D14LED_GREEN

D9LED_GREEN

D9LED_GREEN

R84.99KR84.99K

J3

SA

TA

Connecto

r

J3

SA

TA

Connecto

r

1234567

U5

SN74CB3T3245DGVR

U5

SN74CB3T3245DGVR

n/c1

A12

A23

A34

A45

A56

A67

A78

A89

GND10

B811

B712

B613

B514

B415

B316

B217

B118

OE19

VCC20

C32 0.1uFC32 0.1uF

1 2

R12 49R9R12 49R9

R106 681R106 681

D8LED_GREEN

D8LED_GREENR104 681R104 681

U4

OSC_HC53x_25.175mhZ

U4

OSC_HC53x_25.175mhZ

E/D1

n/c2

GND3

OUT4

n/c5

VDD6

C56

0.1uF

C56

0.1uF

C27

0.1uF

C27

0.1uF

12

J6

J6

123456

C28 0.1uFC28 0.1uF

1 2

R109 681R109 681

R7 49R9R7 49R9

D11LED_GREEN

D11LED_GREEN

R110 681R110 681

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

EXP2_DIFF_p0EXP2_DIFF_p1EXP2_DIFF_p2EXP2_DIFF_p3EXP2_DIFF_p4EXP2_DIFF_p5EXP2_DIFF_p6EXP2_DIFF_p7EXP2_DIFF_p8EXP2_DIFF_p9

EXP2_DIFF_p11EXP2_DIFF_p12EXP2_DIFF_p13EXP2_DIFF_p14EXP2_DIFF_p15EXP2_DIFF_p16EXP2_DIFF_p17EXP2_DIFF_p18EXP2_DIFF_p19EXP2_DIFF_p20EXP2_DIFF_p21

EXP2_DIFF_n0EXP2_DIFF_n1EXP2_DIFF_n2EXP2_DIFF_n3EXP2_DIFF_n4EXP2_DIFF_n5EXP2_DIFF_n6EXP2_DIFF_n7EXP2_DIFF_n8EXP2_DIFF_n9

EXP2_DIFF_n11EXP2_DIFF_n12EXP2_DIFF_n13EXP2_DIFF_n14EXP2_DIFF_n15EXP2_DIFF_n16EXP2_DIFF_n17EXP2_DIFF_n18EXP2_DIFF_n19EXP2_DIFF_n20EXP2_DIFF_n21

EXP2_SE_IO_0EXP2_SE_IO_1EXP2_SE_IO_2EXP2_SE_IO_3EXP2_SE_IO_4EXP2_SE_IO_5EXP2_SE_IO_6EXP2_SE_IO_7EXP2_SE_IO_8EXP2_SE_IO_9EXP2_SE_IO_10EXP2_SE_IO_11EXP2_SE_IO_12EXP2_SE_IO_13EXP2_SE_IO_14EXP2_SE_IO_15EXP2_SE_IO_16

EXP2_SE_IO_18

EXP2_SE_IO_20EXP2_SE_IO_21EXP2_SE_IO_22EXP2_SE_IO_23EXP2_SE_IO_24EXP2_SE_IO_25EXP2_SE_IO_26EXP2_SE_IO_27

EXP2_SE_IO_30EXP2_SE_IO_31EXP2_SE_IO_32EXP2_SE_IO_33

EXP2_DIFF_n13EXP2_DIFF_p13EXP2_DIFF_n16

FLASH_D0FLASH_D1FLASH_D2

FLASH_D4FLASH_D5FLASH_D6FLASH_D7

FLASH_D3

FPGA_M0

FPGA_M2FPGA_M1

SPI_MOSISPI_MISOSPI_CLK

CLK_Socket


EXP2_SE_IO_0

EXP2_DIFF_p0

EXP2_DIFF_p1

EXP2_DIFF_p2

EXP2_DIFF_p3

EXP2_DIFF_p5

EXP2_DIFF_p6

EXP2_DIFF_p4

EXP2_DIFF_p7

EXP2_DIFF_p8

EXP2_DIFF_p9

EXP2_DIFF_p11

EXP2_DIFF_p12

EXP2_DIFF_p13

EXP2_DIFF_p16

EXP2_DIFF_n0

EXP2_DIFF_n1

EXP2_DIFF_n2

EXP2_DIFF_n3

EXP2_DIFF_n4

EXP2_DIFF_n5

EXP2_DIFF_n6

EXP2_DIFF_n7

EXP2_DIFF_n8

EXP2_DIFF_n9

EXP2_DIFF_n11

EXP2_DIFF_n12

EXP2_DIFF_n13

EXP2_DIFF_n16

EXP2_SE_IO_30SPI_MOSI


CLK_Socket


EXP2_DIFF_p20

EXP2_DIFF_p21

EXP2_DIFF_n20

EXP2_DIFF_n21

EXP2_SE_IO_1

EXP2_SE_IO_2

EXP2_SE_IO_3

EXP2_SE_IO_4

EXP2_SE_IO_5

EXP2_SE_IO_6

EXP2_SE_IO_7

EXP2_SE_IO_8

EXP2_SE_IO_9

EXP2_SE_IO_10

EXP2_SE_IO_11

EXP2_SE_IO_12

EXP2_SE_IO_13

EXP2_SE_IO_14

EXP2_SE_IO_15

EXP2_SE_IO_16

EXP2_SE_IO_18

EXP2_SE_IO_21

EXP2_SE_IO_22


EXP2_SE_IO_26

EXP2_SE_IO_27

EXP2_SE_IO_31

FLASH_D1FLASH_D2

FLASH_D4FLASH_D5

FLASH_D6FLASH_D7

FLASH_D3

FLASH_D0

SPI_SEL#



Vcco_2

Vcco_2

+3.3V

+3.3V

+3.3V

Vcco_2

+3.3V

EXP2_SE_IO_[0:33]4,15

EXP2_DIFF_p[0:21]15

EXP2_DIFF_n[0:21]15

PO_RESET# 16

FLASH_D[0:7] 10

SPISEL_14SPISEL_24SPISEL_34SPISEL_44

EXP2_DIFF_p10 15EXP2_DIFF_n10 15

EXP2_DIFF_CLK_OUT_n 15

EXP2_DIFF_CLK_OUT_p 15

EXP2_SE_CLK_OUT 15

EXP2_DIFF_CLK_IN_p 15EXP2_DIFF_CLK_IN_n 15

SAM_CLK 10

FPGA_INIT# 10

EXP2_SE_CLK_IN 15

FPGA_CCLK 10

FLASH_D0 10

SPI_MISO 10

SPI_SEL# 10

SPI_CLK 10

SPI_MOSI 10

FPGA_PUDC 3

Title


Date: Sheet of


0381257 1


C




Date: Sheet of


0381257 1


C




Date: Sheet of


0381257 1


C



DNP

VS[2:0] = b111 results in a

SPI read command of Fast Read

(0x0B) which is compatible

with Intel S33 Flash.

Resistors R34 - R37 and

R133-R134 are for variant

select (VS) to support SPI

configuration of the FPGA.

Closed Open Closed Closed

No

No

Yes

Closed Open Closed Open

No

Yes

No

Yes

Open Open Closed Closed

No

Yes

Open Open Closed Open

No

Yes

M1

Open Closed Open Closed

JP9 7:8

Open Closed Open Open

Master Serial

M0

Slave Serial

Closed Closed Closed Open

Closed

JP9 1:2

Master SPI

Closed

Open

BPI Up

Closed

Open

BPI Up

Open

Closed

Closed

PUDC_B

Open Open Open

Slave Parallel

M2

Open

Yes

Configuration Mode PC Pull-up JP9 3:4JP9 5:6

Master Serial

Slave Serial

Master SPI

Slave Parallel

JTAG

Closed Closed Open Closed

JTAG

Closed Closed Open OpenJP9 Default: JP9 3:4, 5:6

(Master SPI)

JP9JP9

2468

1357

D15

LED_GREEN

D15

LED_GREEN

R804.75KR804.75K

R351KR351K

R29 33R0R29 33R0

R371KR371K

R1331KR1331K

RP231K

RP231K

18

27

36

45

R341KR341K

C55

0.1uF

C55

0.1uF

R361KR361K

R1341KR1341K

OSC

U2

Fox H5C-2E3 compatible

OSC

U2

Fox H5C-2E3 compatible

VCC8

ENABLE1

GND4

OUT5

J10J10

2468

1012

1357911

R13233R0 R13233R0

RP244.7KRP244.7K

18

27

36

45

R131 1KR131 1K

R794.75KR794.75K

BANK 2U6C

XC3SD1800AFG676_1

BANK 2U6C

XC3SD1800AFG676_1

IP_2_VREF_2AA9

IP_2_VREF_2AA20

IP_2_VREF_2AB6

IP_2AB13

IP_2_VREF_2AC10

IP_2AC13

IP_2AC17

IO_2AC22

IP_2AD9

IP_2_VREF_2AD12

IP_2AD16

IP_2_VREF_2AF15

IP_2_VREF_2AF17

IP_2_VREF_2AF22

IP_2_VREF_2Y16

IO_L01p_2_M1AC4

IO_L01n_2_M0AD4

IO_L02p_2_M2Y7

IO_L02n_2_CSO_BAA7

IO_L05p_2W9

IO_L05n_2Y9

IO_L06p_2AE3

IO_L06n_2AF3

IO_L07p_2AE4

IO_L07n_2AF4

IO_L08p_2AC6

IO_L08n_2AD6

IO_L09p_2V10

IO_L09n_2W10

IO_L10p_2AF5

IO_L10n_2AE6

IO_L11p_2AD7

IO_L11n_2AE7

IO_L12p_2Y10

IO_L12n_2AA10

IO_L13p_2V11

IO_L13n_1U11

IO_L14p_2AC8

IO_L14n_2AB7

IO_L15p_2AB9

IO_L15n_2AC9

IO_L16p_2V12

IO_L16n_2W12

IO_L17p_2_RDWR_BY12

IO_L17n_2_VS2AA12

IO_L18p_2AE8

IO_L18n_2AF8

IO_L19p_2_VS1AE9

IO_L19n_2_VS0AF9

IO_L20p_2V13

IO_L20n_2W13

IO_L21p_2AB12

IO_L21n_2AC12

IO_L22p_2_D7AE10

IO_L22n_2_D6AF10

IO_L23p_2AD11

IO_L23n_2AC11

IO_L24p_2_D5AF12

IO_L24n_1_D4AE12

IO_L25p_2_GCLK12AA13

IO_L25n_2_GCLK13Y13

IO_L26p_2_GCLK14AF13

IO_L26n_2_GCLK15AE13

IO_L27p_2_GCLK0Y14

IO_L27n_2_GCLK1AA14

IO_L28p_2_GCLK2AF14

IO_L28n_2_GCLK3AE14

IO_L29p_2AD14

IO_L29n_2AC14

IO_L30p_2AC15

IO_L30n_2_MOSI_CSI_BAB15

IO_L31p_2V14

IO_L31n_2W15

IO_L32p_2_AWAKEAD15

IO_L32n_2_DOUTAE15

IO_L33p_2AE17

IO_L33n_2AD17

IO_L34p_2_INIT_BAA15

IO_L34n_2_D3Y15

IO_L35p_2V15

IO_L35n_2U15

IO_L36p_2_D2AF18

IO_L36n_2_D1AE18

IO_L37p_2AF19

IO_L37n_2AE19

IO_L38p_2AC16

IO_L38n_2AB16

IO_L39p_2AF20

IO_L39n_2AE20

IO_L40p_2AD19

IO_L40n_2AC19

IO_L41p_2AD20

IO_L41n_2AC20

IO_L42p_2V16

IO_L42n_2U16

IO_L43p_2AA17

IO_L43n_2Y17

IO_L44p_2AE21

IO_L44n_2AD21

IO_L45p_2AD22

IO_L45n_2AC21

IO_L46p_2W17

IO_L46n_2V17

IO_L47p_2AB18

IO_L47n_2AA18

IO_L48p_2AF23

IO_L48n_2AE23

IOIO_L51p_2AF25

IO_L51n_2AE25

IO_L52p_2_D0_DIN_MISOAF24

IO_L52n_2_CCLKAE24

IP_2AD10

IP_2AF7

IP_2AD5

IP_2AD23

IP_2AC5

IP_2AC7

IP_2AC18

IP_2_VREF_2AB10

IP_2AB20

IP_2AA19

IP_2AF2

IP_2AB17

IP_2Y8

IP_2Y11

IP_2Y18

IP_2_VREFY19

IP_2W18

IP_2AA8

R130 1KR130 1K

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

FPGA_DDR_D1FPGA_DDR_D2FPGA_DDR_D3


FPGA_DDR_D4


FPGA_DDR_D8


FPGA_DDR_D12


FPGA_DDR_D16


FPGA_DDR_D20


FPGA_DDR_D24

FPGA_DDR_A0


FPGA_DDR_D28

FPGA_DDR_A1FPGA_DDR_A2FPGA_DDR_A3FPGA_DDR_A4FPGA_DDR_A5FPGA_DDR_A6FPGA_DDR_A7FPGA_DDR_A8FPGA_DDR_A9FPGA_DDR_A10FPGA_DDR_A11

FPGA_DDR_D0

FPGA_DDR_A12

ETH_CRSETH_COLETH_Rx_DVETH_Rx_ERETH_INT#ETH_MCLKETH_Rx_CLKETH_Tx_CLK

ETH_Rx_D0ETH_Rx_D1ETH_Rx_D2ETH_Rx_D3ETH_Rx_D4ETH_Rx_D5ETH_Rx_D6ETH_Rx_D7

ETH_GTX_CLK

ETH_Tx_D0

ETH_Tx_D5

ETH_Tx_D1

ETH_Tx_D6

ETH_Tx_D2

ETH_RST#

ETH_Tx_D7

ETH_Tx_D3ETH_Tx_D4

ETH_Tx_ENETH_Tx_ER

ETH_Rx_D0ETH_Rx_D1

ETH_INT#

ETH_CRSETH_COL

ETH_Rx_DV

ETH_Rx_ER

ETH_Rx_D2ETH_Rx_D3

ETH_Tx_D2ETH_Tx_D3

ETH_Tx_CLK

FPGA_DDR_CLK0_pFPGA_DDR_CLK0_n

ETH_Tx_D6ETH_Tx_D7

ETH_Tx_D4ETH_Tx_D5

ETH_GTX_CLKETH_MDCETH_MDIOETH_RST#

ETH_Tx_ENETH_Tx_ER

ETH_MCLK

ETH_Tx_D0

FPGA_DDR_D19

FPGA_DDR_D17FPGA_DDR_D16


FPGA_DDR_D1


FPGA_DDR_D5


FPGA_DDR_D9


FPGA_DDR_D8

FPGA_DDR_D13

FPGA_DDR_D14

FPGA_DDR_D12

FPGA_DDR_D20


FPGA_DDR_D29


FPGA_DDR_D0

FPGA_DDR_CLK1_pFPGA_DDR_CLK1_n


FPGA_DDR_D15

FPGA_DDR_D18

FPGA_DDR_D21

ETH_Rx_CLK

ETH_Tx_D1

ETH_Rx_D4ETH_Rx_D5ETH_Rx_D6ETH_Rx_D7

DDR2_ODT

DDR2_CKE

DDR2_CAS#

DDR2_BS0

DDR2_WE#

DDR2_RAS#DDR2_CS#

CLK_FB_MB

DDR2_LDM_1

DDR2_UDQS#_1DDR2_UDQS_1

DDR2_UDQS#_0

DDR2_UDM_0DDR2_LDM_0

DDR2_LDQS#_1DDR2_LDQS_1


MB_FB_CLK

DDR2_A10DDR2_A9DDR2_A12DDR2_A11

FPGA_DDR_A7

DDR2_A2DDR2_BS1DDR2_A0

DDR2_A1DDR2_A4DDR2_A3DDR2_A6DDR2_A5DDR2_A8

DDR2_UDQS_0

RST_DQS_DIV

FPGA_DDR_CLK1_n

DDR2_A0

DDR2_A6

DDR2_LDM_0

DDR2_A12

DDR2_ODT

DDR2_RAS#DDR2_CS#

FPGA_DDR_CLK0_p

DDR2_CAS#DDR2_WE#

DDR2_A3

DDR2_CKE

DDR2_A8

DDR2_UDQS#_0DDR2_UDQS_0

DDR2_UDM_0


FPGA_DDR_CLK1_p

DDR2_A1

DDR2_A11

DDR2_A2

CLK_FB_MB

DDR2_UDQS_1DDR2_UDQS#_1

DDR2_LDM_1

DDR2_LDQS_1DDR2_LDQS#_1

FPGA_DDR_CLK0_n

DDR2_A10

DDR2_BS1

DDR2_A5

DDR2_A9

DDR2_A4

FPGA_DDR_A11

FPGA_DDR_A3

FPGA_DDR_A1

FPGA_DDR_A2

FPGA_DDR_A9FPGA_DDR_A6

FPGA_DDR_A8

FPGA_DDR_A0

MB_FB_CLK

FPGA_DDR_A4

FPGA_DDR_A12

FPGA_DDR_A10

FPGA_DDR_A5

ETH_MDIOETH_MDC

FPGA_DDR_D[0:31] 8,9

FPGA_DDR2_VREF

+2.5V+1.8V

+2.5V+1.8V

+1.8V +1.8V

FPGA_0.9V_TT

FPGA_0.9V_TT

FPGA_DDR2_VREF

+2.5V+1.8V

+1.8V +2.5V

+2.5V+1.8V

+1.8V

FPGA_DDR_A[0:12] 8,9

GMII_COL 11

GBEINT# 11GBE_MCLK 11

GMII_RXD5 11

GMII_RXD1 11

GMII_RX_DV 11

GMII_RXD3 11

GMII_RXD6 11

GMII_RXD2 11

GMII_RXD0 11

GMII_RXD4 11

GMII_RXD7 11

GMII_CRS 11

GMII_RX_ER 11

GMII_RX_CLK 11GMII_TX_CLK 11

GMII_TXD0 11GMII_TXD1 11GMII_TXD2 11GMII_TXD3 11GMII_TXD4 11GMII_TXD5 11GMII_TXD6 11GMII_TXD7 11GMII_TX_EN 11GMII_TX_ER 11

GMII_GTX_CLK 11

GBE_RST# 11

FPGA_DDR_BS0 8,9

FPGA_DDR_UDM_1 8,9

FPGA_DDR_CKE 8

FPGA_DDR_LDM_0 8,9

FPGA_DDR_CS# 8,9FPGA_DDR_RAS# 8,9

DDR2_ODT_Control 8

FPGA_DDR_WE# 8,9FPGA_DDR_CAS# 8,9

FPGA_DDR_BS1 8,9

FPGA_DDR_CLK_1 8FPGA_DDR_CLK_1# 8

FPGA_DDR_LDQS#_1 8,9FPGA_DDR_LDQS_1 8,9

FPGA_DDR_UDQS_0 8,9FPGA_DDR_UDQS#_0 8,9

FPGA_DDR_UDM_0 8,9

FPGA_DDR_LDQS#_0 8,9FPGA_DDR_LDQS_0 8,9

FPGA_DDR_LDM_1 8,9

FPGA_DDR_UDQS#_1 8,9FPGA_DDR_UDQS_1 8,9

FPGA_DDR_CLK_0 8FPGA_DDR_CLK_0# 8

GMII_MDIO 11GMII_MDC 11

Title


Date: Sheet of


0381257 1


C




Date: Sheet of


0381257 1


C




Date: Sheet of


0381257 1


C



1.8V

Place R136 closeto pin N7

MB_FB_CLK - This trace should havelength equal to DDR_CLK trace length +DQStrace length

RST_DQS_DIV - The trace from T10to T9 should have length equal toDDR_CLK trace length + DQStracelength

Place R135 closeto pin T9

C25

0.1uF

C25

0.1uF

R135 60R4R135 60R4

C133

0.01uF

C133

0.01uF

U9

ADG3304

U9

ADG3304

A12

A23

A34

A45

Y113

Y212

Y311

Y410

VCCA1

VCCY14

EN8

GND7

R140 24R3R140 24R3

C137

1.0uF

C137

1.0uF

RP11

33R0

RP11

33R0

18273645

RP4

33R0

RP4

33R0

18273645

U17

SN74AVC20T245ZQL

U17

SN74AVC20T245ZQL

1B1A1

1B2A2

1DIRA3

1OEA4

1A2A5

1A1A6

1B3B1

1B4B2

GNDB3

GNDB4

1A4B5

1A3B6

1B5C1

1B6C2

VCCBC3

VCCAC4

1A6C5

1A5C6

1B7D1

1B8D2

GNDD3

GNDD4

1A8D5

1A7D6

1B9E1

1B10E2

1A10E5

1A9E6

2B1F1

2B2F2

2A2F5

2A1F6

2B3G1

2B4G2

GNDG3

GNDG4

2A4G5

2A3G6

2B5H1

2B6H2

VCCBH3

VCCAH4

2A6H5

2A5H6

2B7J1

2B8J2

GNDJ3

GNDJ4

2A8J5

2A7J6

2B9K1

2B10K2

2DIRK3

2OEK4

2A10K5

2A9K6

R137 22R0R137 22R0

RP2

33R0

RP2

33R0

18273645

C203

0.1uF

C203

0.1uF

R136 60R4R136 60R4

C206

0.1uF

C206

0.1uF

C207

0.1uF

C207

0.1uFC201

0.1uF

C201

0.1uF

C205

0.1uF

C205

0.1uF

RP3

33R0

RP3

33R0

18273645

C208

0.1uF

C208

0.1uF

C127

0.01uF

C127

0.01uF

RP13

33R0

RP13

33R0

18273645

RP15

24R0

RP15

24R0

18273645

BANK 3U6D

XC3SD1800AFG676_1

BANK 3U6D

XC3SD1800AFG676_1

IP_L20p_3J3

IP_L20n_3_VREF_3J2

IP_L24p_3J1

IP_L24n_3K1

IP_L46p_3U3

IP_L46n_3V4

IP_L50p_3W1

IP_L50n_3_VREF_3W2

IP_L66p_3AE1

IP_L66n_3_VREF_3AE2

IP_L58n_3_VREF_3AA5

IO_L01p_3J8

IO_L01n_3J9

IO_L02p_3B2

IO_L02n_3B1

IO_L03p_3G6

IO_L03n_3H7

IO_L05p_3K9

IO_L05n_3K8

IO_L06p_3D3

IO_L06n_3E4

IO_L07p_3E3

IO_L07n_3F4

IO_L09p_3F5

IO_L09n_3G4

IO_L10p_3J7

IO_L10n_3H6

IO_L11p_3E1

IO_L11n_3F2

IO_L13p_3K7

IO_L13n_3J6

IO_L14p_3G3

IO_L14n_3F3

IO_L15p_3L10

IO_L15n_3L9

IO_L17p_3H2

IO_L17n_3H1

IO_L18p_3K6

IO_L18n_3L7

IO_L19p_3J5

IO_L19n_3J4

IO_L21p_3M10

IO_L21n_3M9

IO_L22p_3K5

IO_L22n_3K4

IO_L23p_3K3

IO_L23n_3K2

IO_L25p_3L4

IO_L25n_3L3

IO_L26p_3M8

IO_L26n_3M7

IO_L27p_3M4

IO_L27n_3M3

IO_L28p_3M5

IO_L28n_3M6

IO_L29p_3M2

IO_L29n_3_VREF_3M1

IO_L30p_3N5

IO_L30n_3N4

IO_L31p_3N1

IO_L31n_3N2

IO_L32p_3_LHCLK0N6

IO_L32n_3_LHCLK1N7

IO_L33p_3_LHCLK2P1

IO_L33n_3_IRDY2_LHCLK3P2

IO_L34p_3_LHCLK4P4

IO_L34n_3_LHCLK5P3

IO_L35p_3_TRDY2_LHCLK6N9

IO_L35n_3_LHCLK7P10

IO_L36p_3_VREF_3R1

IO_L36n_3R2

IO_L37p_3R3

IO_L37n_3R4

IO_L38p_3T3

IO_L38n_3T4

IO_L39p_3P7

IO_L39n_3P6

IO_L40p_3R5

IO_L40n_3R6

IO_L41p_3P8

IO_L41n_3P9

IO_L42p_3T5

IO_L42n_3U4

IO_L43p_3_VREF_3R10

IO_L43n_3R9

IO_L44p_3U1

IO_L44n_3U2

IO_L45p_3R8

IO_L45n_3R7

IO_L47p_3V1

IO_L47n_3V2

IO_L48p_3T10

IO_L48n_3T9

IO_L49p_3U5

IO_L49n_3V5

IO_L51p_3T7

IO_L51n_3U6

IO_L52p_3W3

IO_L52n_3W4

IO_L53p_2Y1

IO_L53n_3Y2

IO_L55p_3AA2

IO_L55n_3AA3

IO_L56p_3U7

IO_L56n_3U8

IO_L57p_3Y5

IO_L57n_3Y6

IO_L59p_3V7

IO_L59n_3V6

IO_L60p_3AB1

IO_L60n_3AC1

IO_L61p_3U9

IO_L61n_3V8

IO_L63p_3W7

IO_L63n_3W6

IO_L64p_3AC2

IO_L64n_3AC3

IO_L65p_3AD1

IO_L65n_3AD2

IP_L54p_3Y3

IP_L12n_3_VREF_3H4

IP_L16n_3G1

IP_L04n_3_VREF_3C1

IP_L04p_3C2

IP_L16p_3G2

IP_L12p_3G5

IP_L08p_3D2

IP_L62p_3AB3

IP_L58p_3AA4

IP_L08n_3D1

IP_L62n_3AB4

IP_L54n_3Y4

RP16

24R0

RP16

24R0

18273645

C202

0.1uF

C202

0.1uF

C112

0.01uF

C112

0.01uF

C117

0.01uF

C117

0.01uF

RP6

33R0

RP6

33R0

18273645

R141 22R0R141 22R0

U18

SN74AVC20T245ZQL

U18

SN74AVC20T245ZQL

1B1A1

1B2A2

1DIRA3

1OEA4

1A2A5

1A1A6

1B3B1

1B4B2

GNDB3

GNDB4

1A4B5

1A3B6

1B5C1

1B6C2

VCCBC3

VCCAC4

1A6C5

1A5C6

1B7D1

1B8D2

GNDD3

GNDD4

1A8D5

1A7D6

1B9E1

1B10E2

1A10E5

1A9E6

2B1F1

2B2F2

2A2F5

2A1F6

2B3G1

2B4G2

GNDG3

GNDG4

2A4G5

2A3G6

2B5H1

2B6H2

VCCBH3

VCCAH4

2A6H5

2A5H6

2B7J1

2B8J2

GNDJ3

GNDJ4

2A8J5

2A7J6

2B9K1

2B10K2

2DIRK3

2OEK4

2A10K5

2A9K6

C200

0.1uF

C200

0.1uF

R138 22R0R138 22R0

C135

1.0uF

C135

1.0uF

RP12

33R0

RP12

33R0

18273645

C131

1.0uF

C131

1.0uF

R151

1K

R151

1K

C138

1.0uF

C138

1.0uF

C26

0.1uF

C26

0.1uF

R139 10KR139 10K

RP33

24R0

RP33

24R0

18273645

C129

0.01uF

C129

0.01uF

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

JTAG_TCKJTAG_TMS

JTAG_TCKJTAG_TMSJTAG_TDOJTAG_TDI

FPGA_TDOFPGA_TDI

Vcco_0

+2.5V Vcco_0 +3.3V

VCC_INT

+2.5V

+3.3V

+2.5V Vcco_2 +3.3V

Vcco_2

+2.5V

+2.5V

+3.3V

+2.5V

VCC_INT

Vcco_0

+1.8V

Vcco_2

+2.5V

+3.3V

+1.8V

FPGA_DONE10

FPGA_PROG# 10

JTAG_TCK10JTAG_TMS10FPGA_TDO10FPGA_TDI10

SUSPEND4

Title


Date: Sheet of


0381257 1


C


Sheet 7 - FPGA PowerTitle


Date: Sheet of


0381257 1


C


Sheet 7 - FPGA PowerTitle


Date: Sheet of


0381257 1


C


Sheet 7 - FPGA Power

EXP1 VOLTAGE SELECT EXP2 VOLTAGE SELECT

JP11 default

setting 1:2

Cap Size TANDCap Size 0201 Cap Size 0402 Cap Size 0603

Cap Size 0603 Cap Size TANDCap Size 0201 Cap Size 0402

Default: JP2 1:2 (VCCO_0 = +3.3V)

Default: JP3 1:2 (VCCO_2 = +3.3V)

Default: JP7

Unpopulated

R113 4.02KR113 4.02K

C65

1.0uF

C65

1.0uF

C87

1.0uF

C87

1.0uF

C24

4.7uF

C24

4.7uF

12

C81

0.01uF

C81

0.01uF

C58

0.01uF

C58

0.01uF

+

C23

470uF

+

C23

470uF

12

C130

0.01uF

C130

0.01uF

C13

4.7uF

C13

4.7uF

12

+

C10

470uF

+

C10

470uF

12

C98

1.0uF

C98

1.0uF

C105

0.01uF

C105

0.01uF

C139

1.0uF

C139

1.0uF

C83

0.01uF

C83

0.01uF

D1

LED_BLU

D1

LED_BLU

C114

0.01uF

C114

0.01uF

C60

0.01uF

C60

0.01uF

C93

1.0uF

C93

1.0uF

R78 4.75KR78 4.75K

C97

0.01uF

C97

0.01uF

C64

1.0uF

C64

1.0uF

C104

0.01uF

C104

0.01uF

JP7JP7

12

C134

1.0uF

C134

1.0uF

C132

0.01uF

C132

0.01uF

C15

4.7uF

C15

4.7uF

12

C8

4.7uF

C8

4.7uF

12

R534.75KR534.75K

C80

0.01uF

C80

0.01uF

C88

0.01uF

C88

0.01uF

C14

4.7uF

C14

4.7uF

12

+

C7

470uF

+

C7

470uF

12

C125

1.0uF

C125

1.0uF

C103

0.01uF

C103

0.01uF

C118

0.01uF

C118

0.01uF

C6

4.7uF

C6

4.7uF

12

C86

0.01uF

C86

0.01uF

C107

0.01uF

C107

0.01uF

C75

1.0uF

C75

1.0uF

C71

0.01uF

C71

0.01uF

C12

4.7uF

C12

4.7uF

12

C128

1.0uF

C128

1.0uF

SW2

SPST

SW2

SPST

314

2

C69

1.0uF

C69

1.0uF

C82

0.01uF

C82

0.01uF

C109

0.01uF

C109

0.01uF

C119

0.01uF

C119

0.01uF

C94

0.01uF

C94

0.01uF

C16

4.7uF

C16

4.7uF

12

C120

0.01uF

C120

0.01uF

C59

1.0uF

C59

1.0uF

C43

0.1uF

C43

0.1uF

C84

0.01uF

C84

0.01uF

C79

0.01uF

C79

0.01uF

C123

1.0uF

C123

1.0uF

C78

0.01uF

C78

0.01uF+

C17

470uF

+

C17

470uF

12

C4

4.7uF

C4

4.7uF

12

C57

1.0uF

C57

1.0uF

+

C22

470uF

+

C22

470uF

12

U6E

XC3SD1800AFG676_1

U6E

XC3SD1800AFG676_1

PR0G_BA2

DONEAB21

SUSPENDV20

TCKA25

TMSD4

TDOE23

TDIG7

VC

CIN

TK

15

VC

CIN

TL16

VC

CIN

TL14

VC

CIN

TL12

VC

CIN

TM

17

VC

CIN

TM

15

VC

CIN

TM

13

VC

CIN

TM

11

VC

CIN

TN

16

VC

CIN

TN

14

VC

CIN

TN

13

VC

CIN

TN

12

VC

CIN

TP

15

VC

CIN

TP

14

VC

CIN

TP

13

VC

CIN

TP

11

VC

CIN

TR

16

VC

CIN

TR

14

VC

CIN

TR

12

VC

CIN

TT

15

VC

CIN

TT

13

VC

CIN

TT

11

VC

CIN

TU

12

VC

CA

UX

E5

VC

CA

UX

J18

VC

CA

UX

K13

VC

CA

UX

L5

VC

CA

UX

N10

VC

CA

UX

P17

VC

CA

UX

T22

VC

CA

UX

U14

VC

CA

UX

V9

VC

CA

UX

AB

22

VC

CA

UX

AB

11

VC

CA

UX

AB

5V

CC

AU

XE

22

VC

CA

UX

E16

VCCO_0B22

VCCO_0B16

VCCO_0B11

VCCO_0B5

VCCO_0E19

VCCO_0E13

VCCO_0E8

VCCO_0H16

VCCO_0H11

VCCO_1AB25

VCCO_1E25

VCCO_1H22

VCCO_1L25

VCCO_1L19

VCCO_1N22

VCCO_1T25

VCCO_1T19

VCCO_1W22

VCCO_2AB19

VCCO_2AB14

VCCO_2AB8

VCCO_2AE22

VCCO_2AE16

VCCO_2AE11

VCCO_2AE5

VCCO_2W16

VCCO_2W11

VCCO_3AB2

VCCO_3E2

VCCO_3H5

VCCO_3L8

VCCO_3L2

VCCO_3P5

VCCO_3T8

VCCO_3T2

VCCO_3W5

GN

DA

26

GN

DA

21

GN

DA

16

GN

DA

11

GN

DA

6G

ND

A1

GN

DA

A26

GN

DA

A21

GN

DA

A16

GN

DA

A11

GN

DA

A6

GN

DA

A1

GN

DA

D24

GN

DA

D18

GN

DA

D13

GN

DA

D8

GN

DA

D3

GN

DA

F26

GN

DA

F21

GN

DA

F16

GN

DA

F11

GN

DA

F6

GN

DA

F1

GN

DC

24

GN

DC

19

GN

DC

14

GN

DC

9G

ND

C3

GN

DF

26

GN

DF

21

GN

DF

16

GN

DF

11

GN

DF

6G

ND

F1

GN

DH

19

GN

DH

14

GN

DH

8G

ND

H3

GN

DJ24

GN

DK

17

GN

DK

10

GN

DL26

GN

DL21

GN

DL15

GN

DL13

GNDL11

GNDL6

GNDL1

GNDM16

GNDM14

GNDM12

GNDN15

GNDN11

GNDN8

GNDP24

GNDP19

GNDP16

GNDP12

GNDR15

GNDR13

GNDR11

GNDT26

GNDT21

GNDT16

GNDT14

GNDT12

GNDT6

GNDT1

GNDU17

GNDU13

GNDU10

GNDV3

GNDW24

GNDW19

GNDW14

GNDW8

C108

0.01uF

C108

0.01uF

C110

0.01uF

C110

0.01uF

C99

1.0uF

C99

1.0uF

C66

0.01uF

C66

0.01uF

C9

4.7uF

C9

4.7uF1

2

+

C3

470uF

+

C3

470uF

12

C62

1.0uF

C62

1.0uF

C92

1.0uF

C92

1.0uF

C63

0.01uF

C63

0.01uF

C102

0.01uF

C102

0.01uF

C2

4.7uF

C2

4.7uF

12

C101

0.01uF

C101

0.01uF

C91

1.0uF

C91

1.0uF

C116

0.01uF

C116

0.01uF

R112 10KR112 10K

JP2JP2

123

C106

1.0uF

C106

1.0uF

C122

0.01uF

C122

0.01uF

C11

4.7uF

C11

4.7uF

12

C115

0.01uF

C115

0.01uF

C5

4.7uF

C5

4.7uF

12

C61

0.01uF

C61

0.01uF

C70

1.0uF

C70

1.0uF

C95

1.0uF

C95

1.0uF

JP11JP11

13

2

C72

0.01uF

C72

0.01uF

C77

0.01uF

C77

0.01uF

R83681R83681

C124

1.0uF

C124

1.0uF

JP3JP3

123

C121

0.01uF

C121

0.01uF

C96

1.0uF

C96

1.0uF

C31

4.7uF

C31

4.7uF

12

C67

0.01uF

C67

0.01uF

Q22N7002

Q22N7002

3

1

2

C73

0.01uF

C73

0.01uF

C68

0.01uF

C68

0.01uF

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

FPGA_DDR_A0FPGA_DDR_A1FPGA_DDR_A2FPGA_DDR_A3FPGA_DDR_A4FPGA_DDR_A5FPGA_DDR_A6FPGA_DDR_A7FPGA_DDR_A8FPGA_DDR_A9FPGA_DDR_A10FPGA_DDR_A11FPGA_DDR_A12

FPGA_MEM_D16FPGA_MEM_D17FPGA_MEM_D18FPGA_MEM_D19FPGA_MEM_D20FPGA_MEM_D21FPGA_MEM_D22FPGA_MEM_D23FPGA_MEM_D24FPGA_MEM_D25FPGA_MEM_D26FPGA_MEM_D27FPGA_MEM_D28FPGA_MEM_D29FPGA_MEM_D30FPGA_MEM_D31

FPGA_MEM_D0FPGA_MEM_D1FPGA_MEM_D2FPGA_MEM_D3FPGA_MEM_D4FPGA_MEM_D5FPGA_MEM_D6FPGA_MEM_D7FPGA_MEM_D8FPGA_MEM_D9FPGA_MEM_D10FPGA_MEM_D11FPGA_MEM_D12FPGA_MEM_D13FPGA_MEM_D14FPGA_MEM_D15

FPGA_DDR_A0FPGA_DDR_A1FPGA_DDR_A2FPGA_DDR_A3FPGA_DDR_A4FPGA_DDR_A5FPGA_DDR_A6FPGA_DDR_A7FPGA_DDR_A8FPGA_DDR_A9

FPGA_DDR_A10FPGA_DDR_A11FPGA_DDR_A12

FPGA_MEM_D0

FPGA_MEM_D1

FPGA_MEM_D15

FPGA_MEM_D2 FPGA_MEM_D3

FPGA_MEM_D4

FPGA_MEM_D5FPGA_MEM_D6

FPGA_MEM_D7

FPGA_MEM_D9


FPGA_MEM_D12

FPGA_MEM_D13

FPGA_MEM_D14

FPGA_MEM_D8

FPGA_DDR_D0

FPGA_DDR_D1

FPGA_DDR_D2 FPGA_DDR_D3

FPGA_DDR_D4


FPGA_DDR_D7

FPGA_DDR_D9


FPGA_DDR_D12

FPGA_DDR_D13

FPGA_DDR_D14

FPGA_DDR_D8

FPGA_DDR_D15

FPGA_DDR_D24

FPGA_DDR_D31


FPGA_DDR_D18

FPGA_DDR_D19





FPGA_DDR_D30FPGA_MEM_D24

FPGA_MEM_D31


FPGA_MEM_D18

FPGA_MEM_D19

FPGA_MEM_D22FPGA_MEM_D23FPGA_MEM_D25


FPGA_MEM_D28

FPGA_MEM_D30


FPGA_MEM_D29

FPGA_DDR_D[0:31]6,9

+1.8V+1.8V

+1.8V +1.8V

FPGA_DDR2_VREF

FPGA_DDR2_VREF

FPGA_DDR2_VREF

FPGA_DDR2_VREF

+1.8V

FPGA_DDR_A[0:12] 6,9

FPGA_DDR_RAS#6,9

FPGA_DDR_BS06,9FPGA_DDR_BS16,9

FPGA_DDR_CAS#6,9

FPGA_DDR_WE#6,9FPGA_DDR_CS#6,9

FPGA_DDR_CKE6

FPGA_DDR_RAS# 6,9

FPGA_DDR_BS0 6,9FPGA_DDR_BS1 6,9

FPGA_DDR_CAS# 6,9

FPGA_DDR_WE# 6,9FPGA_DDR_CS# 6,9

FPGA_DDR_CKE 6

DDR2_ODT_Control6

FPGA_DDR_UDQS#_16,9

FPGA_DDR_UDM_16,9

FPGA_DDR_UDQS_16,9

FPGA_DDR_LDM_16,9

FPGA_DDR_LDQS#_16,9FPGA_DDR_LDQS_16,9

FPGA_DDR_UDQS#_06,9

FPGA_DDR_UDM_06,9

FPGA_DDR_UDQS_06,9

FPGA_DDR_LDM_06,9

FPGA_DDR_LDQS#_06,9FPGA_DDR_LDQS_06,9

FPGA_DDR_CLK_06

FPGA_DDR_CLK_0#6

FPGA_DDR_CLK_1 6

FPGA_DDR_CLK_1# 6

FPGA_DDR_A[0:12]6,9

Title


Date: Sheet of


0381257 1


C


Sheet 8 - DDR2 MemoryTitle


Date: Sheet of


0381257 1


C


Sheet 8 - DDR2 MemoryTitle


Date: Sheet of


0381257 1


C


Sheet 8 - DDR2 Memory

Place series terminations close to FPGA

C178

0.01uF

C178

0.01uF

C169

0.1uF

C169

0.1uF

RP29 24R0RP29 24R0

18273645

C154

0.1uF

C154

0.1uFC149

0.1uF

C149

0.1uF

C168

4.7uF

C168

4.7uF

C191

0.1uF

C191

0.1uF

RP30 24R0RP30 24R0

1 82 73 64 5

C160

0.1uF

C160

0.1uF

C184

0.1uF

C184

0.1uF

C179

0.01uF

C179

0.01uF

C176

0.01uF

C176

0.01uF

C163

0.1uF

C163

0.1uF

C189

0.1uF

C189

0.1uFC186

0.1uF

C186

0.1uF

RP26 24R0RP26 24R0

1 82 73 64 5

C158

0.01uF

C158

0.01uFC166

0.1uF

C166

0.1uF

C153

0.1uF

C153

0.1uF

C171

0.1uF

C171

0.1uF

R143 100R143 100

RP32 24R0RP32 24R0

18273645

C150

0.1uF

C150

0.1uF

C155

0.01uF

C155

0.01uF

C152

0.1uF

C152

0.1uFC187

0.1uF

C187

0.1uF

U12

MT47H32M16BN

U12

MT47H32M16BN

n/cE2

n/cA2

VD

DA

1

VS

SA

3

VS

SQ

A7

UDQS#/NUA8

VD

DQ

A9

DQ14B1

VS

SQ

B2

UDMB3

UDQSB7

VS

SQ

B8

DQ15B9

VD

DQ

C1

DQ9C2

VD

DQ

C3

VD

DQ

C7

DQ8C8

VD

DQ

C9

DQ12D1

VS

SQ

D2

DQ11D3

DQ10D7

VS

SQ

D8

DQ13D9

VD

DE

1

VS

SE

3

VS

SQ

E7

LDQS#/NUE8

VD

DQ

E9

DQ6F1

VS

SQ

F2

LDMF3

LDQSF7

VS

SQ

F8

DQ7F9

VD

DQ

G1

DQ1G2

VD

DQ

G3

VD

DQ

G7

DQ0G8

CAS#L7

BA1L3

BA0L2

RF

UL1

OD

TK

9

CK#K8

RAS#K7

WE#K3

CKEK2

VD

DM

9

CKJ8

VS

SD

LJ7

VS

SJ3

VR

EF

J2

VD

DL

J1

DQ5H9

VS

SQ

H8

DQ2H7

DQ3H3

VS

SQ

H2

DQ4H1

VD

DQ

G9

A10M2

A1M3

A2M7

A0M8

VD

DJ9

VS

SN

1

A3N2

A5N3

A6N7

A4N8

A7P2

A9P3

A11P7

A8P8

VS

SP

9V

DD

R1

A12R2

RF

UR

3R

FU

R7

CS#L8

RF

UR

8

C175

0.01uF

C175

0.01uF

C162

0.1uF

C162

0.1uF

RP35 24R0RP35 24R0

1 82 73 64 5

C165

0.1uF

C165

0.1uF

U13

MT47H32M16BN

U13

MT47H32M16BN

n/cE2

n/cA2

VD

DA

1V

SS

A3

VS

SQ

A7

UDQS#/NUA8

VD

DQ

A9

DQ14B1

VS

SQ

B2

UDMB3

UDQSB7

VS

SQ

B8

DQ15B9

VD

DQ

C1

DQ9C2

VD

DQ

C3

VD

DQ

C7

DQ8C8

VD

DQ

C9

DQ12D1

VS

SQ

D2

DQ11D3

DQ10D7

VS

SQ

D8

DQ13D9

VD

DE

1V

SS

E3

VS

SQ

E7

LDQS#/NUE8

VD

DQ

E9

DQ6F1

VS

SQ

F2

LDMF3

LDQSF7

VS

SQ

F8

DQ7F9

VD

DQ

G1

DQ1G2

VD

DQ

G3

VD

DQ

G7

DQ0G8

CAS#L7

BA1L3

BA0L2

RF

UL1

OD

TK

9

CK#K8

RAS#K7

WE#K3

CKEK2

VD

DM

9

CKJ8

VS

SD

LJ7

VS

SJ3

VR

EF

J2

VD

DL

J1

DQ5H9

VS

SQ

H8

DQ2H7

DQ3H3

VS

SQ

H2

DQ4H1

VD

DQ

G9

A10M2

A1M3

A2M7

A0M8

VD

DJ9

VS

SN

1

A3N2

A5N3

A6N7

A4N8

A7P2

A9P3

A11P7

A8P8

VS

SP

9

VD

DR

1

A12R2

RF

UR

3

RF

UR

7

CS#L8

RF

UR

8

C177

0.01uF

C177

0.01uF

C156

0.01uF

C156

0.01uF

C164

4.7uF

C164

4.7uF

R144 100R144 100

C190

0.1uF

C190

0.1uF

C157

0.01uF

C157

0.01uF

RP31 24R0RP31 24R0

18273645

C148

0.1uF

C148

0.1uF

C185

0.1uF

C185

0.1uF

C170

0.1uF

C170

0.1uF

C161

0.1uF

C161

0.1uF

RP27 24R0RP27 24R0

18273645

C151

0.1uF

C151

0.1uF

R142 DNPR142 DNP

C188

0.1uF

C188

0.1uFC147

0.1uF

C147

0.1uF

RP28 24R0RP28 24R0

1 82 73 64 5

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

FPGA_DDR_A7

FPGA_DDR_A12

FPGA_DDR_A8

FPGA_DDR_A5

FPGA_DDR_A9

FPGA_DDR_A6

FPGA_DDR_A4

FPGA_DDR_A0

FPGA_DDR_A2

FPGA_DDR_A11

FPGA_DDR_A1

FPGA_DDR_A3

FPGA_DDR_A10

FP

GA

_D

DR

_D

31

FP

GA

_D

DR

_D

28

FP

GA

_D

DR

_D

26

FP

GA

_D

DR

_D

29

FP

GA

_D

DR

_D

27

FP

GA

_D

DR

_D

25

FP

GA

_D

DR

_D

30

FP

GA

_D

DR

_D

19

FP

GA

_D

DR

_D

18

FP

GA

_D

DR

_D

22

FP

GA

_D

DR

_D

17

FP

GA

_D

DR

_D

21

FP

GA

_D

DR

_D

16

FP

GA

_D

DR

_D

24

FP

GA

_D

DR

_D

20

FP

GA

_D

DR

_D

23

FP

GA

_D

DR

_D

15

FP

GA

_D

DR

_D

12

FP

GA

_D

DR

_D

10

FP

GA

_D

DR

_D

13

FP

GA

_D

DR

_D

11

FP

GA

_D

DR

_D

9

FP

GA

_D

DR

_D

14

FP

GA

_D

DR

_D

3

FP

GA

_D

DR

_D

2

FP

GA

_D

DR

_D

6

FP

GA

_D

DR

_D

1

FP

GA

_D

DR

_D

5

FP

GA

_D

DR

_D

0

FP

GA

_D

DR

_D

8

FP

GA

_D

DR

_D

4

FP

GA

_D

DR

_D

7

FPGA_DDR_D[0:31]6,8

FPGA_0.9V_TT

FPGA_0.9V_TT

FPGA_0.9V_TT

FPGA_0.9V_TTFPGA_0.9V_TT

FPGA_DDR_A[0:12]6,8

FPGA_DDR_BS06,8FPGA_DDR_BS16,8

FPGA_DDR_RAS#6,8FPGA_DDR_CAS#6,8

FPGA_DDR_WE#6,8FPGA_DDR_CS#6,8

FPGA_DDR_LDM_06,8

FPGA_DDR_LDQS_16,8FPGA_DDR_LDQS#_16,8

FPGA_DDR_LDQS_06,8FPGA_DDR_LDQS#_06,8

FPGA_DDR_UDM_16,8FPGA_DDR_LDM_16,8

FPGA_DDR_UDQS_16,8FPGA_DDR_UDQS#_16,8

FPGA_DDR_UDQS_06,8FPGA_DDR_UDQS#_06,8

FPGA_DDR_UDM_06,8

Title


Date: Sheet of


0381257 1


C


Sheet 9 - DDR2 TerminationTitle


Date: Sheet of


0381257 1


C


Sheet 9 - DDR2 TerminationTitle


Date: Sheet of


0381257 1


C


Sheet 9 - DDR2 Termination

Layout Note:

Install

terminators as

close as possible

to the FPGA (U6)

DNP

DNP

C136

0.01uF

C136

0.01uF

RP560RP560

18

27

36

45

C196

0.01uF

C196

0.01uF

RP3760RP3760

18

27

36

45

RP1760

RP1760

18

27

36

45

RP1460RP1460

18

27

36

45

RP860RP860

18

27

36

45

RP760RP760

18

27

36

45

RP3660RP3660

18

27

36

45

C142

0.1uF

C142

0.1uF

RP1060RP1060

18

27

36

45

RP3860RP3860

18

27

36

45

RP960RP960

18

27

36

45

RP2060RP2060

18

27

36

45

RP1860RP1860

18

27

36

45

C167

0.01uF

C167

0.01uF

RP1960

RP1960

18

27

36

45

C144

0.01uF

C144

0.01uF

RP2260RP2260

18

27

36

45

RP2160RP2160

18

27

36

45

C140

0.01uF

C140

0.01uF

RP3460RP3460

18

27

36

45

C193

0.01uF

C193

0.01uF

C141

0.01uF

C141

0.01uF

C143

0.1uF

C143

0.1uF

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

FLASH_A0

FLASH_A8FLASH_A9FLASH_A10FLASH_A11FLASH_A12FLASH_A13FLASH_A14FLASH_A15

FLASH_A1

FLASH_A16FLASH_A17FLASH_A18FLASH_A19FLASH_A20FLASH_A21FLASH_A22FLASH_A23

FLASH_A2FLASH_A3FLASH_A4FLASH_A5FLASH_A6FLASH_A7

JTAG_TMSJTAG_TCKJTAG_TDI

FLASH_D0FLASH_D1FLASH_D2

FLASH_D4FLASH_D5FLASH_D6FLASH_D7

FLASH_D3

JTAG_TCKJTAG_TMSJTAG_TDOJTAG_TDI

JTAG_TCK

JTAG_TDO

JTAG_TMS

JTAG_TDI

JTAG_TMSJTAG_TDO

JTAG_TDIJTAG_TCK

JTAG_TCKJTAG_TMS

JTAG_TDIJTAG_TDO

+3.3V

+3.3V

+3.3V Vcco_2

+3.3V

+3.3V

+3.3V +3.3V

+2.5V

+3.3V +3.3V +2.5V+2.5V

+2.5V

+2.5V

+2.5V

+3.3V

FLASH_D[0:7]5

FLASH_CE#4

FLASH_OE#4FLASH_WE#4

FLASH_A[0:23]4

Flash_Reset#4

FLASH_CE# 4

FLASH_WE# 4

SPI_CLK5

SPI_SEL#5

SPI_MOSI5

SPI_MISO5

JTAG_TCK7JTAG_TMS7FPGA_TDO7FPGA_TDI7

FLASH_D05

FPGA_PROG# 7

FPGA_CCLK 5

FPGA_INIT#5

FPGA_DONE 7

SAM_D10 4

SAM_A6 4

SAM_RESETn 4SAM_IRQ 4

SAM_D2 4SAM_D4 4SAM_D6 4SAM_D8 4

SAM_D12 4SAM_D14 4

SAM_A2 4SAM_A0 4SAM_OEn 4

SAM_A4 4SAM_D154

SAM_BRDY4

SAM_A34SAM_A14

SAM_WEn4

SAM_A54

SAM_D0 4SAM_D14

SAM_CEn4

SAM_D34SAM_D54SAM_D74SAM_D94

SAM_D114SAM_D134

SAM_CLK5

Title


Date: Sheet of


0381257 1


C

10Friday, July 11, 2008 17

Sheet 10 - Configuration/Flash MemoryTitle


Date: Sheet of


0381257 1


C

10Friday, July 11, 2008 17

Sheet 10 - Configuration/Flash MemoryTitle


Date: Sheet of


0381257 1


C

10Friday, July 11, 2008 17

Sheet 10 - Configuration/Flash Memory

JTAG Parallel IV Connector

Layout Note: Place J4 and J2 close together

Default: JP1 1:2

Default: JP8 No Jumper

C49

0.1uF

C49

0.1uF

R5824R3 R5824R3

12

R128 49R9R128 49R9

C197

0.1uF

C197

0.1uF

C50

0.1uF

C50

0.1uF

R1221KR1221K

12 R43

10KR4310K

R12410KR12410K

12

J2

87332-1420

J2

87332-1420

NC14

GND13

NC12

GND11

TDI10

GND9

TDO8

GND7

TCK6

GND5

TMS4

GND3

VREF2

GND1

U1

28F128J3 TSSOP-56

U1

28F128J3 TSSOP-56

CE0#14

CE1#/RFU2

CE2#/RFU29

A128

A227

A326

A425

A524

A623

A722

A820

A919

A1018

A1117

A1213

A1312

A1411

A1510

A168

A177

A186

A195

A204

A213

A221

A2330

A032

DQ033

DQ135

DQ238

DQ340

DQ444

DQ546

DQ649

DQ751

DQ834

DQ936

DQ1039

DQ1141

DQ1245

DQ1347

DQ1450

DQ1552

VCC9

VCC37

VSS48

VSS42

VSS21

VCCQ43

VPEN15

WE#55

RP#16

OE#54

BYTE#/RFU31

STS53

RFU56

R349R9 R349R9

C53

10uF

C53

10uF

C48

0.1uF

C48

0.1uF

R249R9 R249R9

U16

QH25F640S33

U16

QH25F640S33

Hold#1

VCC2

n/c3

n/c4

n/c5

n/c6

S#7

Q8

W#9

VSS10

n/c11

n/c12

n/c13

n/c14

D15

C16

C52

0.1uF

C52

0.1uF

U3

SN74AVC8T245PW

U3

SN74AVC8T245PW

VCCA1

DIR2

A13

A24

A35

A46

A57

A68

A79

A810

GND11

GND12

GND13

B814

B715

B616

B517

B418

B319

B220

B121

OE22

VCCB23

VCCB24

C51

0.1uF

C51

0.1uF

R126 49R9R126 49R9

C54

0.1uF

C54

0.1uF

J8

SAM Header

CUT PIN 50

J8

SAM Header

CUT PIN 50

3.3V1

3.3V2

TDO3

GND4

TMS5

CLOCK6

TDI7

GND8

PROGRAMn9

TCK10

GND11

GND12

OEn13

INITn14

A0015

WEn16

A0217

A0118

2.5V19

A0320

D0021

2.5V22

D0223

D0124

D0425

D0326

D0627

D0528

D0829

D0730

D1031

D0932

D1233

D1134

D1435

D1336

A0437

D1538

A0639

A0540

IRQ41

GND42

RESETn43

CEn44

DONE45

BRDY46

CCLK47

BITSTREAM48

GND49

GND50

JP1JP1

123

R449R9 R449R9

R549R9 R549R9

R125 49R9R125 49R9

R127 49R9R127 49R9J4J4

123456

JP8JP8

12

RP1

4.7K

RP1

4.7K

1 82 73 64 5

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

LNK10LNK100LNK1000

+2.5V

+2.5V +2.5V +2.5V +2.5V

+2.5V

+2.5V

+2.5V

+2.5V

+2.5V

+2.5V

+2.5V

+2.5V

+2.5V

+2.5V

+2.5V

+2.5V

GBE_MCLK6

GMII_COL6

GMII_TXD26

GMII_RXD56

GMII_TXD06

GMII_RXD16

GMII_TXD56

GBE_RST#6

GMII_TXD36

GMII_MDIO6

GMII_TX_EN6

GMII_RX_DV6

GMII_RXD36

GMII_TXD66

GMII_RXD66

GMII_RXD26

GMII_RXD06

GMII_RXD46

GMII_TXD16

GBEINT#6

GMII_MDC6

GMII_TXD46

GMII_RXD76

GMII_CRS6

GMII_RX_ER6

GMII_TXD76

GMII_GTX_CLK6

GMII_TX_ER6

GMII_RX_CLK6

GMII_TX_CLK6

Title


Date: Sheet of


0381257 1


C

11Friday, July 11, 2008 17

Sheet 11 - 10/100/1000 PHYTitle


Date: Sheet of


0381257 1


C

11Friday, July 11, 2008 17

Sheet 11 - 10/100/1000 PHYTitle


Date: Sheet of


0381257 1


C

11Friday, July 11, 2008 17

Sheet 11 - 10/100/1000 PHY

Default position is 1-2for all JTx jumpers

Place close to PHY

Place close to PHY

Speed1

PHY ADDR0

Speed0

LINK

Place close to PHY

ACT

Auto-Neg

Place close to FPGA

MDIX-EN

MAN-MDIX

MULTI-EN

NON-IEEE

LNK1000

LNK100

LNK10

DUPLEX

MAC CLK-EN

Duplex

DNP

R45 22R45 22

R121 22R121 22

R6749.9 1%R6749.9 1%

12

D3 LED_GRND3 LED_GRN

R92 330R92 330

1 2

JT1

1K

JT1

1K

A3

Com2

B1

JT14

0R

JT14

0R

A3

Com2

B1

R72 22R72 22

R97 1KR97 1K

1 2

JT3

1K

JT3

1K

A3

Com2

B1


R77 22R77 22

R82 22R82 22

JT4

1K

JT4

1K

A3

Com2

B1

C4422pFC4422pF

12

R94 330R94 330

1 2

R50 22R50 22

JT12

0R

JT12

0R

A3

Com2

B1

R60 10MR60 10M

1 2

JT10

0R

JT10

0R

A3

Com2

B1

R117

1K

R117

1K

12

R96 330R96 330

1 2

JT8

0R

JT8

0R

A3

Com2

B1

R47 22R47 22

JT9

0R

JT9

0R

A3

Com2

B1

R7549.9 1%R7549.9 1%

12

U22A DP83865DVHU22A DP83865DVH

TXD0/TX076

TXD1/TX175

TXD2/TX272

TXD3/TX371

TXD468

TXD567

TXD666

TXD765

TX_EN/TXEN_ER62

TX_CLK/RGMII_SEL160

GTX_CLK/TCK79

TX_ER61

RXD0/RX056

RXD1/RX155

RXD2/RX252

RXD3/RX351

RXD450

RXD547

RXD646

RXD745

RX_DV/RCK44

RX_ERRXDV_ER41

RX_CLK57

COL/CLK_MAC_FREQ39

CRS/RGMII_SEL040

MDC81

MDIO80

MDIA_N109

TCK24

TMS27

TDI31

TDO28

TRST32

CLK_IN86

CLK_OUT87

PHY_ADDR495

PHY_ADDR318

PHY_ADDR217

PHY_ADDR114

LED_ACT/SPD07

LED_LNK_10/SPD18

LED_LNK_100/DUPLEX9

MDIX_EN89

INTERRUPT3

LED_LNK_1000/AN_EN10

MAN_MDIX/TX_TCLK6

MULTI_EN/TX_TRIG94

LED_DUP/PHY_ADDR013

NON_IEEE1

RESET33

MDIA_P108

MDIB_N115

MDIB_P114

MDIC_N121

MDIC_P120

MDID_N127

MDID_P126

CLK_TO_MAC85

MAC_CLK_EN/TX_SYN_CLK88

RP25

4.7K

RP25

4.7K

18

27

36

45

R111 22R111 22

J9

1-6605833-1

J9

1-6605833-1

MX2_N7

MX2_P6

MX1_P4

MX1_N5

MX3_P8

D315

MX0_P2

D214

D416

MX3_N9

MX0_N3

D113

CH_GND10

VCC_CT1

SHIELD11

SHIELD12

R98 330R98 330

1 2

U25

74V1G08

U25

74V1G08

1

24

53

JT7

0R

JT7

0R

A3

Com2

B1

R90 22R90 22

Y1

XTAL-25MHz

Y1

XTAL-25MHz

1 3

JT2

1K

JT2

1K

A3

Com2

B1

R114

10R0

R114

10R0

1 2

R8649.9 1%R8649.9 1%

12

R118 DNPR118 DNP

12

JT5

1K

JT5

1K

A3

Com2

B1

R52 22R52 22

C4722pFC4722pF

12


JT15

0R

JT15

0R

A3

Com2

B1

JT11

0R

JT11

0R

A3

Com2

B1

R65 22R65 22

R119

1K

R119

1K

12

R1201KR1201K

12

R76 22R76 22

R51 22R51 22

R62100KR62100K

12

R70 22R70 22

R95 1KR95 1K

1 2

U26

74V1G04

U26

74V1G04

2 4

5

3

R93 1KR93 1K

1 2

R6949.9 1%R6949.9 1%

12

R61 22R61 22

R89 22R89 22

R87 22R87 22

R7149.9 1%R7149.9 1%

12

R8449.9 1%R8449.9 1%

12

R115 22R115 22

R48 22R48 22

R46 22R46 22

R8849.9 1%R8849.9 1%

12

R1161KR1161K

12

R54 22R54 22

R44 22R44 22

R68 22R68 22

R59 1KR59 1K

1 2


R49 22R49 22

R55 22R55 22

R85 22R85 22

JT13

0R

JT13

0R

A3

Com2

B1

R91 1KR91 1K

1 2

JT6

0R

JT6

0R

A3

Com2

B1

R8149.9 1%R8149.9 1%

12

U24

74V1G08

U24

74V1G08

1

24

53

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

+1.8V

+1.8V

+2.5V

+2.5V

+1.8V

+1.8V

Title


Date: Sheet of


0381257 1


B

12Friday, July 11, 2008 17

Sheet 12 - PHY PowerTitle


Date: Sheet of


0381257 1


B

12Friday, July 11, 2008 17

Sheet 12 - PHY PowerTitle


Date: Sheet of


0381257 1


B

12Friday, July 11, 2008 17

Sheet 12 - PHY Power

R57 18R2R57 18R2

1 2

U22B

DP83865DVH

U22B

DP83865DVH

2V5_AVDD2962V5_AVDD1101 CORE_VDD 11

CORE_VDD 19

CORE_VDD 25

CORE_VDD 35

CORE_VDD 48

CORE_VDD 63

CORE_VDD 73

CORE_VDD 92

1V8_AVDD3100

IO_VDD4

IO_VDD15

IO_VDD21

IO_VDD29

IO_VDD37

IO_VDD42

IO_VDD53

IO_VDD58

IO_VDD69

IO_VDD77

IO_VDD83

IO_VDD90

1V8_AVDD1103

1V8_AVDD1105

1V8_AVDD1111

1V8_AVDD1117

1V8_AVDD1123

VDD_SEL34

BG_REF102

VSS 5

VSS 12

VSS 16

VSS 20

VSS 22

VSS 26

VSS 30

VSS 36

VSS 38

VSS 43

VSS 49

VSS 54

VSS 59

VSS 64

VSS 70

VSS 74

VSS 78

VSS 82

VSS 91

VSS 93

VSS 97

VSS 99

VSS 104

VSS 106

VSS 107

VSS 110

VSS 112

VSS 113

VSS 116

VSS 118

VSS 119

VSS 122

VSS 124

VSS 125

VSS 128RSVD84RSVD23RSVD2

1V8_AVDD298

C214

0.01uF

C214

0.01uF

C46

22uF

C46

22uF

12

+

C228

47uF

+

C228

47uF

12

+

C227

47uF

+

C227

47uF

12

C233

0.1uF

C233

0.1uF

C230

0.1uF

C230

0.1uF

C215

0.01uF

C215

0.01uF

C45

22uF

C45

22uF

12

C223

0.1uF

C223

0.1uF

C211

0.1uF

C211

0.1uF

C220

0.1uF

C220

0.1uF

C222

0.01uF

C222

0.01uF

C236

0.01uF

C236

0.01uF

R56 10R0R56 10R0

1 2

C216

0.01uF

C216

0.01uF

C210

0.1uF

C210

0.1uF

C234

0.1uF

C234

0.1uF

C212

0.01uF

C212

0.01uF

C221

0.01uF

C221

0.01uF

C235

0.01uF

C235

0.01uF

C229

0.01uF

C229

0.01uF

C225

0.01uF

C225

0.01uF

C224

0.01uF

C224

0.01uF

C213

0.01uF

C213

0.01uF

C232

0.01uF

C232

0.01uF

C237

0.01uF

C237

0.01uF

C238

0.01uF

C238

0.01uF

C231

0.1uF

C231

0.1uF

R64 9.76K 1%R64 9.76K 1%

1 2

+

C226

47uF

+

C226

47uF

12

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

DAC_G0DAC_G1DAC_G2DAC_G3

DAC_B0DAC_B1DAC_B2DAC_B3

DAC_R0DAC_R1DAC_R2DAC_R3

RED

BLUE

GREEN

DAC_G[0:3]4

DAC_B[0:3]4

DAC_R[0:3]4

DAC_HSYNC4

DAC_VSYNC4

Title


Date: Sheet of


0381257 1


B

13Friday, July 11, 2008 17

Sheet 13 - DAC OutTitle


Date: Sheet of


0381257 1


B

13Friday, July 11, 2008 17

Sheet 13 - DAC OutTitle


Date: Sheet of


0381257 1


B

13Friday, July 11, 2008 17

Sheet 13 - DAC Out

DNP R3175R0R3175R0

R15 2KR15 2K

R19 510R19 510

R26 1KR26 1KR24 2KR24 2K

R27 510R27 510

R23 0R0R23 0R0

R20 4.02KR20 4.02K

R28 0R0R28 0R0R16 4.02KR16 4.02K

R3275R0R3275R0

R17 10R0R17 10R0

1 2

R13 510R13 510

R25 4.02KR25 4.02K

R3075R0R3075R0

R18 1KR18 1K

P1

CO

NN

EC

TO

R D

B1

5

P1

CO

NN

EC

TO

R D

B1

5

8157

146

135

124

113

10291

16

17

18

19

R14 1KR14 1K

R21 2KR21 2K

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A





























EXP1_SE_IO_28

EXP1_SE_IO_29











+3.3V +3.3V

+2.5V+2.5V

+2.5V

+3.3V

EXP1_SE_CLK_IN 3

EXP1_SE_IO_[0:33]3

EXP1_DIFF_p[0:21]3

EXP1_DIFF_n[0:21]3

EXP1_SE_CLK_OUT 3

EXP1_DIFF_CLK_OUT_p3EXP1_DIFF_CLK_OUT_n3

EXP1_DIFF_CLK_IN_p3EXP1_DIFF_CLK_IN_n3

Title


Date: Sheet of


0381257 1


B

14Friday, July 11, 2008 17

Sheet 14 - EXP Connector (JX1)Title


Date: Sheet of


0381257 1


B

14Friday, July 11, 2008 17

Sheet 14 - EXP Connector (JX1)Title


Date: Sheet of


0381257 1


B

14Friday, July 11, 2008 17

Sheet 14 - EXP Connector (JX1)

C192

0.1uF

C192

0.1uF

C180

0.1uF

C180

0.1uF

C76

0.1uF

C76

0.1uF

+ C33

470uF

+ C33

470uF

12

+ C19

470uF

+ C19

470uF

12

C172

0.1uF

C172

0.1uF

JX1

QTE-060

JX1

QTE-060

22

44

66

88

1010

1212

1414

1616

1818

2020

2222

2424

2626

2828

3030

3232

3434

3636

3838

4040

4242

4444

4646

4848

5050

5252

5454

5656

5858

6060

6262

6464

6666

6868

7070

7272

7474

7676

7878

8080

8282

8484

8686

8888

9090

9292

9494

9696

9898

100100

102102

104104

106106

108108

110110

112112

114114

116116

118118

120120

122122

124124

126126

128128

130130

132132

1 1

3 3

5 5

7 7

9 9

11 11

13 13

15 15

17 17

19 19

21 21

23 23

25 25

27 27

29 29

31 31

33 33

35 35

37 37

39 39

41 41

43 43

45 45

47 47

49 49

51 51

53 53

55 55

57 57

59 59

61 61

63 63

65 65

67 67

69 69

71 71

73 73

75 75

77 77

79 79

81 81

83 83

85 85

87 87

89 89

91 91

93 93

95 95

97 97

99 99

101 101

103 103

105 105

107 107

109 109

111 111

113 113

115 115

117 117

119 119

121 121

123 123

125 125

127 127

129 129

131 131

C159

0.1uF

C159

0.1uF

C89

0.1uF

C89

0.1uF

C100

0.1uF

C100

0.1uF

C113

0.1uF

C113

0.1uF

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

EXP2_SE_IO_6














EXP2_SE_IO_28

EXP2_SE_IO_29

























EXP2_SE_IO_4

+2.5V

+3.3V+3.3V

+2.5V

+2.5V

+3.3V

EXP2_SE_CLK_IN 5

EXP2_SE_IO_[0:33]4,5

EXP2_DIFF_p[0:21]5

EXP2_DIFF_n[0:21]5

EXP2_DIFF_CLK_OUT_p5EXP2_DIFF_CLK_OUT_n5

EXP2_SE_CLK_OUT 5

EXP2_DIFF_CLK_IN_n5EXP2_DIFF_CLK_IN_p5

Title


Date: Sheet of


0381257 1


B

15Friday, July 11, 2008 17

Sheet 15 - EXP Connextor (JX2)Title


Date: Sheet of


0381257 1


B

15Friday, July 11, 2008 17

Sheet 15 - EXP Connextor (JX2)Title


Date: Sheet of


0381257 1


B

15Friday, July 11, 2008 17

Sheet 15 - EXP Connextor (JX2)

C195

0.1uF

C195

0.1uF

+ C21

470uF

+ C21

470uF

12

C181

0.1uF

C181

0.1uF

C111

0.1uF

C111

0.1uF

C90

0.1uF

C90

0.1uF

JX2

QTE-060

JX2

QTE-060

22

44

66

88

1010

1212

1414

1616

1818

2020

2222

2424

2626

2828

3030

3232

3434

3636

3838

4040

4242

4444

4646

4848

5050

5252

5454

5656

5858

6060

6262

6464

6666

6868

7070

7272

7474

7676

7878

8080

8282

8484

8686

8888

9090

9292

9494

9696

9898

100100

102102

104104

106106

108108

110110

112112

114114

116116

118118

120120

122122

124124

126126

128128

130130

132132

1 1

3 3

5 5

7 7

9 9

11 11

13 13

15 15

17 17

19 19

21 21

23 23

25 25

27 27

29 29

31 31

33 33

35 35

37 37

39 39

41 41

43 43

45 45

47 47

49 49

51 51

53 53

55 55

57 57

59 59

61 61

63 63

65 65

67 67

69 69

71 71

73 73

75 75

77 77

79 79

81 81

83 83

85 85

87 87

89 89

91 91

93 93

95 95

97 97

99 99

101 101

103 103

105 105

107 107

109 109

111 111

113 113

115 115

117 117

119 119

121 121

123 123

125 125

127 127

129 129

131 131

C194

0.1uF

C194

0.1uF

C174

0.1uF

C174

0.1uF

+ C34

470uF

+ C34

470uF

12

C85

0.1uF

C85

0.1uF

C74

0.1uF

C74

0.1uF

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

PTH_INH#

PWR_ON

PWR_OFF

PTH_INH#

PTH_INH#

PTH_INH#

PGOOD

PTH_Track

PTH_Track

PTH_Track

PTH_Track

PTH_Track

PTH_INH#+3.3V+3.3V

+3.3V

+3.3V

+5V

+5V

+2.5V

+5V

VCC_INT

+5V

+5V

+1.8V

+5V

FPGA_0.9V_TT FPGA_DDR2_VREF

VCC_INT

+2.5V

+3.3V

+5V

+5V

PO_RESET# 5

Title


Date: Sheet of


0381257 1


C

16Friday, July 11, 2008 17

Sheet 16 - Board PowerTitle


Date: Sheet of


0381257 1


C

16Friday, July 11, 2008 17

Sheet 16 - Board PowerTitle


Date: Sheet of


0381257 1


C

16Friday, July 11, 2008 17

Sheet 16 - Board Power

AVX

TPSD476K016R0100

muRata

GRM32ER61C226KE20

POWER (+5V) INPUT

AVX

TPSE107K016R0100

muRata

GRM32ER61C226KE20

muRata

GRM32ER61C226KE20

AVX

TPSD476K016R0100

Power-On Reset

Main Power Switch

JP10 Default

jumper 1:3, 2:4

JP5 Default

jumper 1:3, 2:4

JP4 Default

jumper 1:3, 2:4

JP6 Default

jumper 1:3, 2:4

Vsense = (1 + 18.2K/10K)0.405

Vsense = 1.142V

DNP

SMT-2512

SW4

GLOBAL RESET

SW4

GLOBAL RESET3

14

2

HG4+5VHG4+5V

HG17DGNDHG17DGND

D16

+1.2V

D16

+1.2V

U15

TPS51116PWP

U15

TPS51116PWP

VTTGND3

VTTSNS4

GND5

MODE6

VTTREF7

COMP8

VDDQSNS9

VDDQSET10

S311

S512

PGOOD13

V5IN14

CS15

PGND16

DRVL17

LL18

DRVH19

VBST20

VLDOIN1

VTT2

R4224.3KR4224.3K

HG3DGNDHG3DGND

C3910uFC3910uF

12

U23

TPS3808

U23

TPS3808

RESET1

GND2

MR3

CT4

SENSE5

VDD6

HG15+3.3VHG15+3.3V

HG11DGNDHG11DGND

R152 1KR152 1K

R40 5.11KR40 5.11K

FB1Fair-Rite 2773021447


11

22

HG1DGNDHG1DGND

U8 PTH05050WAZU8 PTH05050WAZ

GN

D1

Vin3

INH4

ADJ5

Vout6

Track2

C2390.1uFC2390.1uF

+C126

100uF

+C126

100uF

12

C217

22uF

C217

22uF

12

R73750KR73750K

HG6DGNDHG6DGND

JP10JP1034

12

C3810uFC3810uF

12

+C209

100uF

+C209

100uF

12

HG5DGNDHG5DGND

C218

47uF

C218

47uF

12

C4110uFC4110uF

12

JP5JP534

12

C3510uFC3510uF

12

HG13+1.8VHG13+1.8V

+C173

100uF

+C173

100uF

12

HG12DGNDHG12DGND

C219 0.1uFC219 0.1uF

1 2

R63698R63698

U20

TPS3828

U20

TPS3828

RESET1

GND2

MR3

WDI4

VDD5

R153 49R9R153 49R9

U11PTH04000WAZU11PTH04000WAZ

GN

D1

Vin3

INH4

ADJ5

Vout6

Track2



11

22

JP4JP434

12

R129 0R0R129 0R0

Q1ASTS2DNF30LQ1ASTS2DNF30L

R6610KR6610K

R158DNPR158DNP

R99 681R99 681

C4010uFC4010uF

12

C36 0.1uFC36 0.1uF

R41 100KR41 100K

C198

22uF

C198

22uF

12

HG8+2.5VHG8+2.5V

Q3MMBT2222LT1Q3MMBT2222LT1

1

23

D6RESETD6RESET

JP6JP634

12

HG7DGNDHG7DGND

R123 1KR123 1K

C199

47uF

C199

47uF

12

R154 681R154 681U19 PTH05050WAZU19 PTH05050WAZ

GN

D1

Vin3

INH4

ADJ5

Vout6

Track2

R10210KR10210K

HG2DGNDHG2DGND

Q1BSTS2DNF30LQ1BSTS2DNF30L

HG9DGNDHG9DGND

SW1

SPDT Slide 6A

SW1

SPDT Slide 6A

1

2

3

C37

4.7uF

C37

4.7uF

12

R74274KR74274K

HG10+1.2VHG10+1.2V



11

22

R155 510R155 510

R382.21KR382.21K

+

C42150uF+

C42150uF

12

C204

0.033uF

C204

0.033uF

L1

2.2uH

L1

2.2uH

+C146

100uF

+C146

100uF

12

R101 10KR101 10K

U21

TPS3307-25

U21

TPS3307-25

Sns11

Sns22

Sns33

GND4

RST5

RST6

MR7

VDD8

HG14DGNDHG14DGND

D17

+2.5V

D17

+2.5V

+

C18470uF

+

C18470uF

12

R100 18.2KR100 18.2K

HG16DGNDHG16DGND

J5

Barrel Socket

J5

Barrel Socket

12

D18

+3.3V

D18

+3.3V

C145

22uF

C145

22uF

12

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

Title


Date: Sheet of


0381257 1


B

17Friday, July 11, 2008 17

Sheet 17 - Revision HistoryTitle


Date: Sheet of


0381257 1


B

17Friday, July 11, 2008 17

Sheet 17 - Revision HistoryTitle


Date: Sheet of


0381257 1


B

17Friday, July 11, 2008 17

Sheet 17 - Revision History

CONNECTED U20.3 TO PTH_INH# NET

REV 1REV A

ADDED POWER LEDS TO VCC_INT, +2.5V AND +3.3V RAILS

ADDED A 2512 PKG LOAD RESISTOR TO +5V RAIL AT PWR JACK

ADDED PARALLEL TERMINATION TO SMA CLOCK INPUT

REMOVED LEVEL SHIFTER U14 & DIRECTLY CONNECTED SPI NETS TO U16

GROUNDED UNUSED I/O PINS ON TRANSCEIVERS U9, U17 & U18

CHANGED NAME OF PIN "V24" ON FPGA SYMBOL FROM "IP" TO "IO"

09/21/07: Updated Bank 2 of FPGA

package by adding pin AA8 (IP_2) and

changing pin AC22 from IP_2 (input

only) to IO_2 (bidirectional)

11/26/07: Changed U1 device type from

28F128J3/P30 EBGA to 28F128J3 TSSOP-56

07/11/08: Corrected typo on pin U23 of FPGA (U6)

Documents

Spartan-3A DSP Starter Board · 7/11/2008 · exp1_se_io_19 exp1_se_io_18 exp1_se_io_17 exp1_se_io_16 exp1_diff_p12 exp1_diff_p13 exp1_diff_p14 exp1_diff_p15 exp1_diff_n1 exp2_se_io_33