Spartan 3 Board

Confidential 1 Sunday, September 07, 2003

FPGA DEVELOPMENT BOARD USERS MANUAL

Initial Draft Model RN-FDB

For assistance please contact REINFOLD [email protected] www.reinfold.net Ph: +91-80-36833572

mailto:[email protected]

http://www.reinfold.net/


1 RN-FDB01 FPGA DEVELOPMENT BOARD 3

1.1 Introduction 3

1.2 Installation 4 1.2.1 Installing Xilinx Webpack 4 1.2.2 Applying Power To RN-FDB Board 4 1.2.3 Connecting a PC To RN-FDB Board 4 1.2.4 Connecting a VGA monitor to RN-FDB Board 4 1.2.5 Connecting a Mouse or Keyboard to RN-FDB Board 4

1.3 Programming 5 1.3.1 Downloading Non-Volatile Bitstreams INTO FPGA using xilinx impact. 5

1.4 Programmers Models 5 1.4.1 RN-FDB board organization and Functional description 5

1.5 Functional Description 6 1.5.1 Programmable Logic: 6 1.5.2 Interfacing Modules 7 1.5.3 Serial Programming 9 1.5.4 VGA Port 9 1.5.5 PS2 Port 10 1.5.6 General Purpose Input and Output 10 1.5.7 Seven-Segment LED[FND] 11 1.5.8 Oscillator 11

1.6 PIN ASSIGNMENT 12

1.7 SCHEMATICS 14 1.7.1 General purpose I/O and FND 14 1.7.2 Interfacing Modules 17 1.7.3 Power Circuitry 19 1.7.4 FPGA AND PROM CONNECTIONS 20

1.8 APPENDIX: 21 1.8.1 External Interfacing Modules 21

Figure 1-1: Arrangement Of Components On Board 6 Figure 1-2 : Stepper motor Bipolar Drive 8 Figure 1-3: 5X4 Keypad 8 Figure 1-4: Serial Port connection Dig 9 Figure 1-5: VGA Port Connection Dig 9 Figure 1-6: PS2 Port Connection Dig 10 Figure 1-7:D Flip Flop and Clock Pulse. 11 Figure 1-8: FND Arrangement Diagram 11 Table 1-1 :Switching Sequence 8 Table 1-2: FPGA Pin Assignment 12 Table 1-3:FPGA pin assignment for input and output leds 13 Table 1-4: Pin connections for external interfacing modules 21


1 RN-FDB01 FPGA Development Board

1.1 Introduction Designers may use the new XC3S50-5PQ208 in-system-programming (ISP) demo board to prototype, debug, and troubleshoot small designs.The Demo Board has all the required Interfacing Modules On board which makes the user easy to use and to debug.The additional Feature of RN-FDB board is it has a provision to use additional interfacing circuit from the outside world. When used with the new Foundation Series or Alliance Series or WebPack software, the board demonstrates the benefits of combining a robust pin-locking architecture with ISP. The RN-FDB01 FPGA Demo-board provides an ideal platform for new engineers requiring experience with basic digital design techniques, as well as those needing exposure to Xilinx CAD tools and FPGA devices. The RN-CB01 FPGA Demo-board features include:

A socketed Xilinx XC3S50-5PQ208 FPGA device containing 5,292 logic cells with 50,000 system gates(logic & RAM).

Non-volatility i.e., designs remain in the FPGA even after power is switched off.This feature is due to the presence of external PROM on board. Configuration data can be read from an external serial PROM (master serial mode), or written into the FPGA in slave serial, slave parallel, or boundary scan mode.

On board JTAG circuitry, that connects directly with PC through parallel port cable. External JTAG cable connection facility. 16 input and output LEDs controlled by DIP switch. Three PushButton switches that generate positive and negative pulsesand also manual clock. Four highly-bright seven segment displays. Provision of on board interfacing modules like DAC,ADC,Stepper,Relay,Keypad, and LCD. Additional Feature of serial programming with Serial port,VGA Port and PS2 Port for Keypad or mouse

related designs. 10MHz on board, low jitter, high precision crystal oscillator. Four 40-pin expansion connector used to connect off board interfacing circuits. Unlimited reprogramming cycles are possible with this approach Program/erase over full commercial voltage and temperature range.

The RN-FDB01 board makes excellent platform for instructional-lab based work. FPGAs are customized by loading configuration data into internal static memory cells. Spartan-III FPGAs are typically used in high-volume applications where the versatility of a fast programmable solution adds benefits.It is fully compatible with all versions of Xilinx CAD tools, including free WebPack tools available at the Xilinx website. The included PGA uses non-volatile configuration memory, so the design remains intact even on power off. The board is shipped with a downloading cable, so designs can be implemented immediately without the need for any additional hardware.


1.2 Installation

1.2.1 Installing Xilinx Webpack

XILINX currently provides the WebPACK tools for programming their CPLDs and Spartan series FPGAs. You can also download the most current version of the WebPACK tools from the XILINX website.

1.2.1.1 Getting Help

Here are some places to get help if you encounter problems:

If you can't get the RN-FDB Board hardware to work, send an e-mail message describing your problem to [email protected] or call on 080-51261526.

If you can't get your XILINX WebPACK software tools installed properly, send an email message describing your problem to [email protected] or check their web site at http://www.xilinx.com/support/support.htm

1.2.2 Applying Power To RN-FDB Board

RN-FDB Board has on board power supply with three regulators delivering 2.5V,3.3V and 5V power supply.To power up the RN-FDB Board you can plug on the adaptor socket to the female jack available on the board. The circuit on the board is powered by a 5 volt precisely regulated output of a bridge rectifier. This gives the user the flexibility to use either AC or DC power supplies in the range of 6V to 9V with current limit of 500mA.

1.2.3 Connecting a PC To RN-FDB Board

The RN-FDB01 board uses a DB-25 parallel port connector to route JTAG programming signals from a host computer to the RN-FDB board. A separate JTAG header is also provided so that a dedicated programming cable (like the Xilinx Parallel III cable) can also be used. The programming circuit simply connects the parallel port pins driven by the Xilinx CAD tools directly to the FPGA programming pins. The RN-FDB Demo-Board is therefore compatible with all Xilinx programming tools. nnecting

1.2.4 Connecting a VGA monitor to RN-FDB Board

You can display images on a VGA monitor by connecting it to the VGA port at the top of your RN-FDB Board (see Figure 1-1 1). You will have to create a VGA display circuit for your RN-FDB Board to actually display an image.

1.2.5 Connecting a Mouse or Keyboard to RN-FDB Board

You can accept inputs from a keyboard or mouse by connecting it to the PS/2 port at the top of your RN-FDB Board (see Figure 1-1). You will have to create a keyboard or mouse interface circuit to actually receive information on keystrokes or mouse movements.

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1.3 Programming

1.3.1 Downloading Non-Volatile Bitstreams into FPGA using xilinx impact.

The RN-FDB Board consists of Two programming Devices PROM and FPGA.You can use the Xilinx iMPACT software to download bitstreams to the RN-FDB Board.The iMPACT programming tool downloads bitstreams through the JTAG interface of the FPGA.Follow the instructions for iMPACT to download bitstreams to the PROM and FPGA. Note that the PROM has to be programmed first to store the Non-Volatile Bitstreams.The presence of PROM makes the device only needs to be reprogrammed once to support iMPACT because it retains its configuration even when power is removed from the board.The program is retained in the PROM and so it retains the configuration in the Flash memory even if the power is removed from the board.

1.4 Programmers Models This section describes the various sections of the RN-FDB Board and shows how the I/O of the FPGA are connected to the rest of the circuitry.. For more information, you can find a table of FPGA pin connections and detailed schematics at the end of this manual.

1.4.1 RN-FDB board organization and Functional description

The RN-FDB01 board has been designed to offer a low cost and minimal system for designers who need a flexible platform to gain exposure to the basics of hardware design and/or to FPGA devices. The RN-FDB board provides sufficient I/Os and onboard interfacing modules that can be implemented without the need for any other external devices.Figure 1-1 shows the Block diagram and the arrangement of Components on the RNFDB Board.


FF

CON

5

40 PIN CONNECTOR

ECO_JP3

S0

5 6

ECO_JP5

S1

6 7

ECO_JP4

PWR CON

S2

7 8

ECO_JP3 S3

8

KEYPAD[5X4]

8

1

RELAY

OUTPUT LEDS

OSC

9

2

PUSHBOTTON

STEPPER

10MHZ

16

3

RESET

CON7

40 PIN CONNECTOR

1

lcd module(16X2)

4

RESET_B

DAC

TEMP_SENSOR

8

MCLK

IC0832

SWITCHES

9

INPUT LEDS

ADC

16

BNC

D0

XC200S-5PQ208

1

IC0804

BNC

D1

FPGA

1

SERIAL PORTJTAG

+

D2

2

VGA PORT

CLOCK

PWR JACK

40 PIN CONNECTOR

D3

3

PS2 PORT

CON

40 PIN CONNECTOR

FNDS

+

D4

PARALLEL PORT

4

DIP SWITCH

Note: Usage of ECO_JP3,ECO_JP4,ECO_JP5,ECO_JP6 headers see APPENDIX

Figure 1-1: Arrangement Of Components On Board

1.5 Functional Description

1.5.1 Programmable Logic:

1.5.1.1 FPGA

The RNFDB Board contains two programmable logic chips:FPGA and PROM FPGA is the main repository of programmable logic on the RN-FDB Board.A 50-Kgate XILINX Spartan-III FPGA in a 208pin PQ package (XC3S50-5PQ208) is the main repository of programmable logic on the RN-FDB Board.

1.5.1.2 PROM

A 2Mbit Flash device provides non-volatile storage for data and FPGA configuration bit streams which is 20 pin package.A Xilinx XCF02S PROM is used to manage the configuration of the FPGA via the parallel port. In-System Programmable PROMs for Configuration of Xilinx FPGAs.Low-Power Advanced CMOS FLASH Process has Endurance of 20,000 Program/Erase Cycles Operation over Full Boundary-Scan (JTAG) Support for

FRMPC


Programming, Prototyping, and Testing JTAG Command .The I/O Pins on PROM are Compatible with Voltage Levels Ranging From 1.5V to 3.3V.Design Support Using the Xilinx Alliance ISE and Foundation ISE Series Software Packages XCF01S/XCF02S/XCF04S - 3.3V supply voltage are used for Serial FPGA configuration interface.

1.5.2 Interfacing Modules

The following are the description of the on board interfacing modules. NOTE: For pin assignment for all the following modules see Table 1-1 and Table 1-2.

1.5.2.1 Digital-To-Analog Convertor(DAC)

Short for Digital-to-Analog Converter, DAC is a device that reconstructs analog voltage waveforms from an incoming sequence of binary digits.The DAC0832LCN used on RN-FDB Board is an advanced CMOS/Si-Cr 8-bit multiplying DAC designed to interface directly with the 8080, 8048 and other popular microprocessors. The circuit uses CMOS current switches and control logic to achieve low power consumption and low output leakage current errors.Special circuitry provides TTL logic input voltage level compatibility.The Output Of the DAC is an analog signal which can be viewed on a CRO.For Details u can find in the data sheet .

1.5.2.2 Analog-To-Digital Converter(ADC)

Analog-to-Digital Convertors are among the most widely used devices for data acquisition.We need ADC to translate the analog signals to digital numbers .The ADC used on RNFDB Board is ADC0804.The ADC0804 IC is an anlog-to-digital convertor in the family of ADC800 series from National Semiconductor.It works with +5V and has the resolution of 8 bits.The ADC shown in Figure 1-1 has two BNC (red is for supply and Black is for Ground).The Analog signals are applied to the two BNCs and the desired output ie the translated signals can be viewed on the desired Display (Eg:FNDs,LCDs etc) For further details and pin Diagram of the IC Refer Datasheet.

1.5.2.3 LM35-Temperature sensor:

Using ADC, temperature can be sensed easily and the values are displayed on FNDs.

1.5.2.4 Stepper Motor Drive

A stepper motor is widely used device that translates electricl pulses into mechanical movement.The stepper motor is connected to the 7-pin connector shown in Figure 1-1: Arrangement Of Components On Board. Below is the drive circuitry for Stepper motor which will be helpful for programming. .


Figure 1-2 : Stepper motor Bipolar Drive

Table 1-1 :Switching Sequence

The rotation direction is as viewed from the front end.

1.5.2.5 Relay

A relay, quite simply, is a small machine consisting of an electromagnet (coil), a switch, and a spring. The spring holds the switch in one position, until a current is passed through the coil. The coil generates a magnetic field which moves the switch. It's that simple. You can use a very small amount of current to activate a relay, and the switch can often handle a lot. Working of relay on RNFDB board is very simple. When the device is Programmed the relay operates with the output visible on the Red led shown near the realy(in Figure 1-1).The led can be controlled via dipswitches.

1.5.2.6 Keypad

Keyboards and Keypads are another form of digital input. A keypad is a convenient way of entering data. The keypad used on our board is 5X4 Matrix with 5 Drive lines as output and 4 Scan lines as inputs.A similar keypad is as shown below.As per the designed circuit the keypad output can be viewed either on LCD or FNDs. :

S0 S1 S2 S4

Figure 1-3: 5X4 Keypad

A1 R

A3 O

B1 B

B3 G

1 0 1 1 0

2 0 1 0 1

3 1 0 0 1

4 1 0 1 0


1.5.2.7 LCD

LCD Another common type of seven segment display is Liquid crystal display.LCD operates by polarizing light so that a nonactivated segment reflects incident light and thus appears invisible against its background. An activated segment does not reflect incident light and thus appears dark.LCDs consume much less power than LEDs but cannot be seen in dark ,while LEDs can.LCDs operate at low-frequency(30Hz-60Hz). The LCD used is of 16X2LCD. In LCD one can put data at any location. For further details see 16X2 LCD Datasheet. For LCD Datasheet Refer “The 8051 Microcontroller and Embedded Systems by Mazidi.

1.5.3 Serial Programming

1.5.3.1 Serial Port

The term "serial port" is usually meant to identify hardware intended to interface with a modem or similar communication devices. The concept behind serial communications is as follows, data is transferred from sender to receiver one bit at a time through a single line or circuit. The serial port takes 8, 16 or 32 parallel bits from your computer bus and converts it as an 8, 16 or 32 bit serial stream. The name serial communications comes from this fact; each bit of information is transferred in series from one locations to another.

9

TOUT

163

FPGA

2164

RIN

MAX32

2

1

SERIAL PORT_DB9

3

5

4

5

3

6

Figure 1-4: Serial Port connection Dig

.

1.5.4 VGA Port

The FPGA can generate a video signal for display on a VGA monitor. The RN-FDB Board can send signals to display graphics on a VGA monitor through this port. The FPGA outputs three bits each of red, green, and blue color information.This provides a palette of 2 x 2x 2 = 8 colors. The outputs sent to the RGB inputs of a VGA monitor. The FPGA also generates the horizontal and vertical sync pulses (HSYNC#, VSYNC#).

Figure 1-5: VGA Port Connection Dig

http://en.wikipedia.org/wiki/Modem


1.5.5 PS2 Port

A PS/2 port provides the FPGA with an interface to either a keyboard or a mouse. The FPGA receives two signals from the each PS/2 interface: a clock signal and a serial data stream that is synchronized with the falling edge of the clock.RN-FDB board has provided two PS/2 Port to make the end user capable of using keyboard and mouse related designs simultaneously or as per users requirement.The Figure 1-6 shows a PS/2 connections to the FPGA.

Figure 1-6: PS2 Port Connection Dig

1.5.6 General Purpose Input and Output

1.5.6.1 Dipswitches and LEDS

Two DIP switches are attached to the FPGA. A two DIP switch passes settings to the RN-FDB Board and controls the input and output LEDs. When closed (ON), each switch pulls the connected pin of the FPGA to ground. The pin is pulled high through a resistor when the switch is open (OFF). Small resistors are placed in series between the FPGA and the switches so prevent damage if the FPGA tries to drive a pin that is being pulled low. A LED allows visible feedback as the RN-FDB Board operates.For the circuit u can see the schematics of general purpose input and output

1.5.6.2 Pushbutton Switch

The FPGA also connects to three pushbuttons. Three pushbuttons send momentary contact information to the FPGA. Each pushbutton applies a low level to its FPGA pin when pressed and a resistor pulls the pin to a high level when the pushbutton is released.Each of the pushbottons are dedicated to Negative Reset(Reset_b),Positive Reset(Reset) and manual Clock(Mclk) as shown in Figure 1-1.Small resistors are placed in series between the FPGA and the pushbuttons to prevent damage if the FPGA tries to drive a pin that is being pulled low.

Manual Clock(Mclk):This pushbutton is used as a manual clock.The user may give the clock manually through the pushbutton. The clock is a sequence of high and low pulses,therefore when the pushbutton is pressed, a low is applied and high when released.This Pushbutton sends contact information to FPGA pin(P77) and the result is observed as designed.

For eg if u want a Dflip flop to be designed and provide a clock manually this can be done as follows. The DFlip Flop has only one input. This input is called D or Data input.

Q

CLK

D Flip Flop

Qb

D

1

0

1

Manual Clock Pulse

0


Figure 1-7:D Flip Flop and Clock Pulse.

Always at the positive edge of clock, the output Q is assigned with the value of D (input value).And Qb the bar of Q.So this Positive edge of clock(ie High Pulse) is given manually via Mclk Pushbutton when released and vice versa.

1.5.7 Seven-Segment LED[FND]

The RN-FDB Board has a 4 FNDs.Segments of the LED glow when a logic-high level is applied to them.The outputs can be displayed on each of the FNDs.The pin mapping of each FND is given in Table 1-2: FPGA P.

Figure 1-8: FND Arrangement Diagram

1.5.8 Oscillator

The RN-CB01 board provides user to use any one of the oscillators that are available on board. The oscillator consists of low jitter high precession crystal oscillator of 10Mhz.

E

B F

G

H

FND0

C

A

D

E

B F

G

H

FND1

C

A

D

E

B F

G

H

FND2

C

A

D

E

B F

G

H

FND3

C

A

D


1.6 PIN ASSIGNMENT

Table 1-2: FPGA Pin Assignment

FPGA PIN NO

MAPPED TO

FPGA PIN NO. MAPPED TO FPGA PIN NO. MAPPED TO

DAC LCD KEYPAD P119 DAC[7] P175 LCD_DATA[7] P198 DRV4

P120 DAC[6] P172 LCD_DATA[6] P197 DRV3




P125 DAC[2] P200 LCD_DATA[2] P190 SCAN3



P132 DAC_WR_B P167 LCD_ E P185 SCAN0

ADC P166 LCD_RNW PS2 PORT

P133 ADC_CHSEL[0] P165 LCD_RS P205 PS2_1_DATA

P138 ADC_READ RELAY P181 PS2_1_CLK


P139 ADC_WRITE P152 RELAY_ON_OUT P204 PS2_0_DATA

P150 ADC_INTR STEPPER MOTOR P180 PS2_0_CLK

P140 ADC[7] P155 STPR_R VGA PORT P141 ADC[6] P156 STPR_O

P143 ADC[5] P161 STPR_B P176 FPGA_VSYNC

P144 ADC[4] P162 STPR_G P52 FPGA_HSYNC

P146 ADC[3] SERIAL PORT P51 RED

P147 ADC[2] P182 FPGA_RIN P48 GREEN

P148 ADC[1] P178 FPGA_TOUT P46 BLUE

P149 ADC[0]

SEVEN SEGMENT DISPLAY

FND0 FND2 PUSHBUTTON SWITCHES

P2 F0A P26 F2A SW1 (neg pulse) P79

P3 F0B P27 F2B SW2 (pos pulse) P80

P7 F0C P28 F2C SW3[ (Mclk)] P76

P9 F0D P29 F2D CLOCK (Internal 4Mhz or 10Mhz)

P10 F0E P34 F2E P77 CLK

P11 F0F P35 F2F

P12 F0G P36 F2G

P4 F0H P22 F2H

FND1 FND3

P13 F1A P37 F3A

P15 F1B P39 F3B

P16 F1C P40 F3C

P18 F1D P42 F3D

P19 F1E P43 F3E

P20 F1F P44 F3F

P21 F1G P45 F3G

P5 F1H P24 F3H

Note:F0A:F0=FND0 and A is segment A of FND0.Details see Figure 1-8 for FND Dig.,

Table 1-3:FPGA pin assignment for input and output leds

GENERAL PURPOSE INPUT[DIPSWITCHES] AND OUTPUTS[LEDS]

DIPSWITCHES[INPUT] LEDS[OUTPUT]

P57 SW0 P87 LED0

P58 SW 1 P90 LED1

P61 SW 2 P93 LED2

P62 SW 3 P94 LED3

P63 SW 4 P95 LED4

P64 SW 5 P100 LED5

P65 SW 6 P101 LED6

P67 SW 7 P102 LED7


P68 SW 8 P106 LED8

P71 SW 9 P107 LED9

P72 SW10 P111 LED10

P74 SW11 P113 LED11

P78 SW12 P114 LED12

P81 SW13 P115 LED13

P85 SW14 P116 LED14

P86 SW15 P117 LED15

1.7 SCHEMATICS

1.7.1 General purpose I/O and FND


o

D13

LED

LED2D9

LED

LED4

D5

LED

LED3

LED10

D15

LED

D19

LED

D12

LED

D10

LED

LED11

LED15

LED6

C

R33

R-PACK

123456789

D6

LED

LED7

D18

LED

OUTPUT_LEDS

GENERAL PURPOSE PERIPHERALS

C

R32

R-PACK

123456789

D20

LED

D16

LED

D11

LED

LED1LED9

D14

LED

C

R34

R-PACK

123456789

LED8

LED12

D7

LED

OUTPUT_LEDS

D8

LED

LED5LED13

LED14

C

R31

R-PACK

123456789

D17

LED

LED0

DSI11

D30

LE

D

DSI6

SW4

SW DIP-8

12345678

161514131211109

DSI14

R4350E

INPUT_SWITCHES

DSI15

DSI2

D37

LE

D

SW5

SW DIP-8

12345678

161514131211109

R4450E

C

R41

R-PACK

123456789

D34

LE

D

D32

LE

D

D23

LE

DD

31

LE

D

D26

LE

D

D38

LE

D

GPIO_3.3V_POS

DSI10

DSI3

DSI7

DSI1

D28

LE

D

DSI0

D36

LE

D

DSI12

DSI8

DSI13

INPUT_SWITCHES

DSI5

D25

LE

D

D29

LE

DD

35

LE

D

DSI4

D24

LE

D

D27

LE

D

C

R39

R-PACK

123456789

D33

LE

D

DSI9


U19

10

9 8 7 6

1 2 3 4 5

g fG

ND a b

e d GN

Dc d

p

F3G

F3C

F3A

FND3

F3EF3F

R57R

F3B

F3H

F3D

LED3

DSI9

MCLK0

DSI2

F2A

LED14

F1B

DSI11

D3.3V_POS

DSI13

DSI6 LED6

LED11DSI10

F2E

F1D

LED1

DSI8

DSI12

LED7

DSI5

DSI0

JP6

Header_ch

1 234567891011121314151617181920

212223242526272829303132333435363738

39 40

RESET0

F3B

F2G

DSI3

LED0

D2.5V_POS

F3G

F1A

F2B

RESET0_B

F0C

LED4F0E

DSI7

DSI1

DSI14

F2F

LED13

LED15

CLK0

F0B

LED12F3D

F1E

D2.5V_POS

F0D

F0A

F1F

F2D

F0H

F0F

F2C

F3C

F3H

F3A

F1C

F3E

F1GF1H

D3.3V_POSJP3

Header_ch

1 234567891011121314151617181920

212223242526272829303132333435363738

39 40

LED10

LED2

LED9LED8

DSI4

LED5

F3F

F0GF2H

DSI15


1.7.2 Interfacing Modules

ALLIF_5V_POS

TEMPERATURE SENSOR

ADC_WRITEECO_R2510K

ADC_INTR

R45200E

ECO_J6

CON7

1234567

STPROUT_Y

ALLIF_5V_POS

STPR_G

ADC_IN[1]

ADC_READ

DAC0_WR_b

J4

CON1

1

JP4

Header_ch

1 234567891011121314151617181920

212223242526272829303132333435363738

39 40

ADC_CHSEL[0]

STPR_O

STPROUT_BL

DAC_IN[7]

R25

200E

DAC_IN[3]

DAC_IN[0]

STPR_O

DAC_IN[2]

ADC_IN[3]

DAC_IN[6]

DAC_IN[7]

STPROUT_O

ADC_IN[1]

STPR_B

R40

1K

13

2

STPR_R

ECO_C9

150pF

ADC_IN[7]

DAC_IN[2]

+

-

U8A

LM3583

21

84

DAC_IN[3]

STPROUT_BL

ADC_CHSEL[0]

DAC AND ADC MODULES

ADC_IN[5]

DAC_IN[1]

IO102

U10

ULN2003A

12345678 9

10111213141516

1B2B3B4B5B6B7BE COM

7C6C5C4C3C2C1C

ECO_JP1JUMPER1 2

R26

3K

ALLIF_5V_POS

IO146

ALLIF_5V_POS

ADC_READ

ADC_IN[4]

STPR_R

DAC_IN[6]

RELAY_CTRL_B

ALLIF_5V_pos

IO135

+

-

U8BLM358

5

67

84

STPROUT_O

ADC_IN[3]

U6

ADC0804

3

1

45

15

9 10

19

6

20

17

811121314

18

7

16

2

WR_b

CS_b

CLK_inINTRb

D3

Vref /2 D_GND

CLK_R

+Vin

VCC

D1

A_GNDD7D6D5D4

D0

-Vin

D2

RD_b

ECO_JP2

JUMPER

1 2

STPROUT_BR

U15

DAC0832

7654

16151413

817

201918

12103

2

911

1

DI0DI1DI2DI3DI4DI5DI6DI7

VrefXFERb

VccILE

WR2b

Iout2GNDGND

WR1b

Rf bIout1

CSbar

J8

CON1

1

STPR_G

ECO_KK8

TEMP_SENSOR

12

3

+VSVOUT

GN

D

ECO_R401K

13

2

D2.5V_POS

ADC_IN[4]

ADC_IN[0]

ADC_WRITE

ADC_PVIN

ADC_IN[2]

J5

CON1

1

STPROUT_BR

STEPPER MOTOR

D3.3V_POS

DAC_IN[5]

DAC_IN[1]

DAC_IN[4]

STPROUT_Y

DAC_IN[0]

DAC0_WR_B

J7

CON1

1

ADC_IN[7]

DAC_IN[4]ADC_IN[0]

ADC_PVIN

ADC_IN[6]

ADC_INTR

ALLIF_5V_pos

R301K

13

2

IO142

ADC_IN[2]

ADC_IN[5]ADC_IN[6]

DAC_IN[5]

TEMP_SENSOR_OUT

TEMP_SENSOR_OUT

STPR_B

R46

3K


F_LCD5

LCD_E

LCD_INTERFACE_16x2

LCD_DATA7

LCD_DATA3

LCD_DATA2

F_LCD0

F_LCD6

F_LCD1

LCD_DATA7

R50

50E

LCD_DATA2LCD_RW

F_LCD2

LCD_DATA4

LCD_DATA7

R4947E

LCD_RS

F_LCD4

LCD_DATA1

R52100E

D5V_POS

LCD_DATA2

F_LCD3

F_LCD7

LCD_DATA1

F_LCD4

ALLIF_5V_POS

LCD_DATA1

LCD_DATA5LCD_DATA5

U13

74LS241

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

1211

1G_b

1A1

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1

GND

Vcc

2G

1Y1

2A4

1Y2

2A3

1Y3

2A2

1Y42A1

LCD_DATA2 LCD_DATA5

F_LCD2 LCD_DATA0LCD_DATA0

ALLIF_5V_POS

LCD_DATA7

ALLIF_5V_pos

CONNECTORS

LCD_DATA6

LCD_DATA4

LCD_DATA6

R42

POT

13

2

LCD_DATA4F_LCD6

F_LCD3

F_LCD0

F_LCD1

LCD_DATA3LCD_DATA3

LCD_DATA1

LCD_DATA5F_LCD7

LCD_DATA4

LCD_DATA0

LCD_DATA6

R53

1K

LCD_DATA0

LCD_DATA6

LCD_DATA3

U12

LCD16x2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

GND

VCC

CON

RS

RW

E

D0

D1

D2

D3

D4

D5

D6

D7

LED_A

LED_K

F_LCD5

ALLIF_5V_POS

U9

MAX232

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

09

C1+

V+

C1-

C2+

C2-

V-

T2OUT

R2IN

VCC

GND

T1OUT

R1IN

R1OUT

T1IN

T2IN

R2OUT

P2

RS232_9pinCON

594837261

C12

0.1uF

C100.1uF

C110.1uF

C130.1uF

FPGA_TOUT

FPGA_RIN

FPGA_VSYNC

FPGA_HSYNC

P1

VGACONNECTOR

8157

146

135

124

113

10291

GREEN2

RRED

BLUE1

R3

R PS2_0_CLK

PS2_0_DATA

JS1

M-DIN_6-R

123 4

56

R23

10k

KEYBOARD MOUSE PS2CONNECTORS

ALLIF_5V_POS

R2410k

PS2_1_DATA

TCK

TDO

F_LCD0

DRV0

SCAN1

DRV3

SCAN2

F_LCD3

U20

KEYPAD_PORT5x4

1

2

3

4

5

6

7

8

9

DRV0

DRV1

DRV2

DRV3

DRV4

SCAN0

SCAN1

SCAN2

SCAN3

F_LCD_RW

REDFPGA_HSYNC

DRV2

F_LCD2

SCAN1

DRV1

GREEN

R58

12345

PS2_0_DATA

FPGA_TOUT

DRV0

BLUE

F_LCD_E PS2_0_CLK

FPGA_RIN

F_LCD4

IO162

SCAN0

SCAN2

DRV1

FPGA_VSYNCF_LCD6

F_LCD1

JP5

Header_ch

1 234567891011121314151617181920

212223242526272829303132333435363738

39 40

PS2_1_CLK

KEYPAD5x4 MATRIX SECTION

F_LCD7SCAN0

DRV2

DRV4

D2.5V_POS

FPGA_TDISCAN3

TMS

D3.3V_POS

F_LCD5

DRV3

SCAN3

F_LCD_RS

DRV4


1.7.3 Power Circuitry

C231UF

R59100

R67R

D45

LED

D3.3V_POS

R65220

R60R

U22

STLM3173 2

1

IN OUT

AD

J

R63100

U23

STLM3173 2

1

IN OUT

AD

J

C172200UF

R61

1

C163500UF

- +

D41BRIDGE

13

24

J9PLUG AC FEMALE

1 2

3

R68220

D2.5V_POS

R66200

C201UF

U21

STLM3173 2

1

IN OUT

AD

J

D48

RED LED

D42

LED

C2110UF/25V

C2410UF/25V

C151UF

D5V_POS

R64R

R62370C18

10UF/25V

J11

CON4

1234

DGND

D3.3

V_P

OS

GROUND CHAINING CONNECTOR

J10

CON4

1234

D2.5

V_P

OS

F1FUSE

D5V

_P

OS

F3FUSE

POWER BUS CHAINING CONNECTOR

J12

CON1

1

DGNDF2FUSE


1.7.4 FPGA AND PROM CONNECTIONS

DSI2

FP

GA

_A

DC

_C

LK

DRV3

JP2

JUMPER

1 2

LE

D15

F2c

SCAN1

F1h

D3.3V_pos

LED3

LED1

STPR_R

D2.5V_pos

F_LCD_RW

CLK0

F3a

SCAN3

F0a

F1c

AD

C_IN

[0]

F3fSCAN3

C16C

FP

GA

_V

SY

NC

AD

C_IN

TR

DSI7

IO142

C3C

F0d

F_LCD0

RELAY_CTRL_b

TMS

F2b

ADC_CHSEL[0]

JP1

JUMPER

1 2

F2a

TMS

F0c

TDI

LE

D13

DSI6IO102 F_LCD2

DA

C_IN

[3]

F0g

PROM_DONE

TDO

F_LCD_RS

ADC_IN[7]

DSI15

LED10

PS2_1_CLK

DAC_IN[1]

F2f

F0e

DSI12

C15C

DRV1

DA

C_IN

[1]

D3.3V_pos

PROM_DIN

ADC_IN[4]

DAC_IN[0]

LED2

LED11

PS2_0_CLK

D3.3V_pos

F1f

PS

2_1_C

LK

DSI14

DSI1

RE

D

C4C

D2.5V_pos

F3c

F_LCD4

F0d

C10C

F3h

ADC_IN[1]

DSI11

LED13

BLUE

PROM_INIT_b

DSI4

RE

SE

T0

C14C

TMS

F0g

ST

PR

_O

PS2_0_CLK

LE

D10

PROM_CCLK

F2d

FPGA_ADC_CLK

DAC_IN[6]

LED5

FPGA_VSYNC

C2C

DSI13

F_LCD_E

F1a

D3.3V_pos

IO135

DRV0

F1d

ST

PR

_R

F2f

SCAN0

C11C

LED9

STPR_G

LED1

F_LCD1

RESET0_b

DSI0

LE

D9

PROM_DONE

PROM_TDO

F2a

AD

C_IN

[4]

AD

C_IN

[7]

SCAN2

DAC_IN[5]

R1

4.7K

F2g

DRV2

D3.3V_pos

DSI9 F_LCD6

STPR_O

DSI10

F1g

PROM_TDO

F1h

TDI

AD

C_W

RIT

E

D3.3V_pos

F2b

TCK

IO102

F2g

LE

D8

DSI15

U5

Header_ch

1 234567891011121314151617181920

212223242526272829303132333435363738

39 40

DSI4

F_LCD_RS

DA

C_IN

[7]

F1a

C13C

F2h

DA

C0_W

R_b

PROM_PROGRAM_b

ADC_WRITE

DAC_IN[2]

MCLK0

LED6

TDO

F3e

DSI3

F0b

F_LCD6

DA

C_IN

[4]

C7C

R3

3.3K

DSI8

F_LCD1

F0e

F1e

FP

GA

_R

IN

F_LCD_RW

ADC_IN[5]

IO162

U3

Header_ch

1 234567891011121314151617181920

212223242526272829303132333435363738

39 40

U6

Header_ch

1 234567891011121314151617181920

212223242526272829303132333435363738

39 40

U4

Header_ch

1 234567891011121314151617181920

212223242526272829303132333435363738

39 40

FPGA_TDI

LED14

PS2_1_DATA

C6C

R2

3.3K

DSI2

FPGA_TDI

AD

C_IN

[3]

F0f

IO146

F_LCD7

PROM_CCLK

F3e

ADC_IN[2]

U2

XC18V512_PROM

45678

9 10

11

12

13

1817161514

3 2 1 20

19

TDITMSTCKD4/CF_bOE/RESET_b

D6

CE

_b

GN

DD

7C

EO

_b

VccintTDO

D1D3D5

CLK

D2

D0

Vccin

tV

cco

D2.5V_pos

PROM_DIN

F1g

F0c

PS

2_1_D

AT

A

LED2

GREEN

DA

C_IN

[5]

C9C

DSI13

F3h

LE

D11

IO146

TCK

F0f

SCAN0

F3d

LED0

F3b

ADC_INTR

F2cF2d

LED12

FPGA_HSYNC

D3.3V_pos

GR

EE

N

ST

PR

_G

F1c

D2.5V_pos

F0a

PROM_DONE

DRV4

F3d

DRV1RESET0

PROM-CIRCUITRY

LED3

FPGA_RIN

F_LCD7DAC_IN[4]

PROM_CCLK

F3f

F3b

FP

GA

_H

SY

NC

F_LCD5

PROM_DIN

DSI6

AD

C_IN

[1]

F3a

SCAN2

AD

C_IN

[2]

DSI1

DSI9

F_LCD3

STPR_B

F0h

MCLK0

LE

D6

F_LCD2

C5C

U1

XC2S200_PQ208

3

5

78

10

15161718

2122232930

333435363741

4344

464849

58

6061

636768697071

7475818283

86

87

88

89

90

94

96

97

99

101

102

110

112

113

120

121

122

123

127

133

134

138

139

140

141

148

149

151

163

165

166

168

172

173

174

175176

179180181187188

191192193194195199

201202

204

206

4

6

9

20

31

42

4547

57

59

62

73

1321292724

205

203

200

189

178

167

164

162

152

150

147

136

125

114

111

109

100

98

95

84

198

190

183

177

169

158

145

137

131

124

116

103

93

85

79

72

64

51

40

32

25

19

11

1 196

186

1552072159157104

7780161160107106154108

115

119

126135142146153545052

18218514

171

143

128

118

91

76

66

38

28

13

208

197

56

184

170

156

144

130

117

105

92

78

65

53

39

26

55

12I/O

I/O

I/OI/O

I/O

I/OI/OI/OI/O

I/OI/OI/OI/OI/O

I/OI/OI/OI/OI/OI/O

I/OI/O

I/OI/OI/O

I/O

I/OI/O

I/OI/OI/OI/OI/OI/O

I/OI/OI/OI/OI/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/OI/O

I/OI/OI/OI/OI/O

I/OI/OI/OI/OI/OI/O

I/OI/O

I/O

I/O

I/O VREF

I/O VREF

I/O VREF

I/O VREF

I/O VREF

I/O VREF

I/O VREFI/O VREF

I/O VREF

I/O VREF

I/O VREF

I/O VREF

I/O IRDY(1)I/O TRDY(1)I/O TRDY(1)I/O IRDY(1)

I/O VREF

I/O VREF

I/O VREF

I/O VREF

I/O VREF

I/O

VR

EF

I/O

VR

EF

I/O

VR

EF

I/O

VR

EF

I/O

VR

EF

I/O

VR

EF

I/O

VR

EF

I/O

VR

EF

I/O

VR

EF

I/O

VR

EF

I/O

VR

EF

I/O

VR

EF

I/O

VR

EF

I/O

VR

EF

I/O

VR

EF

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

VC

C I

NT

VC

C I

NT

CCLKTCKTMSTDI

TDODONE

I, GCK1I, GCK0

I/O (WRITE) BARI/O (CS) BAR

I/O (INIT) BARPROGRAM BAR

I/O (DOUT, BUSY)I/O D(7)

I/O

(D

6)

I/O

(D

5)

I/O D(4)I/O D(3)I/O D(2)I/O (D1)

I/O (DIN, D0)M2M1M0

I, GCK2I, GCK3I/O

VC

C I

NT

VC

C I

NT

VC

C I

NT

VC

C I

NT

VC

C I

NT

VC

C I

NT

VC

C I

NT

VC

C I

NT

VC

C I

NT

VC

C I

NT

VC

CO

VC

CO

NC

VC

CO

VC

CO

VC

CO

VC

CO

VC

CO

VC

CO

VC

CO

VC

CO

VC

CO

VC

CO

VC

CO

VC

CO

VCCO

NC

VCCO

<Doc>

<Title>

C

1 1Saturday , December 10, 2005

Title

Size Document Number Rev

Date: Sheet of

F2e

F3c

DRV3

F1e

DSI5

DSI10

DSI14

F_LCD5

DAC0_WR_b

LE

D12

PROM_INIT_b

C12C

F1d

DA

C_IN

[2]

LED15 FPGA_TDI

DSI12

DSI5

ADC_READ

F1f

SCAN1

DA

C_IN

[0]

IO162

C8C

D2.5V_pos

F_LCD_E

ADC_IN[6]

C1C

PROM_INIT_b

FP

GA

_T

OU

T

LED0

PS2_0_DATA

F1b

VQ44-pinPackage

TCK

DSI11

AD

C_IN

[5]

RE

LA

Y_C

TR

L_b

F_LCD0

PS2_0_DATA

DAC_IN[7]

DSI7

LE

D5

DA

C_IN

[6]

F3g

ADC_IN[3]

AD

C_IN

[6]

LED4

DRV4

DSI8

IO135

AD

C_R

EA

D

BLU

E

AD

C_C

HS

EL[0

]

DRV2

ST

PR

_B

F2h

ADC_IN[0]

F3g

DSI3

LE

D4

LED7RED

F0b

LE

D14

DSI0PROM_PROGRAM_b

IO142

CLK0

F_LCD3

RE

SE

T0_b

D2.5V_pos

PROM_PROGRAM_b

LE

D7

F2e

F0h

F1b

LED8

FPGA_TOUTDAC_IN[3]

F_LCD4

DRV0


1.8 APPENDIX:

1.8.1 External Interfacing Modules

The Board has 40pin extension connectors named ECO_JP3, ECO_JP4, ECO_JP5, ECO_JP6(see Figure 1-1 1) which can be utilized for external interfacing modules.Each of the 40pin connectors are connected to FPGA The user may use the additional connectors for connecting external circuits as per the requirement.The board has additional two 4pin power connector(pwr con) for power chaining to external interfacing modules(see Figure 1-1).The 40 pin extension pin connections are given in Table 1-4.

Table 1-4: Pin connections for external interfacing modules

40 PIN EXTENSION CONNECTOR

EXT PIN No.

ECO_JP3

ECO_JP4 ECO_JP5 ECO_JP6

1 NC NC NC NC

2 NC NC NC NC

3 F0A NC LCD_RS SW0

4 F0B NC LCD_RW SW 1

5 F0C NC LCD_E SW 2

6 F0D NC LCD[0] SW 3

7 F0E NC LCD[1] SW 4

8 F0F IO102 LCD[2] SW 5

9 F0G DAC[7] LCD[3] SW 6

10 F0H DAC[6] LCD[4] SW 7

11 F1A DAC[5] LCD[5] SW 8

12 F1B DAC[4] LCD[6] SW 9

13 F1C DAC[3] LCD[7] SW10

14 F1D DAC2] SCAN[0] SW11

15 F1E DAC[1] SCAN[1] SW12

16 F1F DAC[0] SCAN[2] SW13

17 F1G DAC_WR_B SCAN[3] SW14

18 F1H IO135 DRV[0] SW15

19 F2A IO142 DRV[1] MCLK0

20 F2B IO146 DRV[2] CLK0

21 F2C ADC_CHSEL DRV[3] LED0

22 F2D ADC_READ DRV[4] LED1

23 F2E ADC_WRITE PS2_0_CLK LED2

24 F2F ADC[7] PS2_0_DATA LED3 25 F2G ADC[6] PS2_1_CLK LED4

26 F2H ADC[5] PS2_0_DATA LED5

27 F3A ADC[4] BLUE LED6

28 F3B ADC[3] GREEN LED7

29 F3C ADC[2] RED LED8

30 F3D ADC[1] FPGA_HSYNC LED9

31 F3E ADC[0] FPGA_VSYNC LED10

32 F3F ADC_INTR FPGA_TOUT LED11

33 F3G NC FPGA_RIN LED12


34 F3H RELAY_CTRL_B TCK LED13

35 NC STPR_R TMS LED14

36 NC STPR_O FPGA_TDI LED15

37 NC STPR_B TDO NC

38 NC STPR_G IO162 NC

39 NC NC NC NC

40 NC NC NC NC

NC:NOT CONNECTED

Documents

Spartan 3 Board