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EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 1
EE247Lecture 21
ADC Converters (continued)– Successive approximation ADCs
(continued)– Flash ADC– Flash ADC sources of error
• Sparkle code• Meta-stability
– Comparator design
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 2
Summary of Last LectureADC Converters
– Sampling (continued)• Track & hold circuits• T/H combined with summing/difference function• T/H circuit incorporating gain & offset cancellation
– Electro-Static Discharge (ESD) protection
– ADC architectures • Serial- slope type• Successive approximation
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 3
Successive Approximation ADC
• High accuracy achievable (16+ Bits) • Require N clock cycles for N-bit conversion (much faster than slope type)• Moderate speed proportional to B (MHz range)
VDAC/VREF
Time / Clock Ticks
1
1/2
3/45/8
VIN
1/2 3/4 5/8 11/16 21/32 41/64
Example: 6-bit ADC & VIN=5/8VREF
ADC 101000
DAC
VIN
ControlLogic
Clock
VREF
T/H
Test MSB
Test MSB-1
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 4
Example: SAR ADCCharge Redistribution Type
• T/H inherent in DAC• Operation starts by connecting all top plate to gnd and all bottom plates to Vin• To test the MSB all top plate are opened bottom plate of 32C connected to VREF &
rest of bottom plates connected to ground input to comparator= -Vin +VREF/2 • Comparator is strobed to determine the polarity of input signal if - MSB=1 if +
MSB=0• The process continues until all bits are determined
C2C4C8C32COut
Stop
b1b2b3b4 (msb)
-
Comparator
16C
b3
C
VinVREF
Vin ControlLogicTo
switches
b0
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 5
Example: SAR ADCCharge Redistribution Type
• To 1st order parasitic (Cp) insensitive since top plate driven from initial 0 to final 0 by the global negative feedback
• Linearity is a function of accuracy of C ratios• Possible to add a C ratio calibration cycle (see ref.)
C2C4C8C32COut
reset
b1b2b3b4 (msb)
CP
-
Comparator
16C
b3
C
VinVREF
Vin ControlLogicTo
switches
Ref: H. Lee, D. A. Hodges, and P. R. Gray, "A self-calibrating 15 bit CMOS A/D converter," IEEE Journal of Solid-State Circuits, vol. 19, pp. 813 - 819, December 1984.
b0
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 6
Flash ADC• B-bit flash ADC:
–DAC generates all possible 2B -1 levels
–2B-1 comparators compare VIN to DAC outputs
–Comparator output:• If VDAC < VIN 0• If VDAC > VIN 1
–Comparator outputs form thermometer code
–Encoder converts thermometer to binary code
DigitalOutput
DAC
2B-1 BEncoder
VREF VIN fs
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 7
Flash ADC ConverterExample: 3-bit Conversion
Enc
oder
fs
Thermometer code
B-bits
Time
VREF
0
0
1
1
1
1
1
1
0
1
VIN VIN VREF
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 8
Flash Converter
• Very fast: only 1 clock cycle per conversion
– Half cycle VIN & VDACcomparison
– Half cycle 2B -1 to B encoding
• High complexity: 2B-1 comparators
• Input capacitance of 2B-1 comparators connected to the input node:
High capacitance @ input node
Enc
oder
fsVIN VREF
Thermometer code
B-bits
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 9
Flash Converter Sources of Error
• Comparator input:– Offset– Nonlinear input capacitance– Kickback noise (disturbs
reference)– Signal dependent sampling
time
• Comparator output:– Sparkle codes (… 111101000
…)– Metastability
R/2
R
R
R
R/2
R
Enc
oder Digital
Output
VINVREF fs
.....
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 10
Flash ConverterExample: 8-bits ADC
• 8-bits 255 comparators
• VREF=1V 1LSB=4mV
• DNL<1/2LSB Comparator input referred offset < 2mV
• 2mV =6σoffsetσoffset < 0.33mV
R/2
R
R
R
R/2
R
Enc
oder Digital
Output
VINVREF fs
.....
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 11
Flash ADC ConverterExample: 8-bits ADC (continued)
1σOffset < 0.33mV• Let us assume in the technology used:
– Voffset-per-unit-sqrt(WxL)=3 [mVx μ]
– Issues:• Si area quite large• Large input capacitance• Since depending on input voltage different number of comparator input
transistors would be on/off- total input capacitance varies as input variesNonlinear input capacitance could give rise to signal distortion particularly at
high frequencies
20
2
3[ ] 0.33 83
2Assuming: 9 / 4963
Total input capacitance: 255 0.496 126.5 !
ffset
ox GS ox
mVV mV W LW L
C fF C C W L fF
pF
μ μ
μ
= = → × =×
= → = × =
→ × =
Ref: M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid-State Circuits, vol. 24, pp. 1433 - 1439, October 1989.
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 12
Flash ADC ConverterExample (continued)
Trade-offs:– Allowing larger DNL e.g. 1LSB instead of 0.5LSB:
• Increases the maximum allowable input-referred offset voltage by a factor of 2
• Decreases the required device WxL by a factor of 4• Reduces the input device area by a factor of 4• Reduces the input capacitance by a factor of 4!
– Reducing the ADC resolution by 1-bit• Increases the maximum allowable input-referred offset voltage by a factor
of 2• Decreases the required device WxL by a factor of 4• Reduces the input device area by a factor of 4• Reduce the input capacitance by a factor of 4
– Add offset cancellation to the comparator and thus decrease the input device area– could reduce the conversion rate
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 13
Flash ConverterMaximum Tolerable Comparator Offset versus ADC Resolution
10-1
1
10
102
4 6 8 10
VREF=1V
VREF=2V
Assumption: DNL=0.5LSB
Note:Graph shows offset, note that depending on min acceptable yield, the derived offset numbers are associated with 2σ to 6σ offset voltage
ADC Resolution
Max
imum
Com
para
tor V
offs
et[m
V]
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 14
Typical Flash Output Encoder
0
0
1
1
1
0
1
0
0
Binary Output (negative)
Thermometer to Binary encoder ROM
VDD
• Thermometer code 1-of-n decoding
• Final encoding NOR ROM
• Ideally, for each code, only one ROM row is activated
b3b2b1
b0
b3 b2 b1 b0Output 0 0 1 1
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 15
Sparkle Codes
Correct Output:0111
Problem: Two rows are on
Erroneous Output:1111
1/2FS error!
0
1
0
1
1
1
0
1
0
Erroneous 0 (comparator offset?)
VDD
b3b2b1
b0
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 16
Sparkle Tolerant Encoder
Protects against a single sparkle.
Ref: C. Mangelsdorf et al, “A 400-MHz Flash Converter with Error Correction,” JSSC February 1990, pp. 997-1002
0
0
1
0
1
0
1
0
0
0
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 17
Meta-StabilityDifferent gates interpret meta-stable output X differently
Correct output: 0111
Erroneous output: 1111
Solutions:–Extra latches following
comparator (high power)–Gray encoding
Ref: C. Portmann and T. Meng, “Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters,” JSSC August 1996, pp. 1132-40
0
0
X
1
1
0
1
1
0
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 18
Gray Encoding
• Each Ti affects only one GiAvoids disagreement of interpretation by multiple gates
• Protects also against sparkles• Follow Gray encoder by (latch and) binary encoder
BinaryGrayThermometer Code
1110011111111
0111011111110
1011111111100
0010111111000
1100101110000
0101101100000
1001001000000
0000000000000
B1B2B3G1G2G3T1T2T3T4T5T6T7
43
622
75311
TGTTG
TTTTG
==
+=
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 19
Voltage Comparators
Play an important role in majority of ADCsFunction: Compare the instantaneous value of two analog signals &
generate a digital output voltage based on the sign of the difference:
+
-Vout (Digital Output)
VDD
If Vi+ -Vi- > 0 Vout=“1”If Vi+ -Vi- < 0 Vout=“0”
Vi+
Vi--
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 20
Voltage ComparatorArchitectures
Comparator architectures• High gain amplifier with differential analog input & single-ended large
swing output– Output swing compatible with driving digital logic circuits– Open-loop amplification no frequency compensation required– Precise gain not required
• Latched comparators; in response to a strobe, input stage disabled & digital output stored in a latch till next strobe
– Two options for implementation :• Latch-only comparator• Low-gain amplifier + high-sensitivity latch
• Sample-data comparators– T/H input– Offset cancellation
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 21
Comparators w/ High-Gain Amplification
Amplify Vin(min) to VDD Vin(min) determined by ADC
resolution
Example: 12-bit ADC with:- VFS= 1.5V 1LSB=0.36mV- VDD=1.8V
For 1.8V output & 0.5LSB precision:
Minv
1.8VA 10,000
0.18mV= ≈
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 22
Comparators 1-Single-Stage Amplification
Too slow!Try cascade of lower gain stages to broadband response
fu=0.1-10GHz
f0 fufrequency
Gain
Av
u o
uo
Vu V
o
set t l ingo
Max.Clock
set t l ing
f uni ty-gain frequency, f =-3dB frequency
f f =
AExample: f =1GHz & A 10,000
1GHz f 100kHz
10,0001
1.6 sec2 f
Al low a few for output to set t le 1
f 126kHz5
τ μπ
τ
τ
=
=
= ≈
= =
→ ≈
Assumption: Single pole amplifier
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 23
Comparators2- Cascade of Open Loop Amplifiers
The stages identical small-signal model for the cascades:
One stage:
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 24
Open Loop Cascade of Amplifiers
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 25
Open Loop Cascade of AmplifiersFor |AT(DC)|=10,000
( )
u T
1/ 3 1o N 1/ 3
s e t t l i n go
M a x .C l o c k
s e t t l i n g
E x a m p l e :
N = 3 , f = 1 G H z & A ( 0 ) 1 0 0 0 0
1 G H zf 2 2 3 .7M H z1 0,0 0 0
1 7n s e c2 f
A l l o w a f e w f o r o u t p u t t o s e t t l e
1f 2 9M H z5
τπ
τ
τ
−
=
= ≈
= =
→ ≈
fmax improved from 126kHz to 29MHz x225
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 26
Open Loop Cascade of AmplifiersOffset Voltage
• From offset point of view high gain/stage is preferred
• Choice of # of stage
bandwidth vs offset tradeoff
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 27
Open Loop Cascade of AmplifiersStep Response
•Assuming linear behavior
t
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 28
Open Loop Cascade of AmplifiersStep Response
•Assuming linear behavior
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 29
Open Loop Cascade of AmplifiersDelay/(C/gm)
• Minimum total delay broad function of N
• Relationship between # of stages that minimize delay (Nop) and gain (Vout/Vin) approximately:
Delay/(C/gm)
Ref: J.T. Wu, et al., “A 100-MHz pipelined CMOS comparator ” IEEE Journal of Solid-State Circuits, vol. 23, pp. 1379 - 1385, December 1988.
N 1 log A for A 1000opt 2 T
N 1.2ln A for A 1000opt T
≈ + <
≈ ≥
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 30
Offset Cancellation• In sampled-data cascade of amplifiers Vos can be cancelled
Store on ac-coupling caps in series with amp stages
• Offset associated with a specific amp can be cancelled by storing it in series with either the input or the output of that stage
• Offset can be cancelled by adding a pair of auxiliary inputs to the amplifier and storing the offset on capacitors connected to the aux. inputs during offset cancellation phase
Ref: J.T. Wu, et al., “A 100-MHz pipelined CMOS comparator ” IEEE Journal of Solid-State Circuits, vol. 23, pp. 1379 - 1385, December 1988.
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 31
Offset CancellationOutput Series Cancellation
• Amp modeled as ideal + Vos (input referred)
• Store offset:•S1, S4 open•S2, S3 closed
VC=AxVOS
Ref: J.T. Wu, et al., “A 100-MHz pipelined CMOS comparator ” IEEE Journal of Solid-State Circuits, vol. 23, pp. 1379 - 1385, December 1988.
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 32
Offset CancellationOutput Series Cancellation
Amplify:• S1, S4 closed• S2, S3 open
VC=AxVOS
Circuit requirements:• Amp not saturate during offset
storage• High-impedance (C) load Cc not
discharged• Cc >> CL to avoid attenuation• Cc >> Cswitch offset due to charge
injection
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 33
Offset CancellationCascaded Output Series Cancellation
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 34
Offset CancellationCascaded Output Series Cancellation
1- S1 open, S2,3,4,5 closed
VC1=A1xVos1
VC2=A2xVos2
VC3=A1xVos3
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 35
Offset CancellationCascaded Output Series Cancellation
2- S3 open• Feedthrough from S3 offset on X• Switch offset , ε2 induced on node X• Since S4 remains closed, offset associated with ε2 stored on C2
VX= ε2
VC1=A1xVos1- ε2
VC2=A2x(Vos2+ ε2)
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 36
Offset CancellationCascaded Output Series Cancellation
3- S4 open•Feedthrough from S4 offset on Y•Switch offset , ε3 induces error on node Y•Since S5 remains closed, offset associated with ε3 stored on C3
VY= ε3
VC2=A2x(Vos2+ ε2) - ε3
VC3=A3x(Vos3+ ε3)
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 37
Offset CancellationCascaded Output Series Cancellation
4- S2 open, S1 closed, S5 open• S1 closed & S2 open since input connected to low impedance source
charge injection not of major concern• Switch offset , ε4 introduced due to S5 opening
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 38
Offset CancellationCascaded Output Series Cancellation
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 39
Offset CancellationCascaded Output Series Cancellation
Example: 3-stage open-loop differential amplifier with offset cancellation + output amplifier (see ref.)
ATotal(DC) = 2x106 = 120dBInput-referred offset < 5μV
Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE Journal of Solid-State Circuits, vol. 13, pp. 499 - 503, August 1978.
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 40
Offset CancellationOutput Series Cancellation
• Advantages:– Compete cancellation – Closed-loop stability not required
• Disadvantages:– Gain per stage must be small – Offset storage C in the signal path- could slow
down overall performance
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 41
Offset CancellationInput Series Cancellation
Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE Journal of Solid-State Circuits, vol. 13, pp. 499 - 503, August 1978.
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 42
Offset CancellationInput Series Cancellation
Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE Journal of Solid-State Circuits, vol. 13, pp. 499 - 503, August 1978.
Store offset
Note: Mandates closed-loop stability
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 43
Offset CancellationInput Series Cancellation
Amplify
S2, S3 openS1 closed
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 44
Offset CancellationCascaded Input Series Cancellation
ε2 charge injection associated with opening of S4
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 45
Offset CancellationInput Series Cancellation
• Advantages:– In applications such as C-array successive
approximation ADCs can use C-array to store offset
• Disadvantages:– Cancellation not complete– Requires closed loop stability– Offset storage C in the signal path- could slow
down overall performance
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 46
CMOS ComparatorsCascade of Gain Stages
Fully differential gain stages 1st order cancellation of switch feedthrough offset
1-Output series offset cancellation
2- Input series offset cancellation
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 47
CMOS ComparatorsCascade of Gain Stages
3-Combined input & output series offset cancellation
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 48
Offset Cancellation
• Cancel offset by additional pair of inputs (Lecture 20 slide 16 &17)
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 49
Latched Comparators
Vi+
Vi--
Vout (Digital Output)
+
-
Latch
Vout
Vi+ - Vi-
t
Latch
t
t
“1”
“0”
Compares two input voltages at time tx & generates a digital output:
If Vi+ -Vi- > 0 Vout=“1”If Vi+ -Vi- < 0 Vout=“0”
tx
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 50
CMOS Latched Comparators
Comparator amplification need not be linearcan use a latch regeneration
Latch Amplification + positive feedback
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 51
CMOS Latched ComparatorsSmall Signal Model
Latch can be modeled as a:Single-pole amp + positive feedback
Small signal ac half circuit
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 52
CMOS Latched ComparatorLatch Delay
2 2
1 1
2D 2 1
1
1 11 1
1 1 1Integrating both sides: 1 ln ln ln ln
Latch Delay:1 ln11
mL
m m
m L m L
t V a amb
t V bm L
m
m L
V dVg V CR dt
g dV g dVV dtC g R dt C g R V
g adt dV dx x a bC g R V x b
C Vt t tg V
g R
= +
⎛ ⎞ ⎛ ⎞− = − =⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠
⎛ ⎞ ⎛ ⎞− = = = − =⎜ ⎟⎜ ⎟ ⎝ ⎠⎝ ⎠
⎛ ⎞ ⎛ ⎞= − = ⎜ ⎟ ⎜⎝−⎜ ⎟⎜ ⎟
⎝ ⎠
∫ ∫ ∫
2D
1
For 1
ln
m L
m
g R
C Vtg V
⎟⎠
>>
⎛ ⎞≈ ⎜ ⎟⎝ ⎠
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 53
CMOS Latched Comparators
2D
1
2
1
D
ln
ln
m
L
Lm
C Vtg V
V Latch Gain AV
Ct Ag
⎛ ⎞≈ ⎜ ⎟⎝ ⎠
→ =
→ ≈Compared to a 3-stage open-loop cascade of amps for equal overall gain of 1000
Latch faster by about x3
Normalized Latch Delay
D
m
tC
g
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 54
Latch-Only Comparator
• Main problem associated with latch-only comparator topology:
– High input-referred offset voltage (as high as 100mV!)• Solution:
–Use preamplifier to amplify the signal and reduce overall input-referred offset
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 55
Pre-Amplifier + LatchOverall Input-Referred Offset
LatchVi+
Vi-
Do+
Do-
fs
Preamp
Av
VosLatchVos
Preamp
2 2Re _ _ Pr _2
Pr
_ Pr _ Pr
2 2Re _ 2
1
: 4 & 50 & 10
14 50 6.410
Input ferred Offset Vos eamp Vos Latcheamp
Vos eamp Vos Latch eamp
Input ferred Offset
A
Example mV mV A
mV
σ σ σ
σ σ
σ
−
−
= +
= = =
= + =
Latch offset attenuated by preamp gain when referred to preamp inputAssuming the two offset sources are uncorrelated:
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 56
Pre-Amplifier Tradeoffs
• Example:– Latch offset 50 to 100mV– Preamp DC gain 10X– Preamp input-referred latch offset 5 to 10mV– Input-referred preamplifier offset 2 to 10mV– Overall input-referred offset 5.5 to 14mV
Addition of preamp reduces the latch input-referred offset reduced by ~7 to 9X ~extra 3-bit resolution!
LatchVi+
Vi-
Do+
Do-
fs
Preamp
Av
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 57
Comparator Preamplifier Gain-Speed Tradeoffs
• Amplifier maximum Gain-Bandwidth product (fu)for a given technology, typically a function of maximum device ft
Tradeoff:• To reduce the effect of latch offset high preamp gain desirable• Fast comparator low preamp gain
0 0
0
preamp
0
preamp
0 0
=unity gain frequency, 3 frequency & settling time
For example assuming preamp has a gain of 10:1 100
10
1 1.6 sec2
u
u
u
f f dBff
A
f GHzf MHzA
nf
τ
τπ
= − =
= =
= = =
= =
fu=0.1-10GHz
f0 fuFrequency
Magnitude
Av
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 58
Latched Comparator
Av LatchVi+
Vi-
Do+
Do-
fs
Preamp
Important features:– Maximum clock rate fs settling time, slew rate, small signal bandwidth– Resolution gain, offset– Overdrive recovery– Input capacitance (and linearity of input capacitance!)– Power dissipation– Input common-mode range and CMR – Kickback noise– …
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 59
Comparators Overdrive Recovery
U amplification after time ta
During reset amplifier settles exponentially to its zero input condition with τ0=RC
Assume Vm maximum input normalized to 1/2lsb (=1)
Linear model for a single-pole amplifier:
Example: Worst case input/output waveforms
Previous input max. possible e.g. VFSCurrent input min. input-referred signal
(0.5LSB)
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 60
Comparators Overdrive Recovery
Example: Worst case input/output waveforms
If trecovery is not high enough to allow output to discharge (recover) from previous state- then it may not be able to resolve the current input errorTo minimize this effect:
1. Passive clamp2. Active restore3. Low gain/stage
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 61
Comparators Overdrive RecoveryLimiting Output
ClampAdds parasitic capacitance
Active RestoreAfter outputs are latched Activate φR &
equalize output nodes
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 62
CMOS Latched Comparator DelayIncluding Preamplifier
2D
1
0D
Latch delay found previously:
ln
Assuming gain of for the preamplifier:
ln
m
v
vm in
VCg V
A
VC Ag V
τ
τ
⎛ ⎞≈ ⎜ ⎟⎝ ⎠
⎛ ⎞≈ ⎜ ⎟⎝ ⎠
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 63
Latched Comparator Including PreamplifierExample
oV
inV
-+
+
-
M1 M2CLK
M3 M4
VDD
( )( )
3 31
3 1 1
0D
Preamplifier gain:
Comparator delay:
ln
M MMGS thm
v M M Mm GS th
vm
V VgAg V V
VC Ag Vin
τ
−= =
−
⎛ ⎞≈ ⎜ ⎟⎝ ⎠
M7 M8bias
M5 M6
M9
Preamp Latch
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 64
Comparator Dynamic Behavior
vOUT
CLK
TCLK
τdelay
Comparator Reset Comparator Decision
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 65
Comparator Resolution
VIN =10mV 1mV
0.1mV10μVvOUT
CLK
Δt = (gm/C).ln(Vin1/Vin2)
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 66
Comparator Voltage Transfer FunctionNon-Idealities
Vout
Vin
VOffset
ε
-0.5LSB 0.5LSB
VOffset Comparator offset voltage
ε Meta-Stable region (output ambiguous)
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 67
CMOS Comparator Example
Ref: A. Yukawa, “A CMOS 8-Bit High-Speed A/D Converter IC,” JSSC June 1985, pp. 775-9
• Flash ADC: 8bits, +-1/2LSB INL @ fs=15MHz (Vref=3.8V, LSB~15mV)• No offset cancellation
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 68
Comparator with Auto-Zero
Ref: I. Mehr and L. Singer, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications,” JSSC July 1999, pp. 912-20.
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 69
Ref: I. Mehr and D. Dalton, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications,” JSSC July 1999, pp. 912-20.
Voffset
( )C C
Re f Re f Offset
V VV V V
+ −
+ −
− =− −
Flash ADCComparator with Auto-Zero
EECS 247 Lecture 21: Data Converters © 2006 H.K. Page 70
Ref: I. Mehr and D. Dalton, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications,” JSSC July 1999, pp. 912-20.
Voffset
Vo
( ) ( )[ ]( )
( ) ( )
Offseto P1 P2 In In C C
C C
Re f Re fo P1 P2 In In
VV A A V V V V
Substi tut ing for from prev ious cyc le:V V
V VV A A V V
Note: Offse t is cancelled & dif ference be tweeninput & re ference established
+ − + −
+ −
+ −+ −
− − −= ∗ − −
−
−= ∗ −⎡ − ⎤⎣ ⎦
Flash ADCComparator with Auto-Zero