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SFPSMA CLK
(Differential)
GTP RefCLKSMA
FMC-LPCConnector DDR3
Status LEDs
4x LEDs
4x Push ButtonsLow-power GTP Transceiver(RX/TX)
12v Fan
User CLKSocket
PCle Gen 1
SPI(Prog/Sel/Header)
Mode Switches
Power On/Off
12v Power
PROG and Reset Push Buttons
System ACE Mode Selections
Power Monitoring
High-speed Differential GPIO (SMA)4x I/O
USB JTAG Download Port
Serial USB-UART
Ethernet Status LEDs
Ethernet RJ45
10/100/1000 Ethernet PHY
Video DVI/VGA
Suspend
IIC EEPROM(reverse side)
FPGA: XC6SLX45TFGG484 Spartan-6
16MB Parallel (BPI)Linear Flash
System ACE CF
4x DIP Switches
For More InForMatIon Go to www.xIlInx.coM/sp605
This Hardware Setup Guide will provide the step by step setup instructions to run the diagnostic demo design that is pre-installed on the FLASH of the SP605 Evaluation Board.
sp605 evaluation kitsp605 evaluation kit HArdwArE SETuP GuidEHArdwArE SETuP GuidE
SP605 HArdwArE SETuP GuidE
BoArd FEATurESxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Support InformationTo download design Tools, generate license or get latest tool updates go to www.xilinx.com/support/download
For Technical Support, go to www.xilinx.com/support. on this site you can:
• Subscribe to Alerts on Product Technical documentation updates• Choose instructor-led classes and recorded e-learning options under Training• Collaborate with the xilinx user Community on the Forums• Quickly scan titles of Answers database categories through the Answer Browser• Submit cases and report bugs online 24 hours a day through webCase• initiate and manage return of hardware and software products through the rMA Portal
For more information about this kit, please refer to the Getting Started Guide also included in the kit box. The Getting Started Guide provides further instructions on running demos, installing software, and using the available reference designs to quickly and efficiently develop your applications.
For additional details, please visit the product page for more details: http://www.xilinx.com/sp605
© Copyright 2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Printed in the U.S.A. Xilinx Part Number: 0402790-01/ PN 2426
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STEP 2i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i
STEP 6i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i
STEP 4i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i
STEP 8i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i
STEP 10i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i
Connecting Cables and CF Card
install the CF card that is included in the kit. Connect the Ethernet cable to your PC and the SP605 board. Connect the dVi port to a monitor (dVi2VGA adaptor included), Plug in the power Adaptor to the local AC power. Plug the 12 volt power jack into the board connector on J18. Turn on the power by switching the Sw1 to the “oN” position.
Select an Image
on the uSB FLASH there are images to select. Select the image fractal1.jpg in directory SP601_Brd_reference_design --> SP601_Brd_images. Then “Click” the “show display” Gui button. if you have connected a dVi or VGA monitor, you will also see this image displayed on the monitor.
Setting Ethernet Link
in the Base reference design Gui Application select the menu item Setup, then select a network. You will see the Gui indicate “Connected to FPGA” and you will see the Ethernet Status lights active on the SP605.
Load with Base Reference Design Demo
Verify the SystemACE (S1) diP Switch is set to “1101” where 1, 2, and 4 are set to the “oN” position and switch 3 is set to the “oFF” position. Then press the SYSACE reset switch (Sw9) to make sure the FPGA loads from the CF card slot 3.
Installing the Application GUI
The Base reference design includes an application Gui that must be installed before you will be able to run the demo. on the uSB FLASH drive, included with the kit, you will find a directory called SP605_Brd_reference_design.--> SP605_Brd _Application directory. in there you will find an install image, Baserefdi_Setup2_0_4.msi. This is an application Gui that is used to display the graphical information for the Base reference design. Please double click on this application to install the software.
Experimenting with the Demo
As you select different filter effects, you will see that the image is filtered using these different transform effects. You will notice that the 5x5 Filter coefficient table changes every time you change an effect.
using the dSPmode selection, you may choose between “Logic” and “dSP48A.” The “dSP48A” option will utilize the dPS blocks in the Spartan-6 FPGA. The “Logic” selection will re-load a new design that only uses FPGA logic resources.
To demonstrate the performance these blocks provide, notice the Processing Time for the dSP implementation is around 10.66 mS. when you select “Logic” you will see the FPGA Program and done LEd flash, indicating an FPGA reconfiguration. You will also see that the Ethernet link will disconnect and then reconnect. You will see that the “Logic” version of the design processes the image at about 5x slower than the dPS implementation, running at about 53.3 mS.
sp605 evaluation kitsp605 evaluation kit HArdwArE SETuP GuidEHArdwArE SETuP GuidE
STEP 1i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i
STEP 5i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i
STEP 3i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i
STEP 7i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i
STEP 9i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i
Setting the Default Jumpers
Header J46 and J44 should have Jumpers installed, J22 should have a Jumper on 1,2 and J19 should have a Jumper on 1,2. The following headers should not have any Jumpers installed: J45, J47, J9, J58, J9, J13, J10, J60, J49, and J48.
Starting the Base Reference Design GUI Application
To start the application Gui, please go to your windows STArT menu and select All Programs --> xiLiNx --> Base reference design --> Base reference design interface.
Setting the Configuration Mode
The Base reference design is located in slot 3 of the CF card. The SystemACE (S1) diP Switch is set to “1101” where 1, 2, and 4 are set to the “oN” position and switch 3 is set to the “oFF” position. The Configuration Mode (diP Switch Sw1) can be set with both M0 and M1 in the “oFF” position.
Changing the Filter Effect
The default filtering in Step 8 was “identity”, now use the “Effect” menu to select “Edge detect.” Select other Effects. For more options please see the SP605 Getting Started Guide.
