A System C Based State Space Solver for AMS

Simulations

Rajat Mitra

May 31, 2015

Abstract

The document details a structured Analog Mixed Signal (AMS)simulation environment based on a State Space Solver (SSS). The ad-vantages and caveats of the SSS are outlined and the author explainsthe benefits of this approach in rapid design prototyping.

1 Introduction

Traditional AMS simulations have involved simulating the digital portionof the design with analog circuitry at a transistor level. The Cadence Vir-tuosso Environment is well suited for this type of simulation and has beenused successfully to verify proper functional behavior of the over all mixedsignal system. The digital portions of the design are simulated using Ver-ilog or VHDL and the analog portions of the design are simulated usingSPICE/Spectre. Virtuosso synchronizes simulations events across the mixedsignal domains to yield a very realistic functional scenario of the overall de-sign. This yields a great deal of confidence to the verification effort thatthe I/O between the analog and the digital domain has been hooked up cor-rectly and that the analog section correctly interacts with the digital section.

The disadvantage of traditional AMS simulations is that when prototyp-ing / architecting a mixed signal architecture, neither the digital block northe analog circuitry is initially available. In most cases a quickly prototypeddigital block can easily be put together for concept testing. However the lackof a hardware platform means that the block has to wait till some represen-tation of the analog circuitry is contrived on an FPGA prototyping board.Further the contrived analog circuitry may not be a faithful representationof the final analog block.

In such a situation the Cadence Incisive Environment offers a very flexi-ble simulation platform using the IRUN methodology. The IRUN methodol-ogy easily allows for mixed language simulation and this is where the power

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of the combined Verilog (digital) and SystemC (Analog) languages can beexploited to do a true AMS simulation without resorting to transistor levelimplementations of the analog circuitry.

While there are other approaches to simulate the behavior of the analogblock (Verilog A or Verilog AMS) the procedure that is detailed using Sys-temC is simple, fast and can be used for ESL type simulations.

2 Modeling Analog Behavior

For the most part modeling linear non-conservative analog components likean amplifier, digital to analog converter, analog to digital converter, offsetgenerator is fairly straight forward. However when one considers conser-vative analog components such as continuous time filters and devices thatuse these as sub components (examples are phase locked loops, powertrainof a voltage regulator, current sense circuitry across an inductor etc.) it isimportant to model these using Kirchoff’s Current/Voltage laws. In suchsituations, once might resort to capturing the circuit in a schematic andnetlisting the same using the Verilog-A libraries built into Virtuosso or justusing Verilog-A constructs and writing out the circuit description. Eitherway IRUN will simulate the analog behavior with the digital block effectively.While this methodology is a viable option, a SystemC approach (mentionedhere) offers an alternative and is a good candidate for ESL level simulation.

In what follows we describe a State Space approace to modeling the con-servative parts of the analog functionality and discuss the benefits of thisprocedure. We then discuss several examples that were very successfullysimulated using this approach and also outline the caveats.

3 Solution of a Set of Linear Differential Equationsin State Space

The State Space Method has been used extensively in modern control theoryto model complex feedback systems. The idea is to frame the control pro-cess in terms a set of linear time invariant differential equations that governthe time evolution of the state variables. The details of this methodology isextensively discussed in texts elsewhere[1], [2] and we only mention the keyideas here.

We start with a brief description of how to solve a set of linear timeinvariant differential equations in state space. Consider the following set of

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coupled first order differential equations:

x′ = Ax + Bu (3.1)

y = Cx + Du (3.2)

where x’ is the first order derivative vector of the state variable vectorx, y is the output vector, u is the input vector A is the state transition ma-trix, B is the input matrix, C is the output matrix and D is the feedthroughmatrix. The equation of interest for our purpose here is eqn (3.1).

What this equation tells us is that given a set of state variables x, amodel of the conservative system that relates the state variables to theirrate of change A, a model that ties the rate change to the applied input Band a set of stimulus or inputs u, the rate of change x’ can be determined.However one must note that there are restrictions on when this equationapplies and these are detailed in references[3] to which the reader is encour-aged to refer to. We merely mention some of these these as bullet points:

• The system being modeled is linear or at least has a small signal modelthat is linear. In this situation the input is applied such that systemremains in the small signall region.

• The system is asympototically stable, in that if the applied input isremoved (input is made to go to 0), the state-vector will return to theorigin of the state-space, x=0.

• A bounded(finite

)input will always produce a bounded output. This

is saying that a finite input will produce an output that may have apeak(overshoot) and a valley(undershoot) but will eventually settle toa finite value.

There are standard practices to determining whether the system underconsideration

(the state space equation set

)is stable or not. Two common

approaches are to use a Nyquist Plot[2][3] and The Root Locus Method[2][3].Given that we have an equation for the slope of the state variable and thatthe system has been determined to be stable for the range of input responseswe are attempting to simulate, methods based on The Taylor Series expan-sion allow us do determine the transient behavior of the state variables. Suchmethods include The Euler Forward, The Euler Backward, various orders ofthe Runge Kutta Method etc.[4]. Each of these methods have their meritsin terms of speed and accuracy. In this paper we explain how the RungeKutta Order 4

(RK4 henceforth

)might be used to effectively simulate a

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state space model. We choose the RK4 method over the Euler Methods dueto the higher accuracy of it’s results.

By definition of the differential we have the following equation for thenext state of the state variable-

xn+1 = xn + f(x′,xn,∆t) (3.3)

whereby xn+1 is the next value of the state variable, xn is its presentvalue, f

(xn+1,xn,Δt,

)is some function that determines the increment /

decrement to the state variable based on the state variables rate of change,it’s present value and the simulation time step Δt. In it’s simplest form(first term in the Taylor Series

), this fuction is the rate of change of the

state variable itself and in this form the next state equation computes thenext value of the state variable using the Euler Forward method[4]. For theRK4 method we use the following iterative approach to compute the timeincrement value-

k1 = ∆tf(tn, xn) (3.4)

k2 = ∆tf(tn + ∆t/2, xn + k1/2) (3.5)

k3 = ∆tf(tn + ∆t/2, xn + k2/2) (3.6)

k4 = ∆tf(tn + ∆t, xn + k3) (3.7)

xn+1 = xn +1

6(k1 + k2 + k3 + k4) (3.8)

The choice of the RK4 over the Euler Method might appear to be a lit-tle more compute intensive

(note that the Euler Method is implemented by

dropping k2, k3, k4 and setting the multiplying term in(8)

to 1 instead of1/6

).However on careful observation one sees that the terms ki (i=1,2,3,4)

can be unrolled a priori instead of solving iteratively(in steps). We explainthe application of these methods using the following two examples.

3.1 Simulating a Single Phase Digital Voltage Regulator(Buck

)The functional/performance verification of a digital voltage regulator usingthe SSS is a good example of how this methodology might be used for AMSsimulations. Digital voltage regulators are a reletively new technology. The

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user sends voltage set point commands to the device and in turn the regu-lator regulates to the set point voltage. We refer to Figure 1 to explain howthe simulation environment is set up.

Pulse Width Modulator

PID Contorller

Vo

ltageSeq

uen

cer

LRL

Rc

C

ILoad

PWM_IN

VIN

VOUT, IOUT

ADC

Analog Front End

TestControl

System Verilog

Verilog

System C

SystemC – State Space Solver

Driver & FET

Figure 1 – Digital Voltage Regulator, State Space Solver based Testbench

There are 3 main domains in the simulation environment. These are:

• The System Verilog domain - This is the test control and logging do-main. The Test Control block is able to send voltage set point com-mand to the DUT

(the voltage regulator

)and set output loads in the

SSS.

• The SystemC domain - There are 2 sub domains in the SystemC do-main. These are the Analog Behavioral block that includes the AnalogFront End

(AFE

)and the Analog to Digital Converter

(ADC

). The

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AFE takes the digital voltage output of the Voltage Sequencer in theDUT and converts it to a real valued voltage. This voltage is com-pared with the voltage from the SSS and the difference is digitized bythe ADC.The ADC thereafter passes the digitized voltage difference(error voltage

)to the DUT. The other SystemC domain is the SSS

itself. We will discuss the SSS shortly.

• The Verilog domain - This domain contains the digital voltage regu-lator. The voltage regulator consists of a PID Controller

(PID

)that

drives the Pulse Width Modulator(PWM

). The PID basically in-

structs the PWM how to create the output pulses so as to best achievethe desired set point voltage with minimal overshoot and undershootdue to output load changes and dynamic voltage change requests fromthe test bench. The Voltage Sequencer is responsible for ramping theoutput voltage up or down based on voltage change request receivedfrom the Test Control block.

The SystemC and the Verilog/SystemVerilog are tied together using theSystem Verilog DPI interface. Function calls between the two domains aresynchronized via call backs implemented in the testbench.

We now discuss how the SSS is implemented. Using Kirchoff’s Voltage(KVL

)and Kirchoff’s Current

(KCL

)we write the set of equations that models the

passive output filter(the inductor -L, the inductor DCR -RL, the capacitor

-C, the ESR -Rc), the input voltage source

(the Driver and FET -VIN

)and

the output load(the current source -Iload

). On solving the network equa-

tions we have(in matrix equation form as depicted in

(3.1

)):

[i′Lv′C

]=

[−(RL + RC

)/L −1/L

1/C 0

] [iL,nvC,n

]+

[RC/L 1/L−1/C 0

] [Iload,nVin,n

](3.9)

Here the state variables are the current through the inductor iL andthe voltage across the capacitor vC. The subscript n is used to denote it’sinsantaneous value. On comparing this equation set to

(3.1

)it is clear that

the state transition matrix and the input matrix are constant. Further Vin,n

and Iload,n are the instantaneous input voltage and load current. At thisstage we have established the required “Rate of Change” equations for thestate variables. It remains to now set up the next state equations for thecurrent through the inductor and the voltage across the capacitor. Notethat the state transition matrix A is the matrix that scales the currentstate vector whose elements are the current through the inductor and thevoltage across teh capacitor. The input matrix B scales the input vectorthat consists of the applied input voltage and the output load. In order to

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setup the next step equations for vC and iL, we need to create the next stepfunction from the A and B matrices. As mentioned we use the RK4 methodfor this next step function. We have developed a SystemC solver libraryand one of the functions; solver rk4

()takes as it’s argument the A matrix,

the B matrix, the symbol for the voltage across the capacitor, the symbolfor the current through the inductor, the symbol for the input voltage, thesymbol for the load current and the simulation time step and creates a sumof product equation that models the next state equations for the voltageacross the capacitor and the current through the inductor. More generallythis function takes as its arguments the A matrix, the B matrix, the statevariable vector, the input variable vector and the simulation time step andoutputs the next state variable vector. The equations that are created fromthis function for our particular case look like this:

vC,n+1 = M1,1vC,n + M1,2iL,n + N1,1Vin,n + N1,2Iload,n (3.10)

iL,n+1 = M2,1vC,n + M2,2iL,n + N2,1Vin,n + N2,2Iload,n (3.11)

Here Mi,j are the coefficients generated by solver rk4()

function the forgiven values of the inductance L, the capacitance C, the inductor DCR RL

and the capacitor ESR RC. Note here the computational effeciency that wasachieved using the solver rk4

()function to remove the iterative form of the

RK4 method. Each next state variable now has a sum of product form thatis effectively used to determine its transient behavior based on the appliedinputs. We illustrate in Figure 2 the the ramping of the output voltage ofthe voltage regulator

(DUT

)based on the Test Control sending a request to

ramp to 1.00 Volts.

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Voltage across Capacitor

Current through Inductor Sequencer digitally ramping the

set point voltage to 1.0 volts

Figure 2 – Simulation of the Voltage Regulator

3.2 Simulating a Digital Phase Locked Loop

The SSS methodology was successfully used to simulate the Analog LoopFilter and the VCO combination in a Digital Phase Locked Loop. Figure 3below shows the various domains in the simulation environment:

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Phase DetectorVCO

(Voltage ControlledOscillator)

Analog Loop Filter

Divider

Input Reference

Clock

Local Oscillator

Out

SystemC -State Space Solver

Figure 3 Simulating a Digital Phase Lock Loop Using a State Space Solver

System Verilog Domain

The transfer function of the combined analog loop filter and the voltagecontrolled oscillator combination was converted from the frequency doaminto the time domain using the state space approach similar to the exampleabove. The solver rk4

()function was used to take the circuit description

and generate the generate equation much like(3.10

)and

(3.11

). Figure 4

shows how the local oscillator output voltage reacts to a frequency drift inthe input reference frequency.

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Local Osc and Reference

Locked

Reference StartsDrifting

Local Osc and Reference

Locked

4 Conclusion

We conclude that the SSS methodology can successfully be used to modelpassive analog circuitry using the SystemC libraries. The simulation speed isconsiderably faster that using using a traditional mixed mode (VerilogA/Spice+ Verilog) approach. However the user has to do some initial legwork herein that the circuit description (The A and B Matrix) have to be manuallydetermined. Also the simulation time step needs to be pre-determined andseveral ways exist for doing this(will be discussed in a future paper). Notethat the next state equations for the state variables have been reduced to asum of products form and this makes the set of equations amicable for solvingon a highly parallel processor. One such effort being carried out internally isto have the solver run on a GPU based environment[5]. But overall the use

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of this methodology using IRUN has proved to be quite efficient. A followon version of this paper intends to detail the actual mechanics of the solverlibrary, the system Verilog DPI that connects the SystemC engine to thetestbench and more examples of the application of this practice in solvingcomplex mixed siganl simualtions using only a all digital simulator(ncsim).

References

[1] Derek Rowell Time-Domain Solution of LTI State Equations 2.14 Anal-ysis and Design of Feedback Control Systems, MIT, October 2002

[2] Modern Control Engineering Katshuiko Ogata, Fifth Edition, PrenticeHall, 2010

[3] Control Theory Fundamentals Richard Poley, Second Edition, ControlTheory Seminars, March 2014

[4] Applied Numerical Methods, with MATLAB, for Engineers and Scien-tists Steven Capra, Third Edition, McGraw Hill, 2012

[5] A CUDA based State Space Solver Rajat Mitra, Internal Document, 2014

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