SoCSoC DesignDesign

LectureLecture 22: Design Methodology and: Design Methodology andLecture Lecture 22: Design Methodology and : Design Methodology and StrategiesStrategies

Shaahin HessabiShaahin HessabiDepartment of Computer EngineeringDepartment of Computer Engineering

Sharif University of TechnologySharif University of Technology

Design ChallengeDesign Challenge

System complexity is increasingSystem complexity is increasingP d t lif ti i d iP d t lif ti i d iProduct lifetime is decreasingProduct lifetime is decreasing⇒⇒ Design efficiency is essentialDesign efficiency is essential

New design methods are necessaryNew design methods are necessary⇒⇒ New design methods are necessaryNew design methods are necessary⇒⇒ Higher abstraction levels are introducedHigher abstraction levels are introduced⇒⇒ CAD tools able to handle large amounts of data are neededCAD tools able to handle large amounts of data are neededgg

Sharif University of Technology 2SoC: Design Methodology

Design MethodologyDesign Methodologyg gyg gy

1.1. Budget ($, speed, area, power, Budget ($, speed, area, power, schedule, risk)schedule, risk)

2.2. LowLow--level building blocks, highlevel building blocks, high--l l hit tl l hit tlevel architecturelevel architecture

3.3. SpecificationSpecificationB h i l d i ifi tiB h i l d i ifi ti4.4. Behavioral design, verificationBehavioral design, verification

5.5. Logic design, verificationLogic design, verificationL ifi iL ifi i6.6. Layout, verificationLayout, verification

Sharif University of Technology 3SoC: Design Methodology

Modern Digital Systems EngineeringModern Digital Systems Engineering

Sharif University of Technology 4SoC: Design Methodology

Coping with ComplexityCoping with Complexityp g p yp g p y

How to design complex systems?How to design complex systems?1.1. Design Partitioning, AbstractionDesign Partitioning, Abstraction2.2. Structured DesignStructured Design

Design and verificationDesign and verificationdominate escalatingdominate escalatingggproject costsproject costs

Sharif University of Technology 5SoC: Design Methodology

Abstraction LevelsAbstraction Levels

ArchitectureArchitecture: User’s perspective, what does it do?: User’s perspective, what does it do?I t ti t i tI t ti t i tInstruction set, registersInstruction set, registersMIPS, xMIPS, x8686, Alpha, PIC, ARM, …, Alpha, PIC, ARM, …

MicroarchitectureMicroarchitecture (RTL)(RTL)MicroarchitectureMicroarchitecture (RTL)(RTL)Single cycle, multiSingle cycle, multi--cycle, pipelined, superscalar?cycle, pipelined, superscalar?

LogicLogic: how are functional blocks constructed: how are functional blocks constructedLogicLogic: how are functional blocks constructed: how are functional blocks constructedRipple carry, carry lookRipple carry, carry look--ahead, carry select addersahead, carry select adders

CircuitCircuit: how are transistors used: how are transistors usedComplementary CMOS, pass transistors, dominoComplementary CMOS, pass transistors, domino

PhysicalPhysical: chip layout: chip layoutDatapathsDatapaths, memories, random logic, memories, random logic

Sharif University of Technology 6SoC: Design Methodology

Abstraction LevelsAbstraction LevelsAbstraction LevelsAbstraction Levels

Design domains are divided in several abstraction levels:Design domains are divided in several abstraction levels:

Sharif University of Technology 7SoC: Design Methodology

Abstraction: System LevelAbstraction: System Levelyy

Highest abstraction levelHighest abstraction levelDescription with HDLs or graphical block diagramsDescription with HDLs or graphical block diagrams

Sharif University of Technology 8SoC: Design Methodology

Abstraction: Abstraction: MicroarchitectureMicroarchitecture LevelLevel

Register transfer system is a pure sequential machineRegister transfer system is a pure sequential machineR i t t f i l t ifi ti h tR i t t f i l t ifi ti h tRegister transfer is a complete specification on what a Register transfer is a complete specification on what a chip will do on every cyclechip will do on every cycleMicroarchitectureMicroarchitecture components:components:MicroarchitectureMicroarchitecture components:components:

FFunctionalunctional unitsunitsoo adder, multiplier, adder, multiplier,

comparator, ALU, etc.comparator, ALU, etc.MMemoryemory elementselementsoo latch, FF, register, registerlatch, FF, register, register--

fil RAM ROMfil RAM ROMfile, RAM, ROM ...file, RAM, ROM ...IInterconnectionnterconnection unitsunits

b lti lb lti lSharif University of Technology 9SoC: Design Methodology

oo bus, multiplexerbus, multiplexer

Abstraction: Logic LevelAbstraction: Logic Levelgg

Circuit description on a quite low abstraction levelCircuit description on a quite low abstraction levelToday only used to design optimized functional blocksToday only used to design optimized functional blocks

Sharif University of Technology 10SoC: Design Methodology

Abstraction: Circuit LevelAbstraction: Circuit Level

Lowest abstraction levelLowest abstraction levelTransistor schematic or maskTransistor schematic or mask--layoutlayoutComparable to machine code in computer scienceComparable to machine code in computer science

Sharif University of Technology 11SoC: Design Methodology

Abstraction DomainsAbstraction Domains

Designs can be performed in Designs can be performed in 3 3 abstraction domains:abstraction domains:B h i l d iB h i l d iBehavioral domainBehavioral domainStructural domainStructural domainPhysical domainPhysical domainPhysical domainPhysical domain

Each domain gives different freedoms to the designerEach domain gives different freedoms to the designerParallel or serial algorithmsParallel or serial algorithmsggLogic technology and bitLogic technology and bit--slicesliceFullFull--custom and macrocustom and macro--cells ...cells ...

Sharif University of Technology 12SoC: Design Methodology

Abstraction Domains: YAbstraction Domains: Y--ChartChart

Sharif University of Technology 13SoC: Design Methodology

Behavioral DomainBehavioral Domain

Abstract function: Description and verification of first ideasDescription and verification of first ideasFunction, and not implementation, is askedFunction, and not implementation, is askedModeling with general purpose languagesModeling with general purpose languages

modulamodula--22, , pascalpascal, c, , c, c++c++, lisp, ..., lisp, ...matlabmatlab, , mathematicamathematica, ..., ...hdlhdl erilogerilog hdlhdl cathedralcathedralvhdlvhdl, , verilogverilog--hdlhdl, cathedral, ..., cathedral, ...

graphic languages as graphic languages as veevee, ..., ...

T f ti tT f ti tTransformation to Transformation to structural domain: structural domain: synthesissynthesissynthesissynthesis

Sharif University of Technology 14SoC: Design Methodology

Structural DomainStructural Domain

Interconnection of parts: description and verification of a Interconnection of parts: description and verification of a solutionsolutionsolutionsolutionRestrictions like delay, signal strength, etc.Restrictions like delay, signal strength, etc.Modeling stylesModeling stylesModeling stylesModeling styles

vhdlvhdl, , verilogverilog--hdlhdl,,schematicschematic

Transformation to physical Transformation to physical domain: logic minimizationdomain: logic minimizationdomain: logic minimization, domain: logic minimization, place and route toolsplace and route tools

Sharif University of Technology 15SoC: Design Methodology

Physical DomainPhysical Domainyy

Physical objects with size and positions: description and description and verification of physical implementationverification of physical implementationTechnology specific implementationTechnology specific implementationFloorplanFloorplan, mask, mask--layout, packaginglayout, packagingDescription formatsDescription formats

cifcif, gds, gds22stick diagrams, symbolic layoutstick diagrams, symbolic layout

Sharif University of Technology 16SoC: Design Methodology

Design StrategiesDesign Strategiesg gg g

The goal is a fast as possible The goal is a fast as possible transfer of an idea to a chiptransfer of an idea to a chipDescriptions in the Descriptions in the 3 3 abstraction abstraction d id idomainsdomainsStructured strategies used:Structured strategies used:

HierarchHierarchHierarchyHierarchyRegularityRegularityModularityModularityModularityModularityLocalityLocality

Sharif University of Technology 17SoC: Design Methodology

Design Strategies: HierarchyDesign Strategies: Hierarchyg g yg g y

HierarchyHierarchy: divide and conquer: divide and conquerRecursively divide system into modulesRecursively divide system into modulesDividing in modules, subDividing in modules, sub--modules until complexity of modules until complexity of subsub--modules is comprehensiblemodules is comprehensiblesubsub modules is comprehensiblemodules is comprehensibleComparison to software engineering: split programs in Comparison to software engineering: split programs in modules, procedures, subroutines.modules, procedures, subroutines.

Sharif University of Technology 18SoC: Design Methodology

Design Strategies: RegularityDesign Strategies: Regularityg g g yg g g y

Regularity: reuse modules wherever Regularity: reuse modules wherever possible (similar subpossible (similar sub--modules)modules)Goal: reduction of complexityGoal: reduction of complexityIdea: divide in similar building blocksIdea: divide in similar building blocks

identical blocks, subidentical blocks, sub--blocks, cells, transistor sizesblocks, cells, transistor sizes11 dimentionaldimentional arra sarra s bitbit slice techniq eslice techniq e11--dimentionaldimentional arraysarrays: bit: bit--slice techniqueslice technique22--dimentional arrays: systolic arraysdimentional arrays: systolic arrays

Sharif University of Technology 19SoC: Design Methodology

Design Strategies: ModularityDesign Strategies: Modularityg g yg g y

Define subDefine sub--modules unambiguously with wellmodules unambiguously with well--defined defined interfacesinterfaces

Allows modules to be treated as black boxesAllows modules to be treated as black boxes

Diff t d l h ld t i fl h thDiff t d l h ld t i fl h thDifferent modules should not influence each otherDifferent modules should not influence each othersubsub--modules with well formed interfaces:modules with well formed interfaces:

do not se transmission gatesdo not se transmission gatesdo not use transmission gatesdo not use transmission gateswell defined signal types and strengthswell defined signal types and strengthswell defined interconnection widths, etc.well defined interconnection widths, etc.well defined interconnection widths, etc.well defined interconnection widths, etc.

Sharif University of Technology 20SoC: Design Methodology

Design Strategies: LocalityDesign Strategies: Localityg g yg g y

Max local connections, keeping critical paths Max local connections, keeping critical paths ithi d l b d iithi d l b d iwithin module boundarieswithin module boundaries

Physical and temporalPhysical and temporalTi l lit l d t h d i ( l lTi l lit l d t h d i ( l lTime locality leads to synchronous designs (compare local Time locality leads to synchronous designs (compare local variables in software engineering)variables in software engineering)

Idea: reduction of complexity due to information hidingIdea: reduction of complexity due to information hidingIdea: reduction of complexity due to information hidingIdea: reduction of complexity due to information hidingFew global variablesFew global variables

reduction of interreduction of inter--module influencesmodule influencesreduction of global wiringreduction of global wiring

Sharif University of Technology 21SoC: Design Methodology

Automatic SynthesisAutomatic Synthesisyy

Automatic synthesis: transformation of a design from Automatic synthesis: transformation of a design from behavioral to structural domainbehavioral to structural domainSiliconSilicon compilation: transformation compilation: transformation fromfrom behavioral to behavioral to h i l d ih i l d iphysical domainphysical domain

SSynthesisynthesis is a design is a design process and not a only aprocess and not a only aprocess and not a only a process and not a only a coding as in software coding as in software engineeringengineeringengineeringengineeringSynthesis steps:Synthesis steps:

AllocationAllocationAllocationAllocationSchedulingSchedulingBBindinginding

Sharif University of Technology 22SoC: Design Methodology

BBindinginding

AllocationAllocation

Allocation defines the necessary resourcesAllocation defines the necessary resourcesClocking strategy pipelining memory structure etc haveClocking strategy pipelining memory structure etc haveClocking strategy, pipelining, memory structure, etc. have Clocking strategy, pipelining, memory structure, etc. have to be definedto be definedManual allocation reduces the search space of designManual allocation reduces the search space of designManual allocation reduces the search space of design Manual allocation reduces the search space of design solutionssolutions

TTraderade off between chipoff between chipTTraderade--off between chipoff between chip--area and performancearea and performance

Parallel implementations ofParallel implementations ofParallel implementations of Parallel implementations of designs have high designs have high throughput, but consume throughput, but consume large areaslarge areaslarge areaslarge areas

Sharif University of Technology 23SoC: Design Methodology

Allocation: RTL ExampleAllocation: RTL Examplepp

x = a + b;x = a + b;y = a * c;y = a * c;z = x + d;z = x + d;x = y x = y -- d;d;x = x + c;x = x + c;

Allocation: Allocation: 1 1 adder, adder, 1 1 multiplier, multiplier, 1 1 substractorsubstractor

Sharif University of Technology 24SoC: Design Methodology

SchedulingSchedulinggg

Scheduling defines the operation sequencingScheduling defines the operation sequencingOperations are bound to clock cyclesOperations are bound to clock cyclesScheduling principles:Scheduling principles:

R li it d i t fR li it d i t f

Operations are bound to clock cyclesOperations are bound to clock cycles

Resource limited: given a set of Resource limited: given a set of resources, solutions for a resources, solutions for a minimal execution time has to be minimal execution time has to be foundfoundTimeTime--limited: given a total limited: given a total execution time, a minimal set ofexecution time, a minimal set ofexecution time, a minimal set of execution time, a minimal set of resources has to be foundresources has to be found

Directed acyclic graphs can be Directed acyclic graphs can be usedused

Sharif University of Technology 25SoC: Design Methodology

BindingBindinggg

Binding phase: operations and memory accesses within Binding phase: operations and memory accesses within the clock cycles are bound to the hardware resourcesthe clock cycles are bound to the hardware resourcesthe clock cycles are bound to the hardware resourcesthe clock cycles are bound to the hardware resourcesResources can be reused in different clock cyclesResources can be reused in different clock cyclesBinding steps:Binding steps:Binding steps:Binding steps:

variables are bound to memory elementsvariables are bound to memory elementsoperations are bound to functional blocksoperations are bound to functional blocksppinterconnection elements are bound for data transfers (buses, interconnection elements are bound for data transfers (buses, multiplexers)multiplexers)

Sharif University of Technology 26SoC: Design Methodology

Binding: ExampleBinding: Exampleg pg p

Example:Example:temporary variables xtemporary variables x11 and xand x22 are not used simultaneouslyare not used simultaneously

Sharif University of Technology 27SoC: Design Methodology