© IMEC 1999 1

© imec 1999

SoC++Design Technology at

IMEC/DESICS

Diederik Verkest

http://www.imec.be/http://www.imec.be/vsdm/

© imec 1999

IMEC history

,Personnel > 820 people

,Close worldwide interactionwith industry and with widerange of universities andresearch institutes

,Founded 1984

,Largest independentmicroelectronicsresearch center in Europe

,Located in Leuven, Belgium

,Annual research budget 78 M US$

© IMEC 1999 2

© imec 1999

IMEC activities,21 415 m2 facilities

- 3 600 m2 ultra cleanprocessing area

- 6 200 m2 computer room & utilities

- 10 400 m2 offices & supporting laboratories

- 1 215 m2 training facilities

,R & D activities- Micro-electronics design and

processing technologies

- Balance between long-term and short-to medium-term research

- Contract research including industrialresidents, industrial affiliation program,transfer of qualified technologies

© imec 1999

IMEC measures of success,Scientific impact,Cooperation with universities in complementary

fields,International network of cooperation with most of

the important industrial performers in our field,Portfolio of protected intellectual property,Transfer of technologies to existing companies,Creation of new spin-off companies,Attracting foreign investments in the field of

microelectronics and ICT,Turn-over of well trained researchers to industry

© IMEC 1999 3

© imec 1999

IMEC activity areas

,DESICS: DESign technology forintegrated Information andCommunication Systems

,Semiconductor Process Technology

,Silicon Technology and DeviceIntegration

,Microsystems, Components, Packaging

,IC design training

,Associated University Laboratories

© imec 1999

DESICS activities

+System-level design technology isinherently strongly linked to anapplication domain: communicationand multimedia applications,Digital Broadband Transceivers,Wireless Systems,Multimedia Image Compression

+Total of appr. 120 people (incl.industrial residents, visitingresearchers, PhD students, ...)

© IMEC 1999 4

© imec 1999

Intelligent Home

155Mb/s WLAN 5GHz

<1 Watt10Gop/s

MPEG 4>100 Gop/s 5 Gtr/s 10 Watt

WWW

IntelligentAccess

Terminal

© imec 1999

World’s first 155MB/sec WLAN

wired backbone

Base station155Mb/smulti-user rxantenna diversity

Multi-path fading

,Orthogonal Frequency Division Multiplexing (OFDM) ,Turbo-coding,Spatial Division Multiple Access (SDMA),Hiperlan-2/ IEEE 802.11 compatible

© IMEC 1999 5

© imec 1999

Single-package transceiver

BiCMOS:RF

circuitry

MCM:interconnect

inductors,capacitors,

resistors, filters,baluns

CMOS: IFand

digitalcircuitry

MEMS:switches,varactor,

resonators

© imec 1999

Multimedia MPEG-4 (member sctee)

Live from FZ-TV

,Diversity: 3D, Facial and Body Animation, Video,Scalability: time, space, SNR,Interactivity: behavior = f (input bits, user)

© IMEC 1999 6

© imec 1999

Design Technology Research,Advances in processing technology

,Integration of PCB on single die: SoC

,Design productivity gap

250

200

150

100

50

1995 1998 2001 2004 2007

[ 106 T/chip ]

[ SIA roadmap ]

© imec 1999

SoC or …---… (S.O.S.)

+Design productivity gap grows !,Complexity increase 40 % per year

,Design productivity increase 15 %per year

250

200

150

100

50

1995 1998 2001 2004 2007

[ 106 T/chip ]

[ SIA roadmap ]

© IMEC 1999 7

© imec 1999

Design productivity gap

+System-level design,Concept to VHDL/C

,Algorithms and architecturesmeeting performance, power,area constraints

+Physical design,VHDL/C to silicon

,Timing closure (Monterey, Magma,Synopsys, Cadence, Avant! …)

© imec 1999

System-level design

+Problems,1 line of VHDL produces 40 transistors

,10.106 tr/chip = 250,000 lines VHDL code

,Hardware AND (embedded) software

,IP re-use

+Caused by,Abstraction level (VHDL ~ assembly)

,Discrepancy design conceptsand HDL semantics

© IMEC 1999 8

© imec 1999

Re-use

Design concepts discrepancy

+(V)HDL,Signals

,Events

,Processes

,...

+HW designer,Signals

,Clocks

,FSMs

,Data-paths

,Instructions

,I/F protocols

,...

How do I ?

Coding

© imec 1999

Design process+Observations,Design is often incremental

- Generations of the same product, re-use

,Heterogeneous design environment- Difficult to navigate and explore design space

,Informal system specifications- Impossible to back-track on system decisions

- Ambiguous

+Solution,SoC++ object-oriented system design

© IMEC 1999 9

© imec 1999

System-level design

+Solution,Paradigm shift

- Higher abstraction level

- Object-oriented design

- Re-use of HW (HDL) andSW (C/C++) compilers

- Behavioral IP re-use

- Incremental refinementto RT-HDL (HW) andC/C++ (SW)

© imec 1999

SoC++ object-oriented design

+Eliminate conceptual gap betweendesign concepts and language concepts,Design productivity increase

,Enables behavioral re-use

+Design concepts = objects,Set of C++ object libraries implementing

essential design concepts

,Designers write down system-on-chipspecification directly using these objects

© IMEC 1999 10

© imec 1999

SoC++ incremental refinement+ Introduce implementation

detail in the sameC++ framework

,Floating-point tofixed-point

,Data-flow to detailedcycle timing

,Generation ofregister-transferHDL code

922 lines HL-C++

4,426 lines RT C++

21,798 lines RT VHDL

154,952 lines gate level VHDL

80,00

0 gate

s

© imec 1999

SoC++ programming

RAMRAM

ROM

MMU

customlogic

DSP

ROM microprocessor

Algorithms Data Structures+ + Architectures

ARM

IP1 IP2

RAM ROM

mSoC design =object-oriented programming activity

© IMEC 1999 11

© imec 1999

SoC++ programming env.

,C++ object libraries- Build object hierarchy on execution

,C++ compiler- Produces “executable specification” starting from

any (mixed) abstraction level SoC description

,Execute specification for- Analysis: estimate performance, power, area, …

- Verification: simulate to check functional correctness

- Exploration: interactive refinement

- Generation of low-level HDL/C code

© imec 1999

TaskTask

Task

Systempeople

C

ASM

Softwarepeople

vhdl

verilog

Hardwarepeople

ExecutableExecutablespecificationsspecifications

Executable system spec.

,Executable “feasibility” phase

,Refinement of executable spec.

© IMEC 1999 12

© imec 1999

Historical perspective

Customlayout

19991992198519781971

Design technogy

always lags

processingtechnology

Symboliclayout

Schematicscapture

HDL baseddesign

C/C++ baseddesign

© imec 1999

AFE ADSLDSP

ATMproc.

PC/Windows

MPEG-4co-processor

PC I/F

Micro-processor

Mixed-SignalMixed-SignalDesignDesign

TechnologyTechnology

FASTFAST ATOMIUMATOMIUM

A SoC of the future

OCAPIOCAPI MatisseMatisseExecutableExecutablesystem spec.system spec.

TIPSYTIPSY

© IMEC 1999 13

© imec 1999

AFE ADSLDSP

ATMproc.

PC/Windows

MPEG-4co-processor

PC I/F

Micro-processor

A SoC of the future

ExecutableExecutablesystem spec.system spec.

TIPSYTIPSY

© imec 1999

Executable system spec.

+Requirements,High simulation speed,Only capture relevant structure/function/timing detail

- Maybe different from block to block

,Performance estimation- Concurrency & Time

+TIPSY fast functional verification with timing,C++ class library,Multiple threads of execution,Simulated time for each thread,Guaranteed time consistency between threads

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© imec 1999

OSth

read

thre

adbloc

k

bloc

kbl

ock

symbol rate 4kHz Õ delay(0.25)

Hardware(data-flow)

time-outspecificationÕ delay(200)

context switchÕ delay(2)

Software(“as is”)

AFE ADSLDSP

ATMproc.

PC/Windows

MPEG-4co-processor

PC I/F

Micro-processor/OS

TIPSY - results for ADSL

Abstraction

© imec 1999

EmbeddedControl SW

Digital HWDatapath

Digital HWController

HW

blo

ck

HW block

OCAPI

HW

blo

ck

Qu

eue

Qu

eue Custom

InstructionSet

SimulatorSW

th

read

OSAPI

SW

th

read

HW

wra

p

1. Untimed (reactive)2. Profiling delays3. RTOS model

1. Symbol rate (4 kHz)2. Sample rate (2 Mhz)

1. Instruction rate (8mhz)

COSIM library (message passing primitives)

TIPSY library (concurrency and time)

UNIX OS

TIPSY multi-threading & time

,Fast timed co-simulation of HW and SW

,10 seconds initialization ñ 30 minutes CPU

symbol rate 4kHz Õ delay(0.25)

time-outspecificationÕ delay(200)

context switchÕ delay(2)

© IMEC 1999 15

© imec 1999

AFE ADSLDSP

ATMproc.

PC/Windows

MPEG-4co-processor

PC I/F

Micro-processor

A SoC of the future

OCAPIOCAPI

,Digital signal processing applications

© imec 1999

ComputationalModelData Type

Algorithm

FixedPoint RTArchitecture

FloatingPoint

Dataflow

OCAPI incremental refinement

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© imec 1999

OCAPI incremental refinement

C++ Un-timedFloating-Point

C++ TimedFixed-Point

ControllerVHDL

Data-pathDSFG

Data-pathgates

Controllergates

HDL systemimplementation

Codegeneration

SystemLinkage

IncrementalRefinement

TraditionalSynthesis

© imec 1999

OCAPI Design Experience

+ 75 Kgate DECT modem+ VLIW architecture

+ 22 data paths+ 18 MW (algor. -> gates)

+ 80 Kgate Cable Modem+ DF architecture

+ 26 FSMD+ 36 hrs (? in C++ -> gates)

Beaufort

Also: MPEG4 Wavelet Compressor, xDSL modem, OFDMmodem, ...

© IMEC 1999 17

© imec 1999

AFE ADSLDSP

ATMproc.

PC/Windows

MPEG-4co-processor

PC I/F

Micro-processor

MatisseMatisse

A SoC of the future

,Network protocol processing applications- ATM, Internet Protocol (IP), TCP/IP, ...

© imec 1999

Matisse incremental refinement

+Application domain,Large amount of data

,Dynamically allocated

,Real-time constraints

+Abstract Data Type refinement,Look-up tables, buffers, sets of timers

+Virtual Memory Management,Manage use of available memory

NetworkProtocol

Processing

ATM, IP

© IMEC 1999 18

© imec 1999

ATM_cell * Data_In;Table_with_one_key * Routing_Table;

Routing_Table = new Table_with_one_key();Data_In = new ATM_cell();

if ( Routing_Table->Lookup(Data_In) ) ...

Array (AR)

dat

a

dat

a

dat

a

dat

a

Array * Routing_Table;

Array ();

Linked List (LL)

keydata

keydata

keydata

keydata

Linked_List * Routing_Table;

Linked_List ();

keydata

keydata

keydata

Binary Tree (BT)

Binary_Tree * Routing_Table;

Binary_Tree ();

Matisse: ADT refinement

10 4

10 3

10 2

10 1

10 0

Impl. alternatives

Power function Area function

10 4

10 3

10 2

10 1

10 0

© imec 1999

Matisse: ADT results

,Library for incremental refinement- 28,355 lines of C++ code

- Simulation/profiling

- Implementation

,ATM multiplexer- previous

› 327 mW, 601 mm2

- new› 110 mW, 135 mm2

+ + + + + + + + + + + + + ++

+

+

+

oo o o o o o o o o o o o o o o

o

o

# bits in top-layer key

Po

wer

est

imat

e(a

rea

* ac

cess

es)

LL-LL

LL

PA

PA-AR

0 2 4 6 8 10 12 14 16 180

1

2

3

4

5

6

7

8

9

X 107

© IMEC 1999 19

© imec 1999

RAM

RAM

RAM

Matisse: memory management

Dynamic Memory Mgmt

Task Concurrency Mgmt

Physical Memory Mgmt

Address Optimization

SWdesignflow

HWdesignflow

Concurrent OO spec

RAM

MMU(addr.)

ASIC

data in

ISRtime

data outrouting reply

RoutingRecord

PacketRecord

FIFO

out

IN622 Mb/s

OUT622 Mb/s

OUT622 Mb/s

53 cycles, 200 accesses

ATO

MIU

MA

CR

OP

OL

IS

© imec 1999

MATISSE - results

,Systematic exploration of dynamic memorymanagement- Determine optimal power, area trade-off

- Under guidance of designer

,Two steps- ADT refinement: determine optimal data-structures

for abstract data types (storage + services)

- VMM: * and & become addresses in static arrays

,Applied to SPP, F4, F5, ATMP, …

© IMEC 1999 20

© imec 1999

AFE ADSLDSP

ATMproc.

PC/Windows

MPEG-4co-processor

PC I/F

Micro-processor ATOMIUMATOMIUM

A SoC of the future

,Multi-dimensional signal processing- Memory = performance bottleneck- Optimization of data transfers and data storage

© imec 1999

ATOMIUM

µProc:60%/year.

CPU

DRAM:7%/yearDRAM

1

10

100

1000

1980 1985 1990 1995 2000

Performance

Time

“Moore’s Law”

Processor-MemoryPerformance Gap:(grows 50% / year)

,Memory = performance bottleneck

© IMEC 1999 21

© imec 1999

ATOMIUM exploration

+Memory = performance bottleneck,P(off-chip mem. access) = 30*P(arithmetic)

,P(on-chip mem) = 40-60% P(chip)

+Systematic exploration for reduction,Data storage cost

,Data transfer cost

+Decrease power, area related to datatransfer and storage

+Increase performance

© imec 1999

Search Area memories

ATOMIUM results

,MPEG-4 Motion Estimation

RelativePower

VOP memories

Optimizations steps

0.0

1.0

0.5

Processor Level DTSETask Level DTSE

Total Memory Power

,Resulting Power Reduction = 8

© IMEC 1999 22

© imec 1999

0102030405060708090

100

Per

cent

age

(%)

Exec Time Power Bus Load

Initial Algorithm DTSE Transformed

Multi-media compilers

+MPEG-4 ontrimedia

+ Factor 12bus loadreduction

+ Factor 5powerreduction

+ Factor 3.5performanceincrease

© imec 1999

SoC++: three messages to remember

+Executable system specification,TIPSY (towards an executable “feasibility” phase)

+ Incremental refinement,Efficient path from executable spec to

implementation under designer control- FAST (mixed-signal simulation)

- OCAPI (physical layer of digital modems)

- MATISSE (network protocol processing)

- ATOMIUM (multi-dimensional “array” signal processing)

+Behavioral re-use,Re-use of functions not implementations

© IMEC 1999 23

© imec 1999

The DESICS pipeline

D6 RESEARCH PROGRAM

CoWareFrontierTarget...

ALCATELEricssonESAINTELNationalPhilipsSONY...

Industry product development

D6 / INDUSTRY TRANSFER PROJECTS

© imec 1999

IMEC Industrial R&DInteraction

© IMEC 1999 24

© imec 1999

DESICS Industrial AffiliationPrograms

HW/SW Co-designIP Re-use

HW/SW Partitioning

System Performance Modeling

Mixed Signal Design

SOC++

Memory Optimization

Training

Know-How Transfer

MPEG-4Applications

(“White Box”-IP)

Advanced WirelessLocal

CommunicationSystems

(“White Box”-IP)