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SoC Agile Development Using Intel®
CoFluent™ Studio and Wind River Simics Harsh Kumar
Business Development Manager, Intel Corporation
2
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SoC
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CPU Complex
CPU Cores Media Processing Complex
Low Power Memory Interconnect
Memory
DRAM
Low Power IO Interconnect – PCIe,
Communication.
Complex Custom IP
Storage
Complex
Standard IO Complex DMA, Interrupt, Timer, UART
Firmware
Drivers and Middleware
OS
Applications
SoC and Agile Development
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Requirements
Architecture
Launch/
Production
Integration /
Validation
HW
Development
Sustenance
FW and SW
Development
• Early and Continuous Delivery
• Welcome Changing Requirements
• Close Collaboration and Partnership
• Technical Excellence and User
Experience
• Single Executable Architecture
Specification
• Rapid Requirement/Architecture
Evaluation and Optimization
• Rapid Performance and Power
Analysis
• Rapid FW and SW development and
validation
• FW and SW Root Cause Analysis
Intel® CoFluent™ Studio
Wind River
Simics
Rapid Delivery - TTM
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System Architecture
System Specification
HW Development
SW Development System
Integration
Interactive decisions and earlier product release by shifting the design cycle left
VIRTUAL PROTOTYPE EXECUTABLE SPECIFICATION
Traditionally, SW/FW and iterations development arrive too late in the flow
Guess
Paper
Spec.
System
Design HW Design
SW Design
Iterations
System
Integration
Spreadsheet, pictures, text?...
Wind River Simics*
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Intel® CoFluent™ Studio • Single Design Source
• Single Executable Architecture Specification
• Rapid Architecture Definition, Evaluation and Optimization
• Performance, Power and Cost
• Bus & Memory Sizing
• Algorithm Validation
• Use Case Validation
• Rapid Model Generation
• For Virtual Platform to develop FW/SW
• For High Level Synthesis
• Performance and Power Root Cause Analysis
Wind River Simics
Accelerate software development, free of hardware constraints
Optimize product design, development & deployment
Replace physical hardware with a virtual platform
The leader in full system simulation for software development
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Wind River Simics System Level Features Checkpoint and restore Multicore, processor, board Real-world connections
Repeatable fault injection on any
system component
Scripting Mixed endianness, word sizes,
heterogeneity con0.wait-for-string "$“
con0.record-start
con0.input "./ptest.elf 5\n"
con0.wait-for-string "."
$r = con0.record-stop
if ($r == "fail.”) {
echo ”test failed”
}
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Wind River Simics System Debugging Features
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Synchronous stop
for entire system
Determinism and repeatability Reverse execution
Unlimited and powerful breakpoints Trace anything Insight into all devices
break –x 0x0000 length = 0x1F00
break-io uart0
break-exception int13
Rapid Model Generation from Intel® CoFluent™
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The design intent is
saved in a meta-model Specification is captured
with graphics, C/C++ code
and timing information
High-Level Synthesis
SystemC* Simulation
Virtual Platform
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Summary
• Early and Continuous Delivery
• Rapid Architecture Development
• Single Design Source thru Executable Architecture Specifications – minimum redo’s
• Concurrent Hardware, Firmware and Software Development
• Welcome Changing Requirements
• Rapid Requirements Evaluation and Validation
• Close Collaboration and Partnership
• Sharing of Executable Models and Specifications
• Technical Excellence and User Experience
• Intelligent Requirements/Architecture Trade Off
• Rapid Root Cause Analysis
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Additional Sources of Information
For Intel® CoFluent™ Studio
http://www.intel.com/content/www/us/en/cofluent/intel-cofluent-studio.html
For Wind River Simics
http://www.windriver.com/simics/
Amazing things start with Intel Inside®
