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SNS Integrated Control System
Timing Clients at SNS
DH Thompson
Epics Spring 2003
SNS Integrated Control System
You Think You Have Problems
Your timing system dates from the 16th century and
predicts tides on the Thames
The Boss Looks Like This!
Then your timing system needs updating.
SNS Integrated Control System
Timing Clients
Timing client hardware– V124– Diagnostics– Machine Protection System
Systems– Ion Source and Front End– Linac RF– Target Instruments– Machine Protection System– Diagnostics– Timing Master
SNS Integrated Control System
Hardware Clients V124S
The V124S is based directly on the RHIC Design at BNL .
Receives 17 MHz. EL from timing master.
8 programmable gate outputs and one clock output with 63 nS clock sync resolution and fine delay.
FPGA Based design.
SNS Integrated Control System
V108S Utility Module
V108 Utility module decodes EL and RTDL.– EL events can be processed as EPICS events by
processing event records.– RTDL frames are available as longin records in real time at
60 Hz. (Used to set gate widths from the timing master.)
Provides precise time to IOC from timestamp frames in the RTDL
Module also monitors crate voltages, temperature, and fan speed.
Provides 2 bits of I/O.– Example: Beam image camera gets trigger from EL in
software via V108 I/O
SNS Integrated Control System
Diagnostics Embedded Timing CircuitFeatures of PCI card (NADS)
Temporary debug section
Low jitter (~10ps) clock circuitBalanced timing
system inputs (PECL)
Coax pulse and clock outputs (LVTTL)
Buffered general purpose I/O (68 pin connector compatible with commercial breakout chassis)
Single gate array- PCI Master/Target with scatter/gather DMA- Timing functions, real-time data buffers- ~100k gates left for application specific functions
SNS Integrated Control System
Machine Protection System
Implemented on PMC Card and I/O Chassis. MPS Decodes EL/RTDL to provide 63 NS resolution of MPS trips
and time stamp MPS database records.– Used by correlator to find first trip.– Support added in drvTS so that device support could compute time
stamps.
Timing system is essential to MPS health while the MPS monitors timing system health.– 60 Hz cycle start event is required heartbeat.– Time stamp and other data on RTDL are monitored for reasonable
changes.
MPS and timing system are closely coupled– MPS derives its own clocks from EL
– Auto-Reset and Latched carriers drop on fault.
– Timing system gets fault events and status from MPS– MPS Adapts enabled inputs to beam flavor.
SNS Integrated Control System
MPS Fast Protect Block Diagram
SNS Integrated Control System
Source and Front End
Uses V124 8 Channel Gate Modules
The trigger control chassis which is the “head end” of the Machine Protection System. Outputs gates for ion source RF, Choppers, bunchers and RFQ.
SNS Integrated Control System
Ion Source Control
Trigger Control Chassis Logic(simplified)
S
R
Q
QCycle Start
Beam Enable
To Source
MPS OK
Delayed Source
Source
S
R
Q
Q
Source Enable
SNS Integrated Control System
Linac RF
Primary interface is V124 with optical fanouts to HV Converter Modules.
LLRF Uses several gate outputs including pre-pulse and RF on gate.
Gate start times and rep-rates are on Event Link. Gate widths are on RTDL, Utility module records set
V124 gate width on each LLRF and HPRF channel. Local variable rep rates and gate widths are available
at an IOC. This provides independent timing for DTL RF testing at same time as Front End operations.
SNS Integrated Control System
Ring and Target
Ring Reference is source of EL clock but actual ring phase will sync to the EL’s cycle start.
Neutron beam line instruments at the target will have own timing system based on a high speed parallel-serial-parallel link. – Will decode EL/RTDL on PCI card.– Will manage chopper synchronization to machine cycle.– Will set instrument data acquisition timing and transmit both
accelerator vetos and chopper vetos to instruments.– Will support neutron time of flight measurements.
SNS Integrated Control System
Timing Master
Uses 3 V124s to generate hardware timed events and generate some timed interrupts for the sequencer.– Sequencer schedules V124 Gates on or off according to
rep-rate pattern, to fire inputs on EL encoder.
EL will be monitored by EL Monitor as soon as driver is available.
Uses Utility module for environment but not time or events.
SNS Integrated Control System
Improvements
Combine EL and RTDL on single 100/1000 MHz link based on Ethernet media devices.
The SNS Timing Master has few external events and no hardware RDTL data, so emphasis would be on pre-scheduling link using combination of software and table in FPGA. Still allow as many hardware events as needed within scheduled windows.
More of the gate scheduling could be done at the gates, fewer events & more reliance on cycle start and RTDL.– Gate Generator decodes cycle start + RTDL RF width, and cycle
number– Sets own delay and width based on data on timing link.– Rep-rate pattern stored in gate and used to enable output.– “Special” Cycles must still be supported.
Must maintain availability of the ring sync clock and line sync clock scheme.