SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 …archimedes.ece.ntua.gr/arxeia_inputs/DSL/pack.pdf · 2019. 6. 22. · sn74155, sn74156, sn74ls155a, sn74ls156 dual 2-line to

SN5400, SN54LS00, SN54S00SN7400, SN74LS00, SN74S00

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SDLS025 – DECEMBER 1983 – REVISED MARCH 1988

1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright 1988, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.

SN5404, SN54LS04, SN54S04,SN7404, SN74LS04, SN74S04

HEX INVERTERS

SDLS029B – DECEMBER 1983 – REVISED FEBRUARY 2002


� Dependable Texas Instruments Quality andReliability

description

These devices contain six independent inverters.

Copyright 2002, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A1Y2A2Y3A3Y

GND

VCC6A6Y5A5Y4A4Y

SN5404 . . . J PACKAGESN54LS04, SN54S04 . . . J OR W PACKAGE

SN7404 . . . D, N, OR NS PACKAGESN74LS04 . . . D, DB, N, OR NS PACKAGE

SN74S04 . . . D OR N PACKAGE(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A2Y2A

VCC3A3Y4A

1Y6A6YGND5Y5A4Y

SN5404 . . . W PACKAGE(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

6YNC5ANC5Y

2ANC2YNC3A

SN54LS04, SN54S04 . . . FK PACKAGE(TOP VIEW)

1Y 1A NC

4Y 4A6A

3YG

ND

NC

NC – No internal connection

V CC

PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.

On products compliant to MIL-PRF-38535, all parameters are testedunless otherwise noted. On all other products, productionprocessing does not necessarily include testing of all parameters.

SN5406, SN5416, SN7406, SN7416HEX INVERTER BUFFERS/DRIVERS

WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS

SDLS031A – DECEMBER 1983 – REVISED DECEMBER 2001


� Convert TTL Voltage Levels to MOS Levels

� High Sink-Current Capability

� Input Clamping Diodes Simplify SystemDesign

� Open-Collector Drivers for Indicator Lampsand Relays

� Inputs Fully Compatible With Most TTLCircuits

description

These TTL hex inverter buffers/drivers featurehigh-voltage open-collector outputs for interfacingwith high-level circuits (such as MOS) or fordriving high-current loads (such as lamps orrelays), and also are characterized for use asinverter buffers for driving TTL inputs. TheSN5406 and SN7406 have minimum breakdownvoltages of 30 V. The SN5416 and SN7416 haveminimum breakdown voltages of 15 V. Themaximum sink current is 30 mA for the SN5406and SN5416, and 40 mA for the SN7406 andSN7416.

ORDERING INFORMATION

TA PACKAGE†ORDERABLE

PART NUMBERTOP-SIDEMARKING

Tube SN7406D7406

SOIC DTape and reel SN7406DR

7406

SOIC – DTube SN7416D

74160°C to 70°C Tape and reel SN7416DR

7416

PDIP N TubeSN7406N SN7406N

PDIP – N TubeSN7416N SN7416N

SOP – NS Tape and reel SN7406NSR SN7406

CDIP JTube SNJ5406J SNJ5406J

CDIP – JTube SNJ5416J SNJ5416J

–55°C to 125°CCDIP W

Tube SNJ5406W SNJ5406WCDIP – W

Tube SNJ5416W SNJ5416W

LCCC – FK Tube SNJ5406FK SNJ5406FK

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB designguidelines are available at www.ti.com/sc/package.



SN5406, SN5416 . . . J OR W PACKAGESN7406 . . . D, N, OR NS PACKAGE

SN7416 . . . D OR N PACKAGE(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A1Y2A2Y3A3Y

GND

VCC6A6Y5A5Y4A4Y

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

6YNC5ANC5Y

2ANC2YNC3A

SN5406 . . . FK PACKAGE(TOP VIEW)

1Y 1A NC

6A6A

3YG

ND

NC

CC

V4Y




QUADRUPLE 2-INPUT POSITIVE-AND GATES




SN5410, SN54LS10, SN54S10,SN7410, SN74LS10, SN74S10

TRIPLE 3-INPUT POSITIVE-NAND GATES




SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49

BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS

SDLS111 – MARCH 1974 – REVISED MARCH 1988



SN5474, SN54LS74A, SN54S74SN7474. SN74LS74A, SN74S74

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR




SN5486, SN54LS86A, SN54S86SN7486, SN74LS86A, SN74S86

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES





4-BIT MAGNITUDE COMPARATORS




SN54125, SN54126, SN54LS125A, SN54LS126A,SN74125, SN74126, SN74LS125A, SN74LS126A

QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS

SDLS044A – DECEMBER 1983 – REVISED MARCH 2002


� Quad Bus Buffers

� 3-State Outputs

� Separate Control for Each Channel

description

These bus buffers feature three-state outputsthat, when enabled, have the low impedancecharacteristics of a TTL output with additionaldrive capability at high logic levels to permitdriving heavily loaded bus lines without externalpullup resistors. When disabled, both outputtransistors are turned off, presenting ahigh-impedance state to the bus so the output willact neither as a significant load nor as a driver. The’125 and ’LS125A devices’ outputs are disabledwhen G is high. The ’126 and ’LS126A devices’outputs are disabled when G is low.

The SN54125, SN54126, SN74125, SN74126, and SN54LS126A areobsolete and are no longer supplied.



SN54125, SN54126, SN54LS125A, SN54LS126A . . . J OR W PACKAGESN74125, SN74126 . . . N PACKAGE

SN74LS125A, SN74LS126A . . . D, N, OR NS PACKAGE(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1G, 1G*1A1Y

2G, 2G*2A2Y

GND

VCC4G, 4G*4A4Y3G, 3G*3A3Y

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

4ANC4YNC3G, 3G*

1YNC

2G, 2G*NC2A

1A 1G, 1

G*

NC

3Y 3A4G

, 4G

*

2YG

ND

NC

V CC

SN54LS125A, SN54LS126A . . . FK PACKAGE(TOP VIEW)

*G on ’125 and ’LS125A devices;G on 126 and ’LS126A devicesNC – No internal connection

*G on ’125 and ’LS125A devices;G on 126 and ’LS126A devices


SN54155, SN54156, SN54LS155A, SN54LS156,SN74155, SN74156, SN74LS155A, SN74LS156

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS




SN54190, SN54191, SN54LS190, SN54LS191,SN74190, SN74191, SN74LS190, SN74LS191

SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL




SN54191, SN54LS191, SN74191, SN74LS191SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL


6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54192, SN54193, SN54LS192, SN54LS193,SN74192, SN74193, SN74LS192, SN74LS193

SYNCHRONOUS 4-BIT UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)

SDLS074 – DECMEBER 1972 – REVISED MARCH 1988



SN54193, SN54LS193, SN74193, SN74LS193SYNCHRONOUS 4-BIT UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)

SDLS074 – DECMEBER 1972 – REVISED MARCH 1988

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

��

��

�� SDLS095A – OCTOBER 1976 – REVISED MARCH 1988


Copyright 1988, Texas Instruments Incorporated�� !"#�� $ %& '�# "$ �� (&)*�%"#�� +"#',� �+&%#$ %�� ! #� $('%��%"#��$ (' #-' #' !$ �� '."$ ��$# &!'�#$$#"�+" + /" "�#0, � �+&%#�� ( �%'$$��1 +�'$ ��# �'%'$$" �*0 ��%*&+'#'$#��1 �� "** (" "!'#' $,

description

NE555, SA555, SE555PRECISION TIMERS

SLFS022C – SEPTEMBER 1973 – REVISED FEBRUARY 2002


� Timing From Microseconds to Hours

� Astable or Monostable Operation

� Adjustable Duty Cycle

� TTL-Compatible Output Can Sink or Sourceup to 200 mA

� Designed To Be Interchangeable WithSignetics NE555, SA555, and SE555

description

These devices are precision timing circuitscapable of producing accurate time delays oroscillation. In the time-delay or monostable modeof operation, the timed interval is controlled by asingle external resistor and capacitor network. Inthe astable mode of operation, the frequency andduty cycle can be controlled independently withtwo external resistors and a single externalcapacitor.

The threshold and trigger levels normally aretwo-thirds and one-third, respectively, of VCC.These levels can be altered by use of thecontrol-voltage terminal. When the trigger inputfalls below the trigger level, the flip-flop is set andthe output goes high. If the trigger input is abovethe trigger level and the threshold input is abovethe threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all otherinputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset and the outputgoes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground.

The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.

The NE555 is characterized for operation from 0°C to 70°C. The SA555 is characterized for operation from–40°C to 85°C. The SE555 is characterized for operation over the full military range of –55°C to 125°C.

AVAILABLE OPTIONS

PACKAGE

TA VTHRES MAXVCC = 15 V

SMALLOUTLINE(D, PS)

CHIPCARRIER

(FK)

CERAMICDIP(JG)

PLASTICDIP(P)

PLASTICTHIN SHRINK

SMALL OUTLINE(PW)

0°C to 70°C 11.2 VNE555DNE555PS

— — NE555P NE555PW

–40°C to 85°C 11.2 V SA555D — — SA555P —

–55°C to 125°C 10.6 V SE555D SE555FK SE555JG SE555P —

The D package is available taped and reeled. Add the suffix R to the device type (e.g., NE555DR). The PS and PW packagesare only available taped and reeled.


1

2

3

4

8

7

6

5

GNDTRIGOUT

RESET

VCCDISCHTHRESCONT

NE555 . . . D, P, PS, OR PW PACKAGESA555 . . . D OR P PACKAGE

SE555 . . . D, JG, OR P PACKAGE(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

NCDISCHNCTHRESNC

NCTRIG

NCOUT

NC

SE555 . . . FK PACKAGE(TOP VIEW)

NC

GN

DN

CC

ON

TN

CV

CC

NC

NC

RE

SE

TN

C




Documents

SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 …archimedes.ece.ntua.gr/arxeia_inputs/DSL/pack.pdf · 2019. 6. 22. · sn74155, sn74156, sn74ls155a, sn74ls156 dual 2-line to