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Digital FundamentalsDigital Fundamentals

CHAPTER 4 CHAPTER 4

Boolean Algebra and Logic SimplificationBoolean Algebra and Logic Simplification

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Boolean Operations and Expressions Boolean Operations and Expressions

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Boolean Operations and ExpressionsBoolean Operations and Expressions

• AdditionAddition0 + 0 = 00 + 0 = 0

0 + 1 = 10 + 1 = 1

1 + 0 = 11 + 0 = 1

1 + 1 = 11 + 1 = 1

• MultiplicationMultiplication0 * 0 = 00 * 0 = 0

0 * 1 = 00 * 1 = 0

1 * 0 = 01 * 0 = 0

1 * 1 = 11 * 1 = 1

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Laws and Rules of Boolean Algebra Laws and Rules of Boolean Algebra

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Laws Boolean Algebra Laws Boolean Algebra

• Commutative LawsCommutative Laws

• Associative LawsAssociative Laws

• Distributive LawDistributive Law

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Laws of Boolean AlgebraLaws of Boolean Algebra

• Commutative Law of Addition:Commutative Law of Addition:A + B = B + AA + B = B + A

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Laws of Boolean AlgebraLaws of Boolean Algebra

• Commutative Law of Multiplication:Commutative Law of Multiplication:A * B = B * AA * B = B * A

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Laws of Boolean AlgebraLaws of Boolean Algebra

• Associative Law of Addition:Associative Law of Addition:A + (B + C) = (A + B) + CA + (B + C) = (A + B) + C

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Laws of Boolean AlgebraLaws of Boolean Algebra

• Associative Law of Multiplication:Associative Law of Multiplication:A * (B * C) = (A * B) * CA * (B * C) = (A * B) * C

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Laws of Boolean AlgebraLaws of Boolean Algebra

• Distributive Law:Distributive Law:

A(B + C) = AB + ACA(B + C) = AB + AC

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Rules of Boolean AlgebraRules of Boolean Algebra

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Rules of Boolean AlgebraRules of Boolean Algebra

• Rule 1Rule 1

OR Truth Table

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Rules of Boolean AlgebraRules of Boolean Algebra

• Rule 2Rule 2

OR Truth Table

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Rules of Boolean AlgebraRules of Boolean Algebra

• Rule 3Rule 3

AND Truth Table

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Rules of Boolean AlgebraRules of Boolean Algebra

• Rule 4Rule 4

AND Truth Table

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Rules of Boolean AlgebraRules of Boolean Algebra

• Rule 5Rule 5

OR Truth Table

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Rules of Boolean Algebra Rules of Boolean Algebra

• Rule 6Rule 6

OR Truth Table

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Rules of Boolean AlgebraRules of Boolean Algebra

• Rule 7Rule 7

AND Truth Table

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Rules of Boolean AlgebraRules of Boolean Algebra

• Rule 8Rule 8

AND Truth Table

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Rules of Boolean AlgebraRules of Boolean Algebra

• Rule 9Rule 9

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Rules of Boolean AlgebraRules of Boolean Algebra

• Rule 10: A + AB = ARule 10: A + AB = A

AND Truth Table OR Truth Table

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Rules of Boolean AlgebraRules of Boolean Algebra

• Rule 11:Rule 11: BABAA

AND Truth Table OR Truth Table

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Rules of Boolean AlgebraRules of Boolean Algebra

• Rule 12: (A + B)(A + C) = A + BCRule 12: (A + B)(A + C) = A + BC

AND Truth Table OR Truth Table

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DeMorgan’s Theorem DeMorgan’s Theorem

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DeMorgan’s TheoremsDeMorgan’s Theorems

• Theorem 1Theorem 1

• Theorem 2Theorem 2

YXXY

YXYX Remember: Remember:

““Break the bar, Break the bar, change the sign”change the sign”

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Figure 4–16Figure 4–16 A logic circuit showing the development of the Boolean expression for the output.A logic circuit showing the development of the Boolean expression for the output.

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Figure 4–16Figure 4–16 A logic circuit showing the development of the Boolean expression for the output.A logic circuit showing the development of the Boolean expression for the output.

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Standard Forms of Boolean ExpressionsStandard Forms of Boolean Expressions

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Standard Forms of Boolean ExpressionsStandard Forms of Boolean Expressions

• The sum-of-product (SOP) formThe sum-of-product (SOP) formExample: X = AB + CD + EFExample: X = AB + CD + EF

• The product of sum (POS) formThe product of sum (POS) formExample: X = (A + B)(C + D)(E + F)Example: X = (A + B)(C + D)(E + F)

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Figure 4–18Figure 4–18 Implementation of the SOP expression Implementation of the SOP expression ABAB + + BCDBCD + + ACAC..

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Figure 4–19Figure 4–19 This NAND/NAND implementation is equivalent to the AND/OR in Figure 4–18. This NAND/NAND implementation is equivalent to the AND/OR in Figure 4–18.

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Figure 4–19Figure 4–19 This NAND/NAND implementation is equivalent to the AND/OR in Figure 4–18.This NAND/NAND implementation is equivalent to the AND/OR in Figure 4–18.

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The Karnaugh Map The Karnaugh Map

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The Karnaugh MapThe Karnaugh Map

3-Variable Karnaugh Map3-Variable Example

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The Karnaugh MapThe Karnaugh Map

4-Variable Karnaugh Map

4-Variable Example

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Figure 4–23Figure 4–23 Adjacent cells on a Karnaugh map are those that differ by only one Adjacent cells on a Karnaugh map are those that differ by only one variable. Arrows point between adjacent cells.variable. Arrows point between adjacent cells.

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Figure 4–24Figure 4–24 Example of mapping a standard SOP expression. Example of mapping a standard SOP expression.

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Figure 4–25 Figure 4–25

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Figure 4–28 Figure 4–28

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Figure 4–29 Figure 4–29

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Figure 4–30 Figure 4–30

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Figure 4–31 Figure 4–31

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Figure 4–32 Figure 4–32

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Figure 4–33 Figure 4–33

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Figure 4–34 Figure 4–34

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Figure 4–35Figure 4–35 Example of mapping directly from a truth table to a Karnaugh map. Example of mapping directly from a truth table to a Karnaugh map.

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Figure 4–36Figure 4–36 Example of the use of “don’t care” conditions to simplify an expression. Example of the use of “don’t care” conditions to simplify an expression.

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Figure 4–37Figure 4–37 Example of mapping a standard POS expression. Example of mapping a standard POS expression.

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Figure 4–38 Figure 4–38

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Figure 4–39 Figure 4–39

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Figure 4–40 Figure 4–40

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Figure 4–41 Figure 4–41

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The Karnaugh MapThe Karnaugh Map

5-Variable Karnaugh Mapping

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Figure 4–43Figure 4–43 Illustration of groupings of 1s in adjacent cells of a 5-variable map. Illustration of groupings of 1s in adjacent cells of a 5-variable map.

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Figure 4–44 Figure 4–44

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VHDLVHDL

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Figure 4–45Figure 4–45 A VHDL program for a 2-input AND gate. A VHDL program for a 2-input AND gate.

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VHDLVHDL

• VHDL OperatorsVHDL Operators

andand

oror

notnot

nandnand

nornor

xorxor

xnorxnor

• VHDL ElementsVHDL Elements

entityentity

architecturearchitecture

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VHDLVHDL

• Entity StructureEntity Structure

Example:Example:

entityentity AND_Gate1 AND_Gate1 isis

port(port(A,BA,B:in bit::in bit:XX:out bit);:out bit);

end entity end entity AND_Gate1AND_Gate1

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VHDLVHDL

• ArchitectureArchitecture

Example:Example:

architecturearchitecture LogicFunction of AND_Gate1 LogicFunction of AND_Gate1 isis

beginbegin

XX<=<=A A andand B B;;

end architecture end architecture LogicFunctionLogicFunction

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Figure 4–46 Figure 4–46

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Hardware Description Languages (HDL)Hardware Description Languages (HDL)

• Boolean Expressions in VHDLBoolean Expressions in VHDLANDAND X X <=<= A A andand B B;;

OROR X X <=<= A A oror B B;;

NOTNOT X X <=<= A A notnot B B;;

NANDNAND X X <=<= A A nandnand B B;;

NORNOR X X <=<= A A nornor B B;;

XORXOR X X <=<= A A xorxor B B;;

XNORXNOR X X <=<= A A xnorxnor B B;;

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Figure 4–47Figure 4–47 Seven-segment display format showing arrangement of segments. Seven-segment display format showing arrangement of segments.

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Figure 4–48Figure 4–48 Display of decimal digits with a 7-segment device. Display of decimal digits with a 7-segment device.

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Figure 4–49Figure 4–49 Arrangements of 7-segment LED displays. Arrangements of 7-segment LED displays.

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Figure 4–50Figure 4–50 Block diagram of 7-segment logic and display. Block diagram of 7-segment logic and display.

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Figure 4–51Figure 4–51 Karnaugh map minimization of the segment-a logic expression. Karnaugh map minimization of the segment-a logic expression.

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Figure 4–52Figure 4–52 The minimum logic implementation for segment a of the 7-segment display.The minimum logic implementation for segment a of the 7-segment display.

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SummarySummary

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Figure 4–54 Figure 4–54

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Figure 4–55. What is the Boolean expression for each of the logic gates?Figure 4–55. What is the Boolean expression for each of the logic gates?

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Figure 4–56. What is the Boolean expression for each of the logic gates?Figure 4–56. What is the Boolean expression for each of the logic gates?

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Figure 4–58. Derive a standard SOP and standard POS expression for each truth table.Figure 4–58. Derive a standard SOP and standard POS expression for each truth table.

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Figure 4–59. Figure 4–59. Reduce the function in the truth table to its minimum SOP form by using a Karnaugh map.Reduce the function in the truth table to its minimum SOP form by using a Karnaugh map.

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Figure 4–62. Example 4-21. Related Problem answer.Figure 4–62. Example 4-21. Related Problem answer.

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Figure 4–63. Example 4-22. Related Problem answer.Figure 4–63. Example 4-22. Related Problem answer.

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Figure 4–64. Example 4-23. Related Problem answer.Figure 4–64. Example 4-23. Related Problem answer.

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Figure 4–65. Example 4-24. Related Problem answer.Figure 4–65. Example 4-24. Related Problem answer.

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Figure 4–66. Example 4-30. Related Problem answer.Figure 4–66. Example 4-30. Related Problem answer.