sld virtual jtag Megafunction User Guide - Digchipapplication-notes.digchip.com/038/38-21643.pdf · example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such

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101 Innovation DriveSan Jose, CA 95134(408) 544-7000www.altera.com

sld_virtual_jtag Megafunction

User Guide

Software Version: 6.0Document Version: 1.0 Document Date: June 2006

http://www.altera.com

Copyright © 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks andservice marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al-tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrantsperformance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to makechanges to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap-plication or use of any information, product, or service described herein except as expressly agreed to in writing by AlteraCorporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in-formation and before placing orders for products or services.

ii Altera Corporationsld_virtual_jtag Megafunction User Guide Preliminary May 2006

UG-SLDVRTL-1.0

Altera Corporation June 2006

Contents

Revision History ........................................................................................................................................ vHow to Contact Altera .............................................................................................................................. vTypographic Conventions ...................................................................................................................... vi

Chapter 1. About This MegafunctionDevice Family Support ......................................................................................................................... 1–1Introduction ............................................................................................................................................ 1–1The JTAG Protocol ................................................................................................................................. 1–3Description of the Virtual JTAG Interface (VJI) ................................................................................ 1–4

Overview ........................................................................................................................................... 1–4Operation ........................................................................................................................................... 1–6

Instruction Register Scan Shifts ................................................................................................ 1–6Data Register Scan Shifts ........................................................................................................... 1–6

Communication with the sld_virtual_jtag Instance .................................................................... 1–7Applications ........................................................................................................................................... 1–9

Chapter 2. Getting StartedSystem & Software Requirements ....................................................................................................... 2–1Using the MegaWizard Plug-In Manager .......................................................................................... 2–1Instantiating the sld_virtual_jtag Megafunction in Your Design ................................................. 2–11Simulation Support ............................................................................................................................. 2–14Compiling the Design ......................................................................................................................... 2–17

Third-Party Synthesis Support ..................................................................................................... 2–19Design Example 1 ................................................................................................................................ 2–20

Introduction .................................................................................................................................... 2–20Design Files ..................................................................................................................................... 2–20Requirements .................................................................................................................................. 2–21Generate a sld_virtual_jtag Module ............................................................................................ 2–21Sampling & Updating the Contents of Internal State Machines ............................................. 2–29Simulation Support ........................................................................................................................ 2–31

Design Example 2 ................................................................................................................................ 2–32Introduction .................................................................................................................................... 2–32Design Files ..................................................................................................................................... 2–32Requirements .................................................................................................................................. 2–32Generate a sld_virtual_jtag Module ............................................................................................ 2–33Reading the Contents of a Counter Captured in a RAM .......................................................... 2–33

Conclusion ............................................................................................................................................ 2–35

Chapter 3. SpecificationsPorts & Parameters ................................................................................................................................ 3–1

iiisld_virtual_jtag Megafunction User Guide

Contents sld_virtual_jtag Megafunction User Guide

iv Altera Corporationsld_virtual_jtag Megafunction User Guide June 2006


About This User Guide

Revision History The table below displays the revision history for the chapters in this User Guide.

How to Contact Altera

For the most up-to-date information about Altera® products, go to the Altera world-wide web site at www.altera.com. For technical support on this product, go to www.altera.com/mysupport. For additional information about Altera products, consult the sources shown below.

Chapter Date Document Version Changes Made

All June 2006 1.0 Initial release.

Information Type USA & Canada All Other Locations

Technical support www.altera.com/mysupport/ www.altera.com/mysupport/

(800) 800-EPLD (3753)(7:00 a.m. to 5:00 p.m. Pacific Time)

+1 408-544-8767(1)7:00 a.m. to 5:00 p.m. (GMT -8:00) Pacific Time

Product literature www.altera.com (1) www.altera.com (1)

Altera literature services [email protected] [email protected]

Non-technical customer service

(800) 767-3753 + 1 408-544-70007:00 a.m. to 5:00 p.m. (GMT -8:00) Pacific Time

FTP site ftp.altera.com ftp.altera.com

Note to table:(1) You can also contact your local Altera sales office or sales representative.

vsld_virtual_jtag Megafunction User Guide


http://www.altera.com/mysupport

http://www.altera.com/mysupport/



mailto:[email protected]

mailto:[email protected]

ftp://ftp.altera.com

ftp://ftp.altera.com

http://www.altera.com/mysupport/

Typographic Conventions

Typographic Conventions

This document uses the typographic conventions shown below.

Visual Cue Meaning

Bold Type with Initial Capital Letters

Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box.

bold type External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.

Italic Type with Initial Capital Letters

Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed Board Design.

Italic type Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.

Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: <file name>, <project name>.pof file.

Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu.

“Subheading Title” References to sections within a document and titles of on-line help topics are shown in quotation marks. Example: “Typographic Conventions.”

Courier type Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.

Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.

1., 2., 3., anda., b., c., etc.

Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure.

■ ● • Bullets are used in a list of items when the sequence of the items is not important.

v The checkmark indicates a procedure that consists of one step only.

1 The hand points to information that requires special attention.

cThe caution indicates required information that needs special consideration and understanding and should be read prior to starting or continuing with the procedure or process.

w The warning indicates information that should be read prior to starting or continuing the procedure or processes.

r The angled arrow indicates you should press the Enter key.

f The feet direct you to more information about a particular topic.

vi Altera Corporationsld_virtual_jtag Megafunction User Guide June 2006


1. About This Megafunction

Device Family Support

Megafunctions provide either full or preliminary support for target Altera® device families, as described below:

■ Full support means the megafunction meets all functional and timing requirements for the device family and may be used in production designs

■ Preliminary support means the megafunction meets all functional requirements, but may still be undergoing timing analysis for the device family; it may be used in production designs with caution

Table 1–1 shows the level of support offered by the sld_virtual_jtag megafunction for each Altera device family.

Introduction As designs grow ever larger, with more and more functions being added, designers need better debugging features and tools. As more design blocks are integrated on a single system-on-a-programmable-chip (SOPC) device, not all of the signal and bus activity can be seen from the ports of the device. In-system debugging tools therefore become necessary. Designers need better verification, monitoring, and updating solutions for qualifying their designs.

Altera provides many powerful tools for on-chip debugging in the Quartus® II software, where you can look inside the design while it is running at full speed in the system. Tools such as the SignalTap® II logic

Table 1–1. Device Family Support

Device Family Support

Stratix® II Full

Stratix Full

Stratix II GX Full

Stratix GX Full

Cyclone™ II Full

Cyclone Full

MAX® II Full

APEX™ II Full

APEX 20K Full

1–1sld_virtual_jtag Megafunction User Guide

Introduction

analyzer, the SignalProbe™ feature, and the external Logic Analyzer Interface (LAI) are very popular among designers and have been successfully used for debugging their designs.

The SignalTap II logic analyzer can probe various signals in the design and capture them in the device’s own memory. The data is then retrieved via a JTAG port using an Altera download cable to the PC running the logic analyzer software. The LAI can probe internal signals and send their content outside the device using the device’s I/O pins to the external logic analyzer. The JTAG port is used in conjunction with the LAI core to control the selection of signal banks. These signal banks are different sets of internal signals hooked up in multiplexer fashion.

Although these tools are very powerful, the complexity of today’s systems require additional instrumentation techniques for in-system debugging of your design. These techniques include:

■ Achieving unreachable trigger conditions defined in the SignalTap II logic analyzer

■ Accelerating in-system debugging by loading various registers in your design to achieve trigger conditions that happen very late during debugging

■ Adding virtual input pins to your design■ Configuring some parts of your design to run in test mode while

other parts run in operation mode

The sld_virtual_jtag megafunction addresses these needs and requirements of today’s in-system debugging.

Designers today also build their own system-level debugging infrastructure. This task includes both building their own processor-based debugging solutions and building their own debugging tools in software for system level debugging. The sld_virtual_jtag megafunction can provide one or more transparent communication channels to access different parts of your PLD design using the JTAG interface of the device.

The sld_virtual_jtag megafunction can be instantiated in your HDL code directly. The HDL code containing instances of this megafunction can be synthesized with the Quartus II software or with third-party synthesis software. For communication, you can use Tool Command Language (Tcl) commands to communicate with the parts of your design to which these megafunctions are connected. The Tcl commands run on a host computer that has the quartus_stp executable installed on it. You can also use your own custom hardware, such as a microcontroller, to implement the low-level JTAG controls that create a communication channel between your JTAG controller and this megafunction.

1–2 Altera Corporationsld_virtual_jtag Megafunction User Guide June 2006

About This Megafunction

f For more information about using the SignalTap II embedded logic analyzer, refer to the Design Debugging Using the SignalTap II Embedded Logic Analyzer chapter in volume 3 of the Quartus II Handbook. For more information about using the Logic Analyzer Interface, refer to the In-System Debugging Using External Logic Analyzers chapter in volume 3 of the Quartus II Handbook.

The JTAG Protocol

The Joint Action Test Group (JTAG) defines the specification for Boundary Scan Testing (BST), which is also known as IEEE 1149.1.

One purpose of the JTAG standard is to test device I/Os and their connections to the board during the board’s initial testing. The JTAG architecture consists of a TAP controller, an instruction register (IR), and several data registers (DRs). The input ports to the JTAG circuit are tck, tdi, trst, and tms. The output port from the JTAG circuit is tdo.

The TAP controller is a state machine that transitions through different states on every tck clock cycle. The input to the state machine is tms. The JTAG protocol specifies that data is shifted into the PLD device on the tdi port and shifted out on the tdo port. All of the data is shifted in or out as scan shifts. The JTAG operation involves two scan shifts. The first is an instruction register (IR) scan shift during which data is shifted into the IR of the JTAG circuit on the tdi port. The second is a data register (DR) scan shift during which data is shifted into and out of various DRs of the JTAG circuit on the tdo port.

The JTAG resource on PLD devices is used to perform both testing and configuration of the device; that is, programming the PLD device with a programming file. The JTAG resource is also used in applications such as in-system debugging. Altera’s in-system debugging solutions, including the SignalTap II logic analyzer and In-System Memory Content Editor, use the same JTAG resource on the device to exchange data with the device.

f For a detailed specification of JTAG, refer to application note AN 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices.

Altera Corporation 1–3June 2006 sld_virtual_jtag Megafunction User Guide

Description of the Virtual JTAG Interface (VJI)


1 The Virtual JTAG Interface (VJI) or sld_virtual_jtag megafunction mean the same thing in this document and are used interchangeably.

Overview

The Virtual JTAG Interface provides you with an interface that is similar to the JTAG interface in your designs. Figure 1–1 shows the input and output ports of the design. Figure 1–2 shows a device that consists of a counter and multiple instances of the Virtual JTAG Interface. These VJI instances can be connected to parts of the original design (counter in this case) to achieve different applications. Typical applications of using the VJI in a design are discussed in “Applications” on page 1–9.

Figure 1–1. Input and Output Ports of VJI

Note for Figure 1–1(1) These output ports are collectively referred to as out* in Figure 1–2.



Figure 1–2. VJI and JTAG Block Diagram Note (1)

Notes for Figure 1–2:(1) The outputs of VJI, other than those specified here, are collectively called out*, as shown in Figure 1–1.(2) The trst input to the JTAG circuit is optional on some devices.

The VJI uses the TAP controller of the JTAG device as its state machine. Each VJI instance in a design consists of an instruction register (IR) and logic gates.

Each VJI instance in your design provides tck, tdi, and tms output ports and a tdo input port. In addition, each instance has multiple output ports, collectively called out* in Figure 1–2. The out* ports are active high outputs. They are asserted high to show various states of the JTAG TAP controller and internal states of VJI during scan shift operations.

There is also an ir_in output port. The width of this port depends on the IR width of VJI and reflects the contents of the IR. Each VJI's IR can be 1 bit to 32 bits in width. There is an ir_out input port that has the same width as the ir_in port. The ir_out input port is used to pass any user data from your design to the addressing application. Refer to “Instruction Register Scan Shifts” on page 1–6 for more information about passing data using the ir_out port.

f For more details about the sld_virtual_jtag megafunction’s ports and parameters, refer to Chapter 3, Specifications.



Figure 1–2 shows how a VJI instance connects to your design on one side and to the JTAG circuit of the device through the JTAG hub on the other. The connections through the hub to the JTAG circuit are transparent. They are set up automatically when your design is compiled with the Quartus II software.

The Virtual JTAG Interface can be used in your design to help implement various applications. For example, one application might be to load a counter in a design through the device’s JTAG circuit. The VJI is connected with the counter in this design. For more details about how this design can be achieved in Verilog HDL code, refer to “Instantiating the sld_virtual_jtag Megafunction in Your Design” on page 2–11. More applications of VJI are described in “Applications” on page 1–9.

Operation

The VJI supports two types of scan shifts that are very similar to the scan shifts used in the JTAG protocol. These two scan shifts are instruction register (IR) scan shifts and data register (DR) scan shifts.

Consider an application that drives the JTAG port of the device. This application could be a software application running on a host computer or it could be some custom hardware that can initiate scan shifts for the JTAG. To realize IR and DR scan shifts for the VJI, the application communicates with the JTAG hardware on the device, which in turn communicates with the VJI instances inside the design. More details about methods of communicating with VJI instances can be found in “Communication with the sld_virtual_jtag Instance” on page 1–7.

Instruction Register Scan Shifts

During an IR scan shift, data is shifted into the IR of the VJI instance. The VJI ports involved in this operation are ir_in and ir_out. During an IR scan shift, the flow of data is from the JTAG ports of the device into the IR of the VJI. The ir_in output port reflects the contents of the IR. The ir_out port is used during this scan shift to pass any data from the design to the JTAG circuit and finally to the addressing application. If there are multiple instances of the VJI in a design, separate IR scan shifts must be used to configure the IR in each VJI instance.

Data Register Scan Shifts

Similar to the JTAG circuit architecture, various DRs can be defined in your design for each VJI instance. These data registers are shift registers that capture the data from the VJI's tdi output port during a DR scan shift operation. VJI ports involved in a DR shift are tck, tdi, and tdo. During this shift, data is shifted into DRs associated with the VJI. At the



same time, data is shifted out from the same DRs on the VJI's tdo pin. All the transitions on the VJI's tdi and tdo ports are synchronous with the VJI's tck clock.

During both IR and DR scan shifts, the JTAG TAP controller transitions through various states. These transitions are reflected on the output ports named out* in Figure 1–2 on page 1–5.

Communication with the sld_virtual_jtag Instance

The sld_virtual_jtag megafunction is one of the system-level debugging (SLD) modules provided with the Quartus II software. Other SLD modules include the SignalTap II logic analyzer and the external Logic Analyzer Interface (LAI).

The VJI is part of the SLD infrastructure that is supported by the quartus_stp executable. The quartus_stp executable is part of the Quartus II software. It can be installed as a stand-alone program on any host computer that is running the Windows operating system. This software is used to send data to and receive data from the VJI instances inside your design. All communication between the application and the sld_virtual_jtag megafunction is through the JTAG ports of the device.

You can use the quartus_stp executable to send and receive data from the sld_virtual_jtag megafunction using the following Tcl commands:

■ get_hardware_names■ get_device_names■ open_device■ close_device■ device_lock■ device_unlock■ device_dr_shift■ device_ir_shift■ device_virtual_dr_shift■ device_virtual_ir_shift

The Tcl command used to perform an IR scan shift with the VJI is device_virtual_ir_shift. The underlying JTAG commands used during the IR scan shift are device_ir_shift and device_dr_shift. During this shift, the IR of a particular VJI instance is loaded with the data.

The Tcl command used to perform a DR scan shift for the VJI is device_virtual_dr_shift. The underlying JTAG commands used during this operation are device_ir_shift and device_dr_shift.



The following Tcl commands show the usage of these commands:

device_virtual_ir_shift -instance_index 0 -ir_value 2 \ -no_captured_ir_value

device_virtual_dr_shift -instance_index 0 -length 4 -dr_value \ $update_value -value_in_hex -no_captured_dr_value

f For detailed information about these commands, consult the Quartus II Scripting Reference Manual on the Quartus II Literature page on the Altera website.

You can put these Tcl commands in a script and run them by typing the following command at the system prompt:

quartus_stp -t <file_name>.tcl r

For examples that use these commands, refer to “Design Example 1” on page 2–20 and “Design Example 2” on page 2–32.

The data can be transferred to the VJI instance by two methods. One is to use the quartus_stp executable and Tcl commands. The other is to use your own hardware that behaves like a JTAG port controller. For example, a microcontroller can be used to send and receive data from VJI instances through the JTAG port of the device. You must understand the underlying JTAG commands that the quartus_stp executable uses. These underlying JTAG commands must be converted to appropriate device driver commands. These device drivers are then used by your custom hardware (microcontroller) for driving the JTAG port or the device.

To see the underlying JTAG commands that are called during IR and DR scan shifts, use the show_equivalent_device_ir_dr_shift option with the device_virtual_ir_shift or device_virtual_dr_shift commands.

The following Tcl commands show their usage:

device_virtual_ir_shift -instance_index 0 -ir_value 2 \ -no_captured_ir_value -show_equivalent_device_ir_dr_shift

device_virtual_dr_shift -instance_index 0 -length 4 -dr_value \ $update_value -value_in_hex -no_captured_dr_value \ -show_equivalent_device_ir_dr_shift

Figure 1–3 shows a block diagram of the hardware setup where a host computer with the quartus_stp executable communicates with the FPGA device.



Figure 1–3. Block Diagram Showing a Hardware Communication Setup

You can replace the quartus_stp executable and download cable with an appropriate microcontroller.

Applications Single or multiple instances of the VJI can be instantiated in your HDL code. During synthesis, the Quartus II software assigns unique IDs to each instance so each instance can be accessed individually. The maximum number of VJI instances you can use in a design is 128.

Figure 1–4 shows a typical application in a design with multiple instances of the sld_virtual_jtag megafunction.


Applications

Figure 1–4. Application Example

Behavioral simulation is supported for this megafunction. The simulation is supported by all Altera-supported simulators such as VCS, ModelSim, and NC-Sim. More information about simulation can be found in “Simulation Support” on page 2–14.

The VJI and the quartus_stp executable can operate simultaneously with other debugging applications, such as the SignalTap II logic analyzer and the In-System Memory Content Editor. No conflicts are created when these different utilities are run simultaneously. This feature provides more productivity, efficiency, and flexibility to create solutions that meet your debugging needs.

The VJI can be used in many applications, including the following:

■ The megafunction can be used to diagnose, sample, and update the values of internal parts of your logic. With this megafunction, you can easily sample and update the values of the internal counters and state machines in your hardware device.

■ You can build your own custom software debugging IP using the Tcl commands listed above to debug your hardware. This IP communicates with the instances of the sld_virtual_jtag megafunction inside your design.

■ You can instrument your design to achieve virtual inputs and outputs in your design.



■ If you are building a debugging solution for a system where a microprocessor controls the JTAG chain, the SignalTap II embedded logic analyzer cannot be used because the JTAG control has to be with the microprocessor. By learning the low level controls for the JTAG port from the Tcl commands, you can program microprocessors to communicate with the sld_virtual_jtag megafunction inside the device core.


Applications



2. Getting Started

System & Software Requirements

The instructions in this section require the following hardware and software:

■ A PC running Windows 2000/XP/XP 64-bit, or Red Hat Enterprise Linux 3.0 or 4.0

orA Sun workstation running the Solaris 8 or 9 operating system

■ The Quartus® II software beginning with version 6.0■ An Altera® download cable, such as a USB-Blaster™ cable

1 Windows XP 64-bit supports only the 32-bit version of the Quartus II software, not the 64-bit version. Additionally, Windows XP 64-bit does not support programming cable drivers for the Quartus II software. You must use another supported operating system to program devices

The download cable is required to communicate with the sld_virtual_jtag megafunction from a host running the quartus_stp executable. The quartus_stp executable runs only on Windows machines.

Using the MegaWizard Plug-In Manager

To create the sld_virtual_jtag megafunction in your design, you must use the MegaWizard® Plug-In Manager within the Quartus II software. Perform the following steps to generate the megafunction.

1. On the Tools menu, click MegaWizard Plug-In Manager. The MegaWizard Plug-In Manager dialog box appears (Figure 2–1).



Figure 2–1. MegaWizard Plug-In Manager, Page 1

2. Select Create a new custom megafunction variation.

3. Click Next. Page 2a of the MegaWizard Plug-In Manager appears (Figure 2–2).


Getting Started

Figure 2–2. MegaWizard Plug-In Manager, Page 2a

4. On the list of megafunctions, click Virtual JTAG.

5. Select the device family you are using.

6. Select the type of output file you want to create: Verilog HDL, VHDL, or AHDL.

7. Specify the name of the output file and its location, as shown in Figure 2–2.

8. Click Next. Page 3 of the MegaWizard Plug-In Manager appears (Figure 2–3).




9. Select the width (number of bits) of your instruction register.

10. Assign a unique ID to the instance of your sld_virtual_jtag megafunction. The wizard can assign an ID automatically (recommended) or you can enter one manually.



Getting Started


12. Page 4 defines the stimuli that are used during the simulation of your megafunction. A stimulus is either a data register shift (DR shift) or an instruction register shift (IR shift). Each stimulus requires a time at which that shift occurs, the number of bits you want to shift in or out, and the data value you want to shift in during a shift-in operation. You can add multiple stimuli by clicking Add Stimulus in the dialog box.

The stimuli specified on Page 4 of the wizard are written to the variation file. If you want to change a stimulus after creating the megafunction, you can either edit the variation file or create the megafunction again with a new stimulus. The wizard provides an easy way to generate your stimuli. If you do not want to generate the stimuli, you can skip this step. The stimuli, though, are necessary if you are performing simulation of your design.



13. Click Next. Page 5 of the MegaWizard Plug-In Manager appears (Figure 2–5). In this example, the page shows that you need the altera_mf library to simulate the VJI megafunction in your design.

There is no input required from you on this page.




Getting Started


15. Select any other files you need in addition to the megafunction variation file and the megafunction black box file.

16. Click Finish to create the sld_virtual_jtag megafunction. This action creates the files you need in your project.

The output from the MegaWizard Plug-In Manager is a variation file. The following example shows a sld_virtual_jtag megafunction variation file in VHDL.



LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY altera_mf;USE altera_mf.all;ENTITY my_vji IS PORT ( ir_out : IN STD_LOGIC_VECTOR (1 DOWNTO 0); tdo : IN STD_LOGIC ; ir_in : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); jtag_state_cdr : OUT STD_LOGIC ; jtag_state_cir : OUT STD_LOGIC ; jtag_state_e1dr : OUT STD_LOGIC ; jtag_state_e1ir : OUT STD_LOGIC ; jtag_state_e2dr : OUT STD_LOGIC ; jtag_state_e2ir : OUT STD_LOGIC ; jtag_state_pdr : OUT STD_LOGIC ; jtag_state_pir : OUT STD_LOGIC ; jtag_state_rti : OUT STD_LOGIC ; jtag_state_sdr : OUT STD_LOGIC ; jtag_state_sdrs : OUT STD_LOGIC ; jtag_state_sir : OUT STD_LOGIC ; jtag_state_sirs : OUT STD_LOGIC ; jtag_state_tlr : OUT STD_LOGIC ; jtag_state_udr : OUT STD_LOGIC ; jtag_state_uir : OUT STD_LOGIC ; tck : OUT STD_LOGIC ; tdi : OUT STD_LOGIC ; tms : OUT STD_LOGIC ; virtual_state_cdr : OUT STD_LOGIC ; virtual_state_cir : OUT STD_LOGIC ; virtual_state_e1dr : OUT STD_LOGIC ; virtual_state_e2dr : OUT STD_LOGIC ; virtual_state_pdr : OUT STD_LOGIC ; virtual_state_sdr : OUT STD_LOGIC ; virtual_state_udr : OUT STD_LOGIC ; virtual_state_uir : OUT STD_LOGIC );END my_vji;

ARCHITECTURE SYN OF my_vji IS

COMPONENT sld_virtual_jtagGENERIC (

sld_auto_instance_index : STRING;sld_instance_index : NATURAL;sld_ir_width : NATURAL;sld_sim_action : STRING;sld_sim_n_scan : NATURAL;sld_sim_total_length : NATURAL;lpm_type : STRING);


Getting Started

PORT (tdi : OUT STD_LOGIC ;jtag_state_rti_type : OUT STD_LOGIC ;jtag_state_e1dr : OUT STD_LOGIC ;jtag_state_e2dr : OUT STD_LOGIC ;tms : OUT STD_LOGIC ;jtag_state_pir : OUT STD_LOGIC ;jtag_state_tlr : OUT STD_LOGIC ;tck : OUT STD_LOGIC ;jtag_state_sir : OUT STD_LOGIC ;ir_in : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);virtual_state_cir : OUT STD_LOGIC ;virtual_state_pdr : OUT STD_LOGIC ;ir_out : IN STD_LOGIC_VECTOR (1 DOWNTO 0);virtual_state_uir : OUT STD_LOGIC ;jtag_state_cir : OUT STD_LOGIC ;jtag_state_uir : OUT STD_LOGIC ;jtag_state_pdr : OUT STD_LOGIC ;tdo : IN STD_LOGIC ;jtag_state_sdrs : OUT STD_LOGIC ;virtual_state_sdr : OUT STD_LOGIC ;virtual_state_cdr : OUT STD_LOGIC ;jtag_state_sdr : OUT STD_LOGIC ;jtag_state_cdr : OUT STD_LOGIC ;virtual_state_udr : OUT STD_LOGIC ;jtag_state_udr : OUT STD_LOGIC ;jtag_state_sirs : OUT STD_LOGIC ;jtag_state_e1ir : OUT STD_LOGIC ;jtag_state_e2ir : OUT STD_LOGIC ;virtual_state_e1dr : OUT STD_LOGIC ;virtual_state_e2dr : OUT STD_LOGIC

);END COMPONENT;

BEGIN

sld_virtual_jtag_component : sld_virtual_jtagGENERIC MAP (

sld_auto_instance_index => "YES",sld_instance_index => 0,sld_ir_width => 2,sld_sim_action => "",sld_sim_n_scan => 0,sld_sim_total_length => 0,lpm_type => "sld_virtual_jtag"

)PORT MAP (...);

END SYN;



The same sld_virtual_jtag megafunction variation file in Verilog HDL is shown below.

/* Verilog HDL code showing the input and output ports of the sld_virtual_jtag megafunction*/module my_vji ( ir_out, tdo, ir_in, jtag_state_cdr, jtag_state_cir, jtag_state_e1dr,

jtag_state_e1ir, jtag_state_e2dr,

jtag_state_e2ir, jtag_state_pdr, jtag_state_pir, jtag_state_rti, jtag_state_sdr, jtag_state_sdrs, jtag_state_sir, jtag_state_sirs, jtag_state_tlr, jtag_state_udr, jtag_state_uir, tck, tdi, tms, virtual_state_cdr, virtual_state_cir, virtual_state_e1dr, virtual_state_e2dr, virtual_state_pdr, virtual_state_sdr, virtual_state_udr, virtual_state_uir); input [1:0] ir_out; input tdo;

output [1:0] ir_in;output tck;

output tdi;output tms;output jtag_state_cdr;

output jtag_state_cir; output jtag_state_e1dr; output jtag_state_e1ir; output jtag_state_e2dr; output jtag_state_e2ir; output jtag_state_pdr; output jtag_state_pir; output jtag_state_rti; output jtag_state_sdr;


Getting Started

output jtag_state_sdrs; output jtag_state_sir; output jtag_state_sirs; output jtag_state_tlr; output jtag_state_udr; output jtag_state_uir; output virtual_state_cdr; output virtual_state_cir; output virtual_state_e1dr; output virtual_state_e2dr; output virtual_state_pdr; output virtual_state_sdr; output virtual_state_udr; output virtual_state_uir;

sld_virtual_jtag sld_virtual_jtag_component (......);

defparamsld_virtual_jtag_component.sld_auto_instance_index = "YES",sld_virtual_jtag_component.sld_instance_index = 0,sld_virtual_jtag_component.sld_ir_width = 2,sld_virtual_jtag_component.sld_sim_action = "",sld_virtual_jtag_component.sld_sim_n_scan = 0,sld_virtual_jtag_component.sld_sim_total_length = 0;

endmodule

In the code shown for the variation file, the top module instantiates a sld_virtual_jtag megafunction component. The functional model of this component used for simulation is present in the altera_mf simulation library. The stimuli defined in the MegaWizard Plug-In Manager are passed to this simulation model as parameters.

Instantiating the sld_virtual_jtag Megafunction in Your Design

To properly connect the sld_virtual_jtag megafunction in your design, you should follow these basic connection rules:

■ The tck output from the VJI is the clock used for shifting the data in and out on the tdi and tdo pins.

■ The tms output of the VJI reflects the tms input to the main JTAG circuit.

■ The ir_in output port of the VJI reflects whatever data gets loaded in the IR of VJI and is used to build some decode logic.

■ Outputs other than tck, tdi, tdo, tms, and ir_in represent various states of the megafunction and JTAG TAP controller. They are available to be used as needed, but they are not required to achieve a serial link between the sld_virtual_jtag instance and the addressing application.


Instantiating the sld_virtual_jtag Megafunction in Your Design

You can use the following Verilog HDL template as a guide for instantiating and connecting various signals of the megafunctions in your design.

The following code creates a 4-bit counter named my_counter. The input is clock and the output is my_counter. The counter increments synchronously on every clock edge.

module counter (clock, my_counter);input clock;output [3:0] my_counter;reg [3:0] my_counter;

always @ (posedge clock)my_counter <= my_counter + 1;

endmodule

The purpose of instantiating a VJI instance in this example is to load my_counter through the JTAG port using a software application built with Tcl commands and the quartus_stp executable. In this design, the VJI instance is called my_vji. Whenever a VJI megafunction is instantiated in a design, three logic blocks are usually needed: a decode logic block, a tdo logic block, and a data register block. The following code takes the code shown above and adds the VJI instance, the decode logic, the tdo logic and the data register blocks.

module counter (clock, my_counter);input clock;output [3:0] my_counter;reg [3:0] my_counter;

always @ (posedge clock)if (load && e1dr) // decode logic: used to load the counter my_counter

my_counter <= tmp_reg;else

my_counter <= my_counter + 1;

// Signals and registers declared for VJI instance wire tck, tdi;reg tdo;wire cdr, eldr, e2dr, pdr, sdr, udr, uir, cir;wire [1:0] ir_in;

// Instantiation of VJImy_vji VJI_INST(

.tdo (tdo),

.tck (tck),

.tdi (tdi),

.tms(),


Getting Started

.ir_in(ir_in),

.ir_out(),

.virtual_state_cdr (cdr),

.virtual_state_e1dr(e1dr),

.virtual_state_e2dr(e2dr),

.virtual_state_pdr (pdr),

.virtual_state_sdr (sdr),

.virtual_state_udr (udr),

.virtual_state_uir (uir),

.virtual_state_cir (cir)

);

// Declaration of data registerreg [3:0] tmp_reg;

// Deocde Logic Block// Making some decode logic from ir_in output port of VJIwire load = ir_in[1] && ~ir_in[0];

// Bypass register used to maintain the scan chain continuity for// tdi and tdo ports always @ (posedge tck)bypass_reg = tdi;

// Data Register Blockalways @ (posedge tck)

if ( load && sdr )tmp_reg <= {tdi, tmp_reg[3:1]};

// tdo Logic Blockalways @ (posedge tck)

if(load) tdo <= tmp_reg[0]

elsetdo <= bypass_reg;

endmodule

The decode logic is produced by defining a wire load to be active high whenever the IR of the VJI is 01. The IR scan shift is used to load the data into the IR of the VJI. The ir_in output port reflects the IR contents.

The data register logic contains a 4-bit shift register named tmp_reg. The always blocks shown for the data register logic also contains the decode logic consisting of the load and sdr signals. The sdr signal is the output of the VJI that is asserted high during a DR scan shift operation. The time during which the sdr output is asserted high is the time in which the data


Simulation Support

on tdi is valid. During that time period the data is shifted into the tmp_reg shift register. Thus tmp_reg gets the data from the VJI on the tdi output port during a DR scan operation.

There is a 1-bit register named bypass_reg whose output is connected with tdo logic to maintain the continuity of the scan chain during idle or IR scan shift operation of the VJI. The tdo logic consists of outputs coming from tmp_reg and bypass_reg and connecting to the tdo input of the VJI. The tdo logic passes the data from tmp_reg to the VJI during DR scan shift operations.

The always block of a 4-bit counter also consists of some decode logic. This decode logic uses the load signal and cdr output signal of the VJI to load the counter with the contents of tmp_reg. The VJI output signal cdr is asserted high during a DR scan shift operation when all the data is completely shifted into the tmp_reg and sdr has been deasserted. In addition to sdr and cdr, there are other outputs from VJI that are asserted high to show various states of the TAP controller and internal states of the VJI. All these signals can be used to perform different logic operations as needed in your design. Figure 1–1 on page 1–4 shows all of the input and output ports of VJI.

Simulation Support

Virtual JTAG Interface operations can be simulated using all Altera-supported simulators. The simulation support is for DR and IR scan shift operations. For simulation purposes, a behavioral simulation model of the megafunction is provided in both VHDL and Verilog HDL in the altera_mf libraries. The I/O structure of the model is the same as the megafunction.

In its implementation, the VJI connects to your design on one side and to the JTAG port through the JTAG hub on other (refer to Figure 1–2 on page 1–5). However, a simulation model connects only to your design. There is no simulation model for the JTAG circuit. Therefore, no stimuli can be provided from the JTAG ports of the device to imitate the scan shift operations of the VJI in simulation.

The scan operations in simulation are realized using the simulation model. The simulation model consists of a signal generator, a dummy hub, and the VJI model. The stimuli defined in the wizard are passed as parameters to this simulation model from the variation file. The simulation parameters are listed in Table 2–1. The signal generator then produces the necessary signals for VJI outputs such as tck, tdi, tms, and so forth.

The model is parameterized to allow the simulation of an unlimited number of VJI instances. The parameter sld_sim_action defines the strings used for IR and DR scan shifts. Each VJI’s variation file passes


Getting Started

these parameters to the VJI component. The VJI’s variation file can always be edited for generating different stimuli, though the preferred way to specify stimuli for DR and IR scan shifts is to use the MegaWizard Plug-In Manager.

Simulation has the following limitations:

■ Scan shifts (IR or DR) must be at least 1 ms apart in simulation time.■ Only behavioral or functional level simulation support is present for

this megafunction. There is no gate level or timing level simulation support.

■ For behavioral simulation, the stimuli tell the signal generator model in the sld_virtual_jtag model to generate the sequence of signals needed to produce the necessary outputs for tck, tms, tdi, and so forth. You cannot provide the stimulus at the JTAG pins of the device.

■ The tck clock period used in simulation is 10 MHz with a 50% duty cycle. In hardware the period of the tck clock cycle may vary.

Table 2–1. Description of Simulation Parameters

Parameter Comments

SLD_SIM_N_SCAN Specifies the number of shifts in the simulation model.

SLD_SIM_TOTAL_LENGTH The total number of bits to be shifted in either an IR shift or a DR shift. This value should be equal to the sum of all the length values specified in the SLD_SIM_ACTION string.

SLD_SIM_ACTION The string has the following format:((time,type,value,length),(time,type,value,length),...

(time,type,value,length))where:time: A 32-bit value in milliseconds that represents the start time of the shift relative to the completion of the previous shift.type: A 4-bit value that determines whether the shift is a DR shift or an IR shift.value: The data associated with the shift. For IR shifts, it is a 32-bit value. For DR shifts, the length is determined by length.length: A 32-bit value that specifies the length of the data being shifted. This value should be equal to SLD_NODE_IR_WIDTH; otherwise, the value field may be padded or truncated. 0 is invalid.

Entries are in hexadecimal format.


Simulation Support

■ In a real system, each instance of the VJI works independently. In simulation, multiple instances can work at the same time. For example, if you define a scan shift for VJI instance number 1 to happen at 3 ms and a scan shift for VJI instance number 2 to happen at the same time, the simulation works correctly.

If you are using the ModelSim-Altera simulator, the altera_mf.v and altera_mf.vhd libraries are provided in precompiled form with the simulator.

The inputs and outputs of the VJI during a typical IR scan shift operation are shown in Figure 2–7.

Figure 2–7. IR Shift Waveform

The inputs and outputs of VJI during a typical DR scan shift operation are shown in Figure 2–8.


Getting Started

Figure 2–8. DR Shift Waveform

Compiling the Design

A design that contains instances of the VJI is no different from a regular compile flow with the Quartus II software. To compile your design, your project must have the variation file of all the different sld_virtual_jtag megafunctions in your HDL code. If your design entry is a netlist synthesized with a third-party synthesis tool, your project must have the Verilog Quartus Mapping (VQM) netlist and all the megafunction variation files that were instantiated in your HDL code. This megafunction cannot be inferred from HDL code. You must instantiate the sld_virtual_jtag megafunction in your design to create the virtual JTAG interface.

In a design, you can instantiate a maximum of 128 instances of the sld_virtual_jtag megafunction. After compilation, each instance has a unique ID, as shown on the Virtual JTAG Settings page of the Analysis & Synthesis section of the Compilation Report (Figure 2–9).


Compiling the Design

Figure 2–9. IDs of sld_virtual_jtag Instances

These unique IDs are necessary for addressing applications to properly address each instance of the megafunction.

The addition of sld_virtual_jtag megafunctions uses logic resources in your design. The Fitter resource section in the Compilation Report shows how many logic resources are utilized (Figure 2–10).


Getting Started

Figure 2–10. Logic Resources Utilized

f To learn more about compiling designs with the Quartus II software or about compilation flows, refer to volumes 2 and 3 of the Quartus II Handbook.

Third-Party Synthesis Support

In addition to the variation file, the MegaWizard Plug-In Manager creates a black box file for the VJI megafunction you created. For example, if you create a my_vji.v file, a my_vji_bb.v file is also created. In third-party synthesis, you include this black box file along with your design files to synthesize your project. A VQM file is usually produced by third-party synthesis tools. This VQM netlist and the sld_virtual_jtag megafunction's variation files are input to the Quartus II software for further compilation.


Design Example 1

Design Example 1

This design example uses the Virtual JTAG Interface megafunction to capture information from internal registers in a design. This example shows you how to implement the VJI in a design and how to use the quartus_stp executable to communicate with instances of the VJI megafunction in a design. The example uses the MegaWizard Plug-In Manager to create the instances used in this design.

Introduction

In this design example, the state machines consist of two synchronous counters that start counting from zero. The two counters are incremented every clock cycle, based on these expressions:

counter1 = counter1 + 1counter2 = counter1 + counter2 + 2

The design example uses two instances of the VJI and the quartus_stp executable to sample and update the contents of these counters.

During their operation, the two counters eventually reach a state where they have the same value. When both counters have the same value, they stop incrementing.

You use the quartus_stp executable and the VJI instances in the design to capture the event when both counters have the same value. You then feed a new seed value into both counters so they start incrementing again from that seed value.

In this example, you perform the following tasks:

■ Create two sld_virtual_jtag modules in Verilog HDL to be used in the design. The modules are instantiated in Verilog RTL.

■ Compile the design using the Quartus II software version 6.0 or later.■ Program the target hardware (FPGA) with the programming file.■ Run the Tcl scripts provided to sample and update contents of the

internal state machines.■ (optional) Simulate the sld_virtual_jtag megafunctions with

your design.

Design Files

The example design files are available in the Quartus II Projects section on the Design Examples page of the Altera website (www.altera.com).

Click Examples for sld_virtual_jtag Megafunction User Guide on the examples page to download the design files.


Getting Started

Requirements

This design example requires the following hardware and software:

■ Quartus II software version 6.0 or later running on a host computer with the Windows operating system on it

■ Any Altera development board or equivalent■ Altera download cable

Generate a sld_virtual_jtag Module

You can either create a new megafunction using the MegaWizard Plug-In Manager or use the existing sld_virtual_jtag modules contained in the design files provided at the Design Examples page.

To create an instance of the megafunction, perform the following steps:

1. On the Tools menu, click MegaWizard Plug-In Manager. The MegaWizard Plug-In Manager dialog box appears (Figure 2–11).


2. Select Create a new custom megafunction variation.

Click Next. Page 2a of the MegaWizard Plug-In Manager appears (Figure 2–12).


Design Example 1

Figure 2–12. MegaWizard Plug-In Manager, Page 2a

3. From the list of megafunctions, select Virtual JTAG.

4. Under Which device family will you be using?, select Cyclone II.

5. Under Which type of output file do you want to create?, select Verilog HDL.

6. Under What name do you want for the output file?, browse to your project’s directory and type my_vji_a.v



Getting Started


8. Set the width of the instruction register to 2.

9. Select Automatic for assigning a unique ID number to the instance of the megafunction.



Design Example 1


11. You specify the stimuli for the megafunction on page 4 of the wizard.

Enter the following values:

● Type of shift: IR-Shift● Length of delay: 1 ms● Hexadecimal value to shift: 0x1

Click Add Stimulus.

12. Similarly, add other DR and IR stimuli as shown in Figure 2–15. For DR shifts, set the number of bits you want to shift to 4.


Getting Started

Figure 2–15. MegaWizard Plug-In Manager, Page 4, With Stimuli Added for Module A



Design Example 1


14. Page 5 tells you that the altera_mf.v library is required to properly simulate the megafunction.

There is no input required from you on this page.

Click Next. Page 6 of the MegaWizard Plug-In Manager appears (Figure 2–17).


Getting Started


15. Click Finish to create the my_vji_a.v file.

The MegaWizard Plug-In Manager will also create the files that are checked on page 6.

16. Repeat steps 1-15 to create the my_vji_b.v file, which is the second module that is used in this design example. The only difference is that on page 4 of the wizard, when setting up the stimuli (step 11), specify time delays of 5, 1, 1, and 1 ms for the four stimuli (Figure 2–18).


Design Example 1

Figure 2–18. MegaWizard Plug-In Manager, Page 4, With Stimuli Added for Module B

With the two megafunctions in place and the design files downloaded, the project is ready to be compiled.

You can either make a new project or open the project dsgn_exmple_1.qpf. Note that the dsgn_exmple_1.qpf project has constraints for the Nios® II Cyclone™ II development board. If you use another development board or your own board, the constraints file must be regenerated or edited for the target board and hardware.

You can either start a new project in the Quartus II software version 6.0 or modify the pin constraints in the existing project. After the project compiles successfully, program the target device with the programming file that was generated. Alternatively, you can use the existing programming file produced for the Nios II Cyclone II development board.


Getting Started

When your device is configured, the operation starts and the internal counters begin counting.

Sampling & Updating the Contents of Internal State Machines

1 This example runs at about 1 Hz and uses a Nios II Cyclone II development board.

Before you proceed, make sure the Altera download cable is still connected to your hardware.

Get the Tcl script named my_test.tcl that is provided in the zip file as part of the design example. Run the script by typing the following command at a command prompt (Figure 2–19):

quartus_stp –t my_test.tcl r

Figure 2–19. Run the Tcl Script for Design 1

The script samples the internal contents of the state machines and displays them on the screen (Figure 2–20).


Design Example 1

Figure 2–20. Display the State Machine Contents

Sampling stops when both counters have the same value.

The script then asks you to enter a value that is fed to both counters in the design. This seed value now serves as the new starting point for the counters. (When the device started its first operation, both counters started counting from zero.)

The 7-segment LED modules on the development board display the contents of the counters during the operation.

When you run the Tcl script, the quartus_stp executable generates different sequences of IR and DR scan shift commands for the two VJI instances my_vji_a and my_vji_b. IR scan shifts load values into the IR of each VJI instance and DR scan shifts shift the data out from the counter registers. Note that the IR and DR shift commands for any VJI instance are run consecutively; they cannot happen simultaneously.


Getting Started

You can repeat the sequence with different starting values to see different results. The Tcl script provided runs three times. The loop variable in the script can be edited to run the script as many times as you want.

You can run the same design on a different development kit with an appropriate constraints file.

Simulation Support

When the design is communicating with the quartus_stp executable, various IR and DR scan shifts are performed. These scan shifts can also be simulated to see how the data flows inside the design. To simulate this example, you can use any Verilog HDL simulator with an appropriate megafunction library (for example, altera_mf.v) and design files.

While creating the Virtual JTAG Interface instances, you entered a few IR and DR scan shift commands for both instances. These IR and DR scan shifts are provided to show how the simulation works. They do not show all the results that you see when running the Tcl script. The Tcl script has many more IR and DR scan shift commands. To see all the hardware results that were generated while running the script, you must add the same sequence of IR and DR scan shift commands in Page 4 of the MegaWizard Plug-In Manager (refer to Figure 2–15 on page 2–25).

When simulating the design files with the simulator, be sure to add +define+SIM to your run scripts or command line. These options create a clock faster than 1 Hz, so the simulation time does not have to be very long to update the internal state machines (counters). In simulation mode, the internal clock is switched to 3.3 MHz. Additionally, +define+SIM initializes the counters to a known value at the start of the simulation.


Design Example 2

Design Example 2

This design example shows you how to use the Virtual JTAG Interface megafunction to capture information from internal state machines running at system speed. It shows you how to implement the VJI in a design and how to use the quartus_stp executable to communicate with instances of the Virtual JTAG Interface in a design.

Introduction

This design example consists of two internal counters and a dual port RAM. The counter counter1 contains the address for the RAM and the counter counter2 contains the data for the RAM. One port of the RAM is used to write to the RAM at system speed. The second port is used by the sld_virtual_jtag instance to read the RAM contents. Both counters increment by predetermined amounts that do not change during the operation. Therefore the RAM contents are written repeatedly with the same values of counter2. The address pointer to this RAM, which is counter1, also does not change.

This example demonstrates how the quartus_stp executable and the Virtual JTAG Interface are used to retrieve the data from the RAM and write it to a file system.

In this example, you use the quartus_stp executable and VJI instances in the design to read the contents of the RAM inside the design. You will perform the following tasks:

■ Create a sld_virtual_jtag module in Verilog HDL to be used in the design

■ Compile the design using the Quartus II software version 6.0 or later■ Program the target hardware (FPGA) with the programming file■ Run the Tcl script provided to read the contents of the RAM

Design Files

The example design files are available in the Quartus II Projects section on the Design Examples page of the Altera website (www.altera.com).

Click Examples for sld_virtual_jtag Megafunction User Guide on the examples page to download the design files from the Altera internet website.

Requirements

This design example requires the following hardware and software:

■ Quartus II software version 6.0 or later running on a host computer with the Windows operating system on it


Getting Started

■ Any Altera development board or equivalent■ Altera download cable

Generate a sld_virtual_jtag Module

You can either create a new instance of the megafunction using the MegaWizard Plug-In Manager or use the existing sld_virtual_jtag modules contained in the design files provided at the Design Examples page.

To create the instance used in this design example, repeat the steps in “Generate a sld_virtual_jtag Module” on page 2–21, but name the new instance my_vji.v. Because no simulation is performed in this design example, you can skip the stimulus part of the MegaWizard Plug-In Manager. When prompted to enter the stimulus, click Next to advance to the next page in the wizard.

You can either make a new project or open the project dsgn_exmple_2.qpf. Note that the dsgn_exmple_2.qpf project has constraints for the Nios II Cyclone II development board. If you want to use another development board or your own board, the constraints file must be regenerated or edited for the target board and hardware. If you make a new project or open an existing project from the design example directory, you must compile the project. If you do not want to compile the project, you can use the programming file in the design example directory (note that this programming file is for the Nios II Cyclone II development board from Altera).

Reading the Contents of a Counter Captured in a RAM

After compiling and configuring the device, run the Tcl script by typing the following command at a system command prompt:

quartus_stp –t my_test.tcl r

The Tcl script consists of Tcl commands that communicate over the JTAG port with the sld_virtual_jtag megafunction and the device logic.

The loop called LOOP reads and writes the contents of the memory addresses specified by the lower_limit and upper_limit values to a file named dump.hex. By default, the lower limit is 10 and the upper limit is 19. You can change the lower_limit and upper_limit values in the Tcl script with any text editor.

When you run the script, the output is as shown in Figure 2–21.


Design Example 2

Figure 2–21. Capture the RAM Data


Getting Started

Conclusion The sld_virtual_jtag megafunction gives you the ability to create your own software solution for monitoring, updating, and debugging your designs through the JTAG port without using any I/O pins on the device. It allows you to instrument your design for efficient, fast, and productive debugging solutions. These debugging solutions can be part of an evaluation test where you use other logic analyzers to debug your design or as part of a production test where you do not have a host running an embedded logic analyzer. In addition to helping in debugging, the sld_virtual_jtag megafunction can be used to provide a single channel or multiple serial channels through the JTAG port of the device. These serial channels can be used in many applications to capture data or to force data to various parts of your logic.


Design Example 2



3. Specifications

Ports & Parameters

The tables in this section describe all of the ports and parameters that are available for the sld_virtual_jtag megafunction.

Table 3–1 shows the input ports. Table 3–2 shows the output ports. Table 3–3 shows the parameters for the sld_virtual_jtag megafunction.

Table 3–1. sld_virtual_jtag Input Ports

Port Name Description Comments

tdo Write to the TDO pin on the device when the virtual JTAG is in Shift_DR state.

ir_out[] Write to the virtual JTAG instruction register. The value is captured every time when virtual_state_cir is high.

ir_out[SLD_IR_WIDTH – 1 .. 0] wide

Table 3–2. sld_virtual_jtag Output Ports (Part 1 of 3)


tck JTAG test clock. This port is connected to the TCK pin on the device directly. Shared among all instances.

tdi TDI input data on the device used when the virtual JTAG is in Shift_DR state.

Shared among all instances.

ir_in[] Virtual JTAG instruction register data.

Ir_in[SLD_IR_WIDTH-1..0] The value is available and latched when the virtual JTAG is in Update_IR state.

High-level Virtual JTAG State Signal

virtual_state_cdr Indicates that virtual JTAG is in Capture_DR state.

virtual_state_sdr Indicates that virtual JTAG is in Shift_DR state.

At this state, this instance is required to establish the JTAG chain for this device.

virtual_state_e1dr Indicates that virtual JTAG is in Exit1_DR state.

virtual_state_pdr Indicates that virtual JTAG is in Pause_DR state.

Quartus II software does not cycle through this state.


Ports & Parameters

virtual_state_e2dr Indicates that virtual JTAG is in Exit2_DR state.

Quartus II software does not cycle through this state.

virtual_state_udr Indicates that virtual JTAG is in Update_DR state.

virtual_state_cir Indicates that virtual JTAG is in Capture_IR state.

virtual_state_uir Indicates that virtual JTAG is in Update_IR state.

Low-level Device JTAG State Signal

jtag_state_tlr Indicates that the device JTAG controller is in the Test_Logic_Reset state.

Shared among all instances

jtag_state_rti Indicates that the device JTAG controller is in the Run_Test/Idle state.


jtag_state_sdrs Indicates that the device JTAG controller is in the Select_DR_Scan state.


jtag_state_cdr Indicates that the device JTAG controller is in the Capture_DR state.


jtag_state_sdr Indicates that the device JTAG controller is in the Shift_DR state.


jtag_state_e1dr Indicates that the device JTAG controller is in the Exit1_DR state.


jtag_state_pdr Indicates that the device JTAG controller is in the Pause_DR state.


jtag_state_e2dr Indicates that the device JTAG controller is in the Exit2_DR state.


jtag_state_udr Indicates that the device JTAG controller is in the Update_DR state.


jtag_state_sirs Indicates that the device JTAG controller is in the Select_IR_Scan state.


jtag_state_cir Indicates that the device JTAG controller is in the Capture_IR state.


jtag_state_sir Indicates that the device JTAG controller is in the Shift_IR state.





Specifications

jtag_state_e1ir Indicates that the device JTAG controller is in the Exit1_IR state.


jtag_state_pir Indicates that the device JTAG controller is in the Pause_IR state.


jtag_state_e2ir Indicates that the device JTAG controller is in the Exit2_IR state.


jtag_state_uir Indicates that the device JTAG controller is in the Update_IR state.


tms TMS input pin on the device. Shared among all instances

Table 3–3. sld_virtual_jtag Parameter Description

Parameter Type Comments

SLD_AUTO_INSTANCE_INDEX String Specifies whether the instance index is automatically assigned by the compiler. Values are YES or NO. When NO is specified, the auto assigned value of INSTANCE_ID can be found in the report file of quartus_map. When NO is specified, INSTANCE_INDEX must be defined. If the index specified is not unique in a design, the index is reassigned automatically by the compiler. The default is YES.

SLD_INSTANCE_INDEX Integer Specifies a unique identifier for every instance of the sld_virtual_jtag megafunction when AUTO_INSTANCE_ID is specified to YES. Otherwise, this value is ignored.

SLD_IR_WIDTH Integer Specifies the width of the instruction register of this virtual JTAG between 1 and 32. If omitted, the default is 1.




Ports & Parameters


Documents

sld virtual jtag Megafunction User Guide - Digchipapplication-notes.digchip.com/038/38-21643.pdf · example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such