SISSA Trieste AMD and SUN Roberto Dognini Business Development Enterprise Manager Trieste, 22 Novembre 2004

SISSA TriesteAMD and SUN

Roberto DogniniBusiness Development Enterprise Manager

Trieste, 22 Novembre 2004

Trieste22 Novembre 2004

2

AMD Overview

A leading global supplier of innovative semiconductor solutions for the personal and enterprise computing,

communications and consumer electronic markets

Founded: 1969

Headquarters: Sunnyvale, California

Employees: 15,000 worldwide

Sales Mix: 80% international

2003 Revenue: $3.5 billion

2004 Q2 Revenue: $1.262 billion

• Flash Memory: $673 million

• Microprocessors: $554 million

• Other: $34 million


3

AMD’s Extensive Processor History

8080A

Second source microprocessors

1975

19911982

1995

1993

1997

20031999

1979

8086286Am386

Am486

K5™

2001


4

AMDAn Innovation Powerhouse

AMD

1,090

1,055

825

* Technology Patents in 2002Source: IFI Claims, 2003

Year

2001

2000

1999

Rank Company U.S. Patents*

1 IBM3,333

2 CANON 1,895

3 NEC 1,833

3 MICRON 1,833

5 HITACHI 1,6166 MATSUSHITA 1,5667 SONY

1,4568 GE

1,4179 MITSUBISHI 1,40810 SAMSUNG 1,32911 FUJITSU

1,26312 TOSHIBA

1,17113 AMD

1,15414 INTEL

1,08015 HP

1,06516 PHILIPS

84817 MOTOROLA 73618 TI

72419 XEROX

70120 FUJI

695

Intel

811

797

735


5

An industry defining moment.

Joining 20 years of enterprise expertise with industry standard economics,

targeting the delivery of high performance systems at accessible

prices.

More Than A Product Announcement


6

Building the AMD64 EcosystemAMD and SUN

Key independent software vendors are already embracing the Sun and AMD Opteron processor-based offering as the standard in network computing: BEA Systems, Cadence Design Systems, Inc., Computer Associates,

Documentum, MatrixOne Inc., Oracle, Synopsys, Inc., and SAP AG.

http://www.amd.com/us-en/assets/content_type/DownloadableAssets/AMD64_ecosystem_final.pdf


7

Key Architecture Innovations

•AMD’s Eighth Generation processor integrates key system elements:

Integrated DDR memory controller

Next generation core

HyperTransport™ technology

L2Cache

L1Instruct.

Cache

L1Data

Cache

X86 32-64Processor

Core

HyperTransport™ technology

DDR Memory Controller

“Hammer” Architecture


8

Building a Bridge from the 32- to the 64-bit World

• Adds 64-bit capabilities to the world’s highest performing 32-bit core for 2P and 4P servers

• Provides investment protection for users who have invested in 32-bit application software

• Current 32-bit applications will work on today’s 32-bit operating systems as well as tomorrow’s 64-bit operating systems

–Windows XP, Windows 2000–Windows (with AMD64 compatibility)–Windows Server 2003–Linux for x86, Linux for AMD64

• Enables a gradual application transition to 64-bits as required by end-user individual needs

• Doesn’t require special hardware or investment in a proprietary infrastructure

32-bit Operating

System

64-bit Operating

System

32-bit Applications

32-bit Applications

64-bit Applications


9

Intel Xeon Processor-based ServerAMD Opteron™ Processor-based Server

IntelIntelXeonXeon

ProcessorProcessor

IntelIntelXeonXeon

ProcessorProcessor

MemoryCtlr Hub(MCH)1

MemoryCtlr Hub(MCH)1

I/OHub3

I/OHub3 PCI

PCI-X

IDE, USB,LPC, Etc.

PCI-XBridge2

PCI-XBridge2

I/O & Memory Share FSB

Memory Access Delayed By Passing Through MCH

Bandwidth Bottlenecks:Link Bandwidth < I/O Bridge BandwidthMore Chips

Needed for Basic Server

IntelIntelXeonXeon

ProcessorProcessor

IntelIntelXeonXeon

ProcessorProcessor

DDR144-bit

*AMD-8131™ HyperTransport PCI-X Tunnel **AMD-8111™ HyperTransport I/O Hub

AMDAMDOpteron™Opteron™

ProcessorProcessor

AMDAMDOpteron™Opteron™

ProcessorProcessor

PCI-XBridge*

PCI-XBridge*

I/OHub**

I/OHub**

PCI

PCI-X

IDE, USB,LPC, Etc.

DDR144-bit

HyperTransport™ Technology Buses for Glueless I/O or CPU Expansion

Separate Memory andI/O Paths Eliminates Most Bus Contention

HyperTransportLink Has Ample Bandwidth For I/O Devices

Fewer Chips NeededFor Basic Server (Reduces Cost)

AMDAMDOpteronOpteronProcessorProcessor


DDR144-bit

KeyMemory TrafficI/O TrafficIPC Traffic


Arc

hite

ctur

eM

emor

y A

cces

s Te

chno

logy

Prim

ary

Bus

Te

chno

logy

Memory CapacityScales w/ Numberof Processors

Second Processor Competes for FSB Bus Bandwidth

AMD Opteron™ Processor-based Server Intel Xeon Processor-based Server

AMD64 Architecture

• Enables simultaneous high-performance 32- and 64-bit computing

• Allows businesses to migrate to 64-bit computing as they require

IA32 Architecture

• High-performance 32-bit computing only

• Businesses needing 64-bit benefits must switch to a new architecture

Integrated DDR Memory Controller

• Dramatically reduces latency for fast memory reads

• Provides a dedicated path from memory to processor

• Memory bandwidth scales as processors are added

• Helps eliminate need for larger caches

• “Northbridge”-style Memory Controller via Front Side Bus

• Passage through memory controller hub delays memory reads

• Processors compete for FSB bandwidth

• Memory and I/O must share FSB bandwidth, further reducing the efficiency of the FSB

HyperTransport™ Technology

• At up to 6.4 GB/s bandwidth per link, HyperTransport provides sufficient bandwidth for supporting new and existing interconnects including Fibre Channel, Gigabit Ethernet, PCI-X, PCI-X 2.0, Serial-ATA, Serial Attached SCSI and 10G Ethernet

Proprietary Hub I/O Buses

• PCI-X bridge’s2 hub interface has only half the peak bandwidth of the two PCI-X bridges

• I/O Hub3 interface bus can be overloaded by the aggregate demands of its many I/O devices

AMD, the AMD Arrow logo, AMD Opteron and combinations thereof, and AMD-8111 and AMD-8131 are trademarks of Advanced Micro Devices, Inc. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium. Other product and company names used herein may be trademarks of their respective companies.

1 Intel E7500 Chipset Memory Controller Hub (MCH) 2 Intel 82870P2 64-bit PCI/PCI-X Controller Hub 2 (P64H2)

3 Intel 82801CA I/O Controller Hub 3-S (ICH3-S)


10

AMD Opteron Processor-based Server• AMD64 Architecture: provides simultaneous high-performance

32-bit and 64-bit computing. Scales to 8P without glue logic.• Integrated Memory Controller: provides low-latency memory

access and bandwidth that scales as processors are added.• HyperTransport Technology: at up to 6.4GB/s bandwidth per

link, designed to provide a high-speed connection between processors and core logic with sufficient bandwidth for supporting new and existing interconnects.

AMD Opteron™ Processor-based Server Intel Xeon MP Processor-based Server



HyperTransport™ Technology Buses for Glueless I/O or CPU Expansion

HyperTransport™ Technology Buses Enable Glueless Expansion for up to 8-way Servers

Separate Memory andI/O Paths Eliminates Most Bus Contention

HyperTransportLink Has Ample Bandwidth For I/O Devices

Memory CapacityScales w/ Numberof Processors

PCI-XBridge *

PCI-XBridge *

PCI-X

OtherBridge

OtherBridge

OtherI/O

AMDAMDOpteronOpteron™™

ProcessorProcessor

AMDAMDOpteronOpteron™™

ProcessorProcessor



DDR144-bit





DDR144-bit

DDR144-bit

DDR144-bit

PCI-XBridge

PCI-XBridge

I/OHub**

I/OHub**

IDE, USB,LPC, Etc.

FSB Bus Bandwidth Shared Across All Four Processors

I/O & Memory Share FSB

Bandwidth Bottlenecks:Link Bandwidth < I/O Bridge Bandwidth

9-Chip Chipset Needed for 4-way Server

IntelIntelXeonXeon

ProcessorProcessor

IntelIntelXeonXeon

ProcessorProcessor

IntelIntelXeonXeon

ProcessorProcessor

IntelIntelXeonXeon

ProcessorProcessor

IntelIntelXeonXeon

ProcessorProcessor

IntelIntelXeonXeon

ProcessorProcessor

IntelIntelXeonXeon

ProcessorProcessor

IntelIntelXeonXeon

ProcessorProcessor

I/OHub3

I/OHub3

PCIIDE, FDC,USB, Etc.

PCI-XPCI-XBridge2

PCI-XBridge2

MemoryCtlr Hub(MCH) 1

MemoryCtlr Hub(MCH) 1

PCI-XPCI-XBridge

PCI-XBridge

PCI-XPCI-XBridge

PCI-XBridge

DDR144-bit

MemoryAddressBuffer4

MemoryAddressBuffer4

Maximum of Four Processors per Memory Controller Hub

Maximum of Three PCI-X Bridges per Memory Controller Hub

Limited Memory Bandwidth Shared by AllMemory

AMD, the AMD Arrow logo, AMD Opteron and combinations thereof, and AMD-8111 and AMD-8131 are trademarks of Advanced Micro Devices, Inc. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium. Other product and company names used herein may be trademarks of their respective companies.

*AMD-8131™ HyperTransport PCI-X Tunnel **AMD-8111™ HyperTransport I/O Hub1 ServerWorks CMIC HE Memory Controller Hub (MCH) 2 ServerWorks CIOB-X 64-bit PCI/PCI-X Controller Hub

3 ServerWorks CSB5 I/O Controller Hub 4 ServerWorks REMC Memory Address Buffer

Intel Xeon MP Processor-based Server• IA32 Architecture: provides high-performance 32-bit

computing only—does not offer 64-bit benefits.• “Northbridge”-based Memory Controller: All four

processors compete for fixed memory and front-side bus bandwidths—8P solutions require even more chips.

• Proprietary Hub I/O Buses: bridge and hub devices can be overwhelmed by the I/O demands of attached peripherals.

MemoryAddressBuffer

MemoryAddressBuffer

DDR144-bit

DDR144-bit

MemoryAddressBuffer

MemoryAddressBuffer

MemoryAddressBuffer

MemoryAddressBuffer

DDR144-bit

Fewer Chips Needed for 4-way Server (Reduces Cost)

11

Scalable Memory Bandwidth and IOScalable Memory Bandwidth and IOOpteron’s on die IO controllerOpteron’s on die IO controller

SystemSystemRequestRequestQueueQueue

CPU 0CPU 0CPU 1CPU 1

DDR MemoryDDR Memory

IO HT LinkIO HT Link

CrossbarCrossbar

CPU-CPU HT LinkCPU-CPU HT Link

CPU-CPU HT LinkCPU-CPU HT Link6.46.4 GB/sGB/s

6.46.4 GB/sGB/s

6.4 – 8.06.4 – 8.0 GB/sGB/s

6.4 – 8.06.4 – 8.0 GB/sGB/s

25.6 – 28.825.6 – 28.8GB/sGB/s

1.6 – 2.0 1.6 – 2.0 GT/sGT/s coherentcoherent

1.6 1.6 GT/sGT/s non-coherentnon-coherent

Dual channelsDual channelsto DDR Memoryto DDR Memory

AMD Opteron™ Processor ServerAMD Opteron™ Processor Server Intel Xeon MP Processor ServerIntel Xeon MP Processor Server



HyperTransport™ Technology HyperTransport™ Technology Buses for Glueless I/O or CPU Buses for Glueless I/O or CPU ExpansionExpansion

HyperTransport™ Technology HyperTransport™ Technology Buses Enable Glueless Buses Enable Glueless Expansion for up to 8-way Expansion for up to 8-way ServersServers

Separate Memory andSeparate Memory andI/O Paths Eliminates Most I/O Paths Eliminates Most Bus ContentionBus Contention

HyperTransportHyperTransportLink Has Ample Link Has Ample Bandwidth For Bandwidth For I/O DevicesI/O Devices

Memory CapacityMemory CapacityScales w/ NumberScales w/ Numberof Processorsof Processors

PCI-XBridge *

PCI-XBridge *

PCI-X

OtherBridge

OtherBridge

OtherI/O

AMDOpteron™Processor

AMDOpteron™Processor

AMDOpteron

Processor

AMDOpteron

Processor

DDR144-bit144-bit

AMDOpteron

Processor

AMDOpteron

Processor

AMDOpteron

Processor

AMDOpteron

Processor

PCI-XBridge

PCI-XBridge

I/OHub**

I/OHub**

IDE, USB,LPC, Etc.

FSB Bus Bandwidth Shared Across FSB Bus Bandwidth Shared Across All Four ProcessorsAll Four Processors

I/O & Memory Share FSBI/O & Memory Share FSB

Bandwidth Bottlenecks:Bandwidth Bottlenecks:Link Bandwidth < I/O Bridge Link Bandwidth < I/O Bridge BandwidthBandwidth

IntelXeon

Processor

IntelXeon

Processor

IntelXeon

Processor

IntelXeon

Processor

IntelXeon

Processor

IntelXeon

ProcessorIntelXeon

Processor

IntelXeon

Processor

I/OHub3

I/OHub3

PCIIDE, FDC,USB, Etc.

PCI-XPCI-XPCI-XBridgeBridge22

PCI-XPCI-XBridgeBridge22

MemoryMemoryCtlr HubCtlr Hub(MCH)(MCH)

MemoryMemoryCtlr HubCtlr Hub(MCH)(MCH)

PCI-XPCI-XPCI-XBridgeBridge

PCI-XPCI-XBridgeBridge

PCI-XPCI-XPCI-XBridgeBridge

PCI-XPCI-XBridgeBridge

MemoryMemoryAddressAddressBufferBuffer


Maximum of Four Processors Maximum of Four Processors per Memory Controller Hubper Memory Controller Hub

Maximum of Three Maximum of Three PCI-X Bridges per PCI-X Bridges per Memory Controller Memory Controller HubHub

Limited Memory Limited Memory Bandwidth Bandwidth Shared by Shared by AllAllMemoryMemory





MemoryAddressBuffer

MemoryAddressBuffer

DDR144-bit144-bit

DDR144-bit144-bit

DDR144-bit144-bit

DDR144-bit144-bit

DDR144-bit144-bit

DDR144-bit144-bit

DDR144-bit144-bit

4 Separate IO Channels per CPU – 4 Separate IO Channels per CPU – Scalable SMP BandwidthScalable SMP Bandwidth

HyptertransportHyptertransportTMTM Interconnect – Interconnect – low SMP memory latencylow SMP memory latency

Commodity/High Performance SMP SolutionCommodity/High Performance SMP Solution

presently dual core ready – SRQ controller has port for 2presently dual core ready – SRQ controller has port for 2ndnd core core

fewer # of chips required for MP chipsets – lowering cost of SMP systemsfewer # of chips required for MP chipsets – lowering cost of SMP systems

6.4 GB/s6.4 GB/s6.4 GB/sXeonEMT

115.2 GB/s41.6 GB/s12.8 GB/sOpteron

4P2P1PArchitectureArchitecture

> 200 ns~200 ns80 nsXeonEMT

110 ns75 ns50 nsOpteron

4P2P1PArchitectureArchitecture

12

ACML – AMD’s superior equivalent of MKLACML – AMD’s superior equivalent of MKL

Compilers – PGI performance enhancementsCompilers – PGI performance enhancements

Speed up Opteron Architecture

Documents

SISSA Trieste AMD and SUN Roberto Dognini Business Development Enterprise Manager Trieste, 22 Novembre 2004