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Sensors and Actuators A 188 (2012) 481– 488

Contents lists available at SciVerse ScienceDirect

Sensors and Actuators A: Physical

jo u rn al hom epage: www.elsev ier .com/ locate /sna

ingle-device “XOR” and “AND” gates for high speed, very low power LSIechanical processors

aisal K. Chowdhurya, Daniel Saabb, Massood Tabib-Azara,∗

University of Utah, Salt Lake City, UT, USACase Western Reserve University, Cleveland, OH, USA

r t i c l e i n f o

rticle history:eceived 31 August 2011eceived in revised form 26 April 2012ccepted 3 May 2012vailable online 19 May 2012

eywords:EMS microprocessors

a b s t r a c t

Here we demonstrate the feasibility of micro-electro-mechanical system (MEMS) functional deviceswhere a single device functions as a logic gate. This novel approach reduces the number of MEMS devicesneeded to implement a mechanical processor by a factor of 10. MEMS processors are suitable for opera-tion in harsh environment in engines and in the presence of ionizing radiations inside nuclear reactors orin space applications. MEMS devices have overall lower speed and are less reliable than the complemen-tary metal-oxide-semiconductor (CMOS) devices. By reducing the number of devices needed for a givenoperation, our approach improves yield, reproducibility, speed and simplifies implementation of MEMS

EMS logic gateEMS processors

adiation-hard devicesEMS XOR gateEMS AND gate

circuits such as adders and multiplexers. Specifically, we discuss XOR and AND gates fabricated on Si3N4

and polysilicon as bridge materials using W electrodes. The XOR gates with ∼1.5 V turn-on voltage at50 MHz with >109 cycles of reliable operations and low operational power consumption (leakage current<10−9 A at V ∼ 0.5 V, and power <1 �W) were tested. We also present data showing the operation of XORwithout deterioration at high temperature and in 90 kW ionizing radiation for 120 min. Related circuitssuch as a 2-bit full adder and a multiplexer are also discussed.

. Introduction

Simple micro-electro-mechanical on/off switches have beeneported in the past for applications in processors and to addressower management in very large scale integrated circuits (VLSI),rogramming interconnect in field-programmable gate arraysFPGAs), biomedical devices where it is desirable to reduce leakageower to prolong implanted battery life, and other applications inarsh environment where CMOS cannot operate due to high tem-erature or radiation [1–9]. One such case includes operation in theresence of ionizing radiation in troubled reactors like Chernobylnd Fukushima or at high temperatures encountered inside com-ustion engines. In these cases silicon channel in CMOS becomesighly conductive due to thermal generation of carriers or due to

attice defect generation caused by radiation over prolonged expo-ure [1]. Space applications also require radiation-hard devices andaterials. In some electronic materials such as SiC, the energy

equired to produce lattice defects is high enabling these materialso withstand ionizing radiations longer than Si. In other materials

uch as InP, defects heal at relatively low temperatures enablingnP devices to recover quickly.

∗ Corresponding author.E-mail address: M.Tabib-Azar@utah.edu (M. Tabib-Azar).

924-4247/$ – see front matter © 2012 Elsevier B.V. All rights reserved.ttp://dx.doi.org/10.1016/j.sna.2012.05.005

© 2012 Elsevier B.V. All rights reserved.

Nano-electromechanical systems (NEMS) and MEMS devicesare based on mechanical elements that are inherently insensitiveto ionizing radiation that creates lattice defects in these devicesbut these defects do not alter their characteristics the way theyaffect channel resistance in CMOS. Eventually large defect densi-ties created over extended exposure leads to embrittlement thatmay affect NEMS/MEMS electrical and switching characteristics.NEMS/MEMS devices also have very low leakage power makingthem very desirable in biomedical implant devices or other appli-cations requiring very long battery lifetime.

Despite their very high off-to-on resistance (100 G � to 10 m �)ratios, and very low off-state leakage currents (<10−14 A), MEMSswitches tend to be slow (<1 MHz), large (>40 �m2), and unreliablewith limited lifetime of ∼106 operation cycles [1–4]. In addi-tion, MEMS/NEMS switches have many interesting and challengingissues including: (a) contact reliability, (b) stiction problem relatedto release during fabrication and micro-welding during hot-contactoperation, (c) reliability of their flexure structures and (d) particu-late problems that occur during repeated operations that can leadto switch failure. To address some of these issues, our approachduring the last two years have shifted from the CMOS paradigmthat uses complementary switches for implementing logic gates

to single functional structures creating a single-device logic plat-form for improved characteristics. These devices are based on acomposite Si3N4/polysilicon cross-bridge platform with metal con-tacts designed to provide AND or XOR functionality. The following

482 F.K. Chowdhury et al. / Sensors and Ac

Fig. 1. Schematic of MEMS single-device XOR gate. Only the central regions of thebridges are shown. The metallization patterns at the top surface of the bottom bridge(a(

spa

2

ofaawacaIatoTtb

Fg

Gate 2 and source) and at the bottom surface of the top bridge (Gate 1 and drain)re matched so that when the two bridges contact each other, the intended functionXOR in this case) is executed.

ections elaborate on the functional structure design, fabricationrocess and the results of testing these novel single device XORnd AND gates.

. Functional structure design

The cross-bridge platform shown in Fig. 1 forms the basis forur single-device logic gates. It illustrates the electrode designor an XOR gate where metal traces overlap at the intersectionrea of the two bridges. The bridges are actuated by electrostaticttraction between the gate electrodes on the opposite bridges thathen contact each other result in the drain and source electrodes,

lso on opposite bridges, to contact each other. Other logic gatesan be constructed using similar structures with different met-llization/contact patterns as shown in Fig. 2 for an “AND” gate.n Fig. 2, the cross-sectional view of the XOR and AND devicere shown along with their truth table. The XOR diagram hashe two bridges with different electrodes labeled as “Gate 1” thatverlaps with “Gate 2” and “Drain” that overlaps with “Source”.

he “AND” diagram has “Gate 1a” and “Gate 1b” on the bottom ofhe top bridge and “Gate 2a” and “Gate 2b” on the top of the bottomridge.

ig. 2. Cross-section of XOR and AND gates. The truth tables corresponding to XORate and AND gate operation.

tuators A 188 (2012) 481– 488

From Fig. 2, XOR diagram it can be seen that when both Gate1 and Gate 2 are low (“00”) or when both are high (“11”) there isno electrostatic attraction. When either one of the gates are high(“10” or “01”), electrostatic attraction between the two gates causesthe bridges to attract and touch each other enabling the drain andsource electrodes to contact each other. The truth table of XOR isshown in Fig. 2.

A minor modification of the electrode design of the XOR gateproduces AND gate as shown in Fig. 2. The AND gate requires bothinput to be high for the output to be high. Any other combinationsof the input values produce low output. To realize AND functional-ity, we split the Gate 1 and Gate 2 in the XOR structure each intotwo gates: Gates 1a, Gate 1b, Gate 2a, and Gate 2b, respectively.We then ground Gate 2a and Gate 2b. When both Gate 1a andGate 1b are high, the combined electrostatic attraction betweenGate 1a – Gate 2a and Gate 1b – Gate 2b is large enough to over-come the elastic restoring force of the two bridges and the bridgescontact each other. Thus, the drain and source electrodes contacteach other resulting in AND operation. Any other combinationsof voltages on Gate 1a and Gate 1b, do not result in attractionbetween the bridges. The truth table for AND is shown in Fig. 2.We note that for AND gate we could keep Gate 2 intact withoutsplitting. In our implementation of AND gate we actually did notsplit Gate 2 but we thought it is important to discuss its possi-ble splitting to enable more symmetric and generalized thinkingabout other possible logic gates or functional devices not discussedhere.

To prevent the drain-source electrodes from causing the attrac-tion between the two bridges, their overlapping area is designedto be 4 times smaller than that of the gate electrodes in the XORgate. Similar approaches will also reduce the possibility of drain tosource voltage actuating the bridges in AND and other logic gates.The gate electrodes in these logic gates also touch each other. Toprevent gate–gate leakage current, the gate electrodes should becovered with an appropriate insulator.

The design and fabrication of XOR and AND logic gates is dis-cussed in the following two sections. Other gates such as NANDand NOT can also be realized in a similar manner. An XOR gate canbe converted to NOT gate by fixing one of its inputs at “1”. A NANDgate can be produced by NOT(AND) or by using different electrodeconfiguration on the bridges.

In both XOR and AND gates, the gate electrodes are coated witha thin insulator (atomic layer deposited Al2O3) to prevent dc con-duction when they contact each other. To prevent drain-sourcevoltages from actuating the bridges, we intentionally chose thegate overlap areas 4 times larger than the drain-source overlapareas.

Fig. 3 shows optical images of the XOR and AND gates. Thecommon implementation of XOR using 8 individual switches ascommonly used in CMOS implementation of XOR is shown in Fig. 4[10]. The factor 8 reductions in device count and associated reduc-tions in number of moving parts and areas lead to 8 times betterreliability, at least 4 times faster overall logic gate speed and pro-portionately higher yields.

We also note that multi-input (>2) gates can also be designedusing the cross-bridge geometry with two or more metal tracesfor multiple contact electrodes. A 4-input XOR gate will reduce thedevice count by ×24.

3. Design calculations

Based on mathematical models of fixed-fixed MEMS beams dis-cussed in [11], switching time (ts), resonant frequency (f0) and pull

F.K. Chowdhury et al. / Sensors and Ac

Fig. 3. (a) Fabricated XOR gate. G1 and G2 are gate electrodes. S and D representSource/Drain. (b) Fabricated AND gate. S–D will connect only if gates 1a and 1b arehigh at the same time.

S

G

D

S

G

D

S

G

D

S

G

D

D

G

S

D

G

S

D

G

S

D

G

S

B B

B B

B B

B B

Vdd

Abar B

Bbar

AbarB

Gnd

A Outp ut

Fig. 4. XOR implemented using individual CMOS switches require 8 devices each25 �m2 while our single XOR device requires only 25 �m2 area.

tuators A 188 (2012) 481– 488 483

down voltages (Vp) were calculated for various thicknesses of sili-con nitride, polysilicon and tungsten:

ts = 3.67Vp

Vsw0(1)

where Vs is the switching voltage, ω0 = 2�f0 and the resonant fre-quency f0 is given by:

f0 = 12�

√ka

m(2)

and the pull-down voltage is given by:

Vp = VS

(2g0

3

)=

√8ka

27ε0Wwg3

0� (3)

with the overall spring constant ka given by:

ka = k′a + k′′

a = 32Ew(

t

l

)3 (2749

)+ 8�(1 − v)w

(t

l

) (35

)(4)

where, k′a is the constant component due to material factors, k′′

ais the spring constant component due to biaxial residual stress,E is the Young’s Modulus, l is the bridge length, w is the bridgewidth, W is the width of the electrostatically active portion of thepull down electrode (therefore, area of pull down electrode = Ww),t is the bridge thickness, � is the biaxial residual stress, � is thePoissons ratio, ε0 is the permittivity of free space, g0 is the gapheight between two bridges, m is the effective bridge mass, Va isthe applied voltage and � is a scale factor that accounts for bothbridges moving toward each other. One can show that � is 1/

√2.

Fig. 5 shows plots of the switching time, resonant frequency,and the pull-down voltage for different bridges. It can be seen fromFig. 5(a) that silicon nitride bridges have faster switching speedsthan polysilicon or tungsten bridges with l = 30 �m and w = 15 �m.This is mainly due to the large built-in stress of the nitride layer dur-ing deposition. It was experimentally observed that silicon nitridebridges alone could not withstand fabrication process and had tobe reinforced with a thin layer of polysilicon.

Actuation voltages were also calculated and are shown inFig. 5(c). It can be seen that sub-one volt actuation is possible withthe combination of bridge dimensions and g0 ∼ 10 nm.

4. Fabrication

The fabrication process flow is given in Fig. 6. The conduct-ing silicon wafer was insulated with 100 nm LPCVD stoichiometricsilicon nitride deposited at 780 ◦C, first tungsten layer (thickness100 nm) sputtered uniformly and patterned to form a “stationary”ground electrode. This electrode was used both as a gate in “MOS-FET” like operation of the device and to separate the two bridgeswhen needed. The tungsten layer was then capped with 100 lay-ers (∼0.1 nm/layer) of thermal Al2O3 deposited using Fiji AtomicLayer Deposition (ALD) system and low-pressure chemical vapordeposited (LPCVD) nitride (100 nm) and patterned to form the firstbridge. In step 6, the second layer of tungsten was sputtered andpatterned to form the electrodes on the first bridge. ALD Al2O3was subsequently used to cap the patterned tungsten and also asthe sacrificial gap between bottom and top electrode-bridges. Thiswas followed by the third tungsten metallization and patterning todeposit the electrodes that reside under the second nitride bridge.Then, another patterned nitride layer was used to define the topbridge. After fabricating the whole structure that required 8 masks,the ALD layers were sacrificially etched in buffered oxide etch (BOE)

etchant to “free” the two bridges from each other and from the sub-strate. H2O2 at room temperature was used as the wet etchant topattern tungsten resulting in a clean and uniform etch all over thewafer. Silicon nitride was pattered using a dry etch recipe of CF4/O2

484 F.K. Chowdhury et al. / Sensors and Actuators A 188 (2012) 481– 488

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

x 10-7

0

5

10

15

20Switching time vs Thickness (Vs=1.4Vp)

Thickness(m)

Sw

itchi

ng T

ime

(ns)

Tung sten (E=411 GPa)

Polysili con (E=200 GPa)Sili con Nitride (E=270 GPa)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

x 10-7

0

1

2

3

4x 10

8 Frequency vs Thickness (t/l=0.0033)

Thickness (m)

Fre

quen

cy (

Hz)

Tung sten (E=411 GPa)

Polysili con (E=200 GPa)Sili con Nitride (E=270 GPa)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

x 10-7

0

0.1

0.2

0.3

0.4Pull down voltage vs Thickness

Thickness (m)

Vol

tage

(V

)

Tung sten (E=411 GPa, s=200 MPa)

Polysili con (E=200 GPa)

Sili con Nitride (E=270 GPa)

Fig. 5. (a) Switching time vs. thickness for fixed length and width silicon nitride,polysilicon and tungsten bridges. (b) Graph showing bridge dimensions corre-ssg

aTr

5

iSoctv

v4c∼c(epc

i

high. No actuation was observed when either both gates are lowor both gates are high. At the ON state (when the bridges con-tact each other), the drain and source electrodes contact each other

0.E+00

3.E-07

6.E-07

9.E-07

0 0.5 1 1.5 2 2.5 3

Cu

rren

t (A

)

Voltage (V)

Multiple Switching Characteristics

Fig. 7. I–V characteristics over a million switching cycles. In this test, the G1 was

ponding to GHz operational frequencies. The bridge length (l) and width (w) arehown above the plots, (c) pull down voltage vs. thickness for l = 30 �m, w = 15 �m,0 = 10 nm.

t 200 W. This also resulted in a clean etch of the nitride bridges.he ALD Al2O3 layers acted as an effective etch stop for this dry etchecipe.

. Testing and results

The micro-fabricated XOR gates were tested to find their switch-ng characteristics and reliability using an Agilent 4156C Precisionemiconductor Analyzer and a probe station. A switching voltagef approximately Vp ∼ 1.5 V was observed over repeated cycling asan be seen in Fig. 7. In this and next tests the Gate 1 was shortedo drain and Gate 2 was shorted to the source and the switchingoltage was applied between the top and bottom bridges.

The devices were also tested at elevated temperature inside aacuum chamber. I–V characteristics of the switch at 298 K and09 K are shown in Fig. 8. The switching characteristics did nothange appreciably at elevated temperatures, albeit shifted by0.5 V. The shift in the voltage at elevated temperatures can be

aused by the temperature dependence of material parametersi.e., Young’s modulus) and by the temperature dependence of thelectrical properties of the different parts of the switch. The tem-

erature dependence of the contact region may dominate in mostases since it is the most active part of the switch.

The setup used to test the device’s logic functionality is schemat-cally shown in Fig. 9. As seen from the switching characteristics,

Fig. 6. Fabrication process flow for XOR and AND gates. The process flow is the samefor other gates.

the two gate regions attract each other only when one of them is

shorted to D and G2 was shorted to S. These contacts are shown in Fig. 2 and thevoltage was then applied between the G2-D and G1-S electrodes. The dashed cir-cles and the associated arrows indicate the I–V branch in the forward direction andreverse direction for the many traces shown here. The hysteresis is due to stictionbetween the bridges after they touch each other.

F.K. Chowdhury et al. / Sensors and Actuators A 188 (2012) 481– 488 485

-2.E-07

0.E+00

2.E-07

4.E-07

6.E-07

8.E-07

1.E-06

1.E-06

0 0.5 1 1.5 2

Cu

rren

t (A

)

Voltage (V)

Switching characteristics at elevated temperatures

I-V at 409K

I-V at 298K

Fig. 8. Switching characteristics at elevated temperatures. These tests were per-fs

aasel

rwi

1.E-16

1.E-14

1.E-12

1.E-10

1.E-08

1.E-06

1.E-04

0 0.5 1 1.5 2 2.5

Pow

er (

W)

Voltage (V)

Measured Leakage Power

Fig. 10. Graph showing leakage power characteristic of the fabricated XOR gate

Ft

ormed using the same electrode arrangements used in Fig. 8. The arrows show thecan directions. The hysteresis is caused by stiction as explained in Fig. 7.

nd produce the desired output. This simple structure operated asn XOR gate. The devices “D” and “S” electrodes were situated oneparate bridges leading to very small surface leakage current. Thelectrodes had ∼4 �m2 contact area and their leakage current wasess than 10−9 A at 0.5 V. The leakage power is shown in Fig. 10.

In order to investigate the performance of these devices in high

adiation environments, The TRIGA reactor at University of Utahas employed. According to reactor specifications, at 90 kW, typ-

cal neutron flux is ∼3 × 1012 neutrons/cm2-s. The energy of the

ig. 9. Voltage transitions of a single XOR device. S–D transitions to HIGH only when eransitions to LOW.

(∼1 �W). The arrows show direction of scan. The hysteresis is caused by stiction asdiscussed in Fig. 7.

neutrons varies from 0.025 eV to 10 MeV, but most of have ener-gies less than 1 MeV. In general, alpha particles do not exist inthe reactor core except for inside the fuel element which has anaverage energy of 6 MeV. It is known that gamma rays exist ubiq-uitously in the reactor core. Approximate gamma flux is on orderof 1013 gamma/cm2-s (or higher). Gamma particles’ energy ranges

from approximately several keV to 3 MeV. Beta particles’ flux at90 kW is approximately 1013 beta/cm2-s and typical energy of abeta particle is between 100–1500 keV.

ither G1 or G2 are high. When both G1 and G2 are LOW (or HIGH) together, S–D

486 F.K. Chowdhury et al. / Sensors and Actuators A 188 (2012) 481– 488

Fig. 11. (a) MOSFET Ids–Vds at 1 W ionizing radiation, 1 min. (b) Its Ids–Vds at 90 kW ionizing radiation for 120 min.

Fig. 12. MEMS switch I–V characteristics at 1W-1 min, 90kW-60 min & 90kW-120 min ionizing radiation. Clear “on” and “off” states are still discernible even after prolongedexposure to I–R. The arrows shows scan directions.

F.K. Chowdhury et al. / Sensors and Actuators A 188 (2012) 481– 488 487

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0 1000 0 2000 0 30000 40000 50000 60000 70000V

olt

age

(V)

Time (sec)

109 Switching Cycles

F in she

MsTsi

Fm

ig. 13. Switching characteristics of the XOR gate operated as a switch as explainedxperiment time.

Figs. 11–12, respectively, show the I–V characteristics of aOSFET and an XOR gate connected as a switch (i.e., Gate 1

horted to drain and Gate 2 shorted to the source) inside the

RIGA nuclear reactor at 90 kW. After a few minutes of expo-ure, the MOSFET’s IDS increased by an order of magnitude andts channel became permanently conducting (Fig. 11(b)). At this

ig. 14. MEMS circuits fabricated using single-device XOR and AND gates. (a) 2-bitultiplexer, (b) 1-bit full adder and (c) 2-bit full adder.

own in Fig. 7. The gate switched up to 109 cycles and the study was limited by the

point the MOSFET gate voltage could no longer control the chan-nel current. In the case of XOR gate, the I–Vs were not affectedappreciably by the radiation even after 120 min, as seen in Fig. 12.The switching voltage changed somewhat but the device con-tinued to operate with clear “on” and “off” states. Many factorsmay contribute to the changes in the switching parameters ofMEMS and NEMS exposed to intense ionizing radiation. Mate-rial embrittlement following large densities of defect generations,the resulting resistance changes, and heating are just to name afew.

Additionally, device lifetime measurement was carried out andits continuous switching characteristic obtained over 109 cyclesas shown in Fig. 13. The device was intact even after the 109

cycles and the experiment had to be stopped due to time con-straint. We estimate the actual device lifetime is in excess of 1010

cycles.In addition to the above single logic gates, we also fabricated

circuits composed of many interconnected logic gates to demon-strate the feasibility of integrated MEMS circuits. Fig. 14(a)–(c)illustrates optical images of a 1-bit multiplexer chip using 4AND gates, a 1-bit adder chip using 3 XOR and 2 AND gatesand a 2-bit full adder circuit utilizing 6 XOR and 4 AND gatesthat are currently being tested and will be reported in a futurepublications.

6. Conclusion

This article presented functional MEMS/NEMS structures thatoperate as logic gates in a single device instead of using indi-vidual switches commonly employed in CMOS. Given that 6–14CMOS switches are typically needed in logic gates, the functionalstructures reduce the device count leading to better reliabil-ity, yield, speed and overall better characteristics (sub-thresholdcharacteristics, smaller turn-on/off voltage variations, etc.). Thedesign, fabrication and characterization of XOR and AND gatesas specific examples of single-device logics were discussed. Theresults showed a ∼1–2 V pull-down voltage, less than 1 �W leak-age power consumption and switching lifetime of ∼109 cycles.Moreover, harsh environment operation at elevated temperatures(409 K) and high ionizing radiation environment (120 min in 90 kWnuclear reactor) showed successful and reliable operation of these

MEMS devices over a silicon MOSFET. Finally, microfabricatedcircuits such as multiplexers, 1-bit full adder and a 2-bit fulladder that employ the XOR and AND gates were also presentedhere.

4 and Ac

A

P2

R

[

[

88 F.K. Chowdhury et al. / Sensors

cknowledgements

This work is supported by DARPA NEMS Grant # NBCH1090003.arts of this work were used in an extended abstract accepted in012 Hilton Head Workshop.

eferences

[1] F.K. Chowdhury, K.N. Chappanda, D. Saab, M. Tabib-Azar, Novel single-deviceXOR and AND gates for high speed, very low power LSI mechanical processors,in: The 16th International Conference on Solid-State Sensors, Actuators andMicrosystems, Beijing, China, 2011.

[2] M. Tabib-Azar, S.R. Venumbaka, K. Alzoubi, D. Saab, 1 Volt, 1 GHz nems switches,in: IEEE Sensors, 2010, 2010, pp. 1424–1426.

[3] K. Alzoubi, D.G. Saab, M. Tabib-Azar, Circuit simulation for nano-electro-mechanical switches VLSI circuits, in: 2010 53rd IEEE InternationalMidwest Symposium on Circuits and Systems (MWSCAS), 2010, pp.1177–1180.

[4] V.K. Sirigir, K. Alzoubi, D.G. Saab, F. Kocan, M. Tabib-Azar, Ultra-low-powerultra-fast hybrid CNEMS-CMOS FPGA, in: 2010 International Confer-ence on Field Programmable Logic and Applications (FPL), 2010, pp.368–373.

[5] M. Tabib-Azar, K. Alzoubi, D. Saab, Novel MEMS 900 MHz electrostatic silicondelay line, in: IEEE Sensors, 2010, 2010, pp. 205–207.

[6] K. Akarvardar, D. Elata, R. Parsa, G.C. Wan, K. Yoo, J. Provine, P. Peumans, R.T.Howe, H.S.P. Wong, Design considerations for complementary nanoelectrome-chanical logic gates, in: IEEE International Electron Devices Meeting, 2007.IEDM 2007, 2007, pp. 299–302.

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tuators A 188 (2012) 481– 488

Biographies

Faisal K. Chowdhury obtained his MSc from the Advanced Metrology and Nano-Device Applications (AMANDA) Lab, Electrical and Computer Engineering (ECE)Department at the University of Utah, in 2011. He is currently pursuing hisPhD from the same lab and institution. His research interests include novelMEMS and NEMS devices design, fabrication and applications, Surface EnhancedRaman Spectroscopy (SERS), Rapid DNA sequencing techniques and other con-cepts that enable nanotechnology. His expertise includes surface metrology forMEMS switches and other devices, MEMS-based computational logic gates, MEMSultra-high-quality gyroscopes, MEMS based resonators and Micro-Plasma Devices(MOPFETs) to name a few. Faisal is an avid technology enthusiast and is pas-sionate about solving challenging problems to enable devices and systems of thefuture.

Daniel G. Saab obtained his BS, MS and Ph.D. in UIUC and is an Associate Professor atCase. He has 90 papers in CAD and won the 1988 SRC Inventor award for the CHAMPtechniques. His interests include “beyond the Moore” devices and architectures.

Massood Tabib-Azar received MS and PhD degrees in electrical engineering fromthe Rensselaer Polytechnic Institute in 1984 and 1986, respectively. In 1987 hejoined the faculty of EECS department at Case Western Reserve University. He was afellow at NASA during 1992–1992, on Sabbatical at Harvard University during 93–94,and at Yale University during 2000–2001. Massood is currently a USTAR Professor ofECE at the University of Utah, Electrical and Computer Engineering Department withadjunct appointment in Bioengineering Department. His current research interestsinclude nanometrology (microwave-atomic force microscopy), molecular electron-ics, novel devices based on solid electrolytes, sensors and actuators (microfluidics),and quantum computing. His teaching interests include development of courses inthe area of electronic device physics and electromagnetics with an emphasis onsolving problems and the use of computer-aided instruction tools. He is author ofthree books, two book chapters, more than 150 journal publications, and numerousconference proceeding articles. He has introduced and chairs many internationalsymposia in his fields of interest.

Dr. Tabib-Azar is a recipient of the 1991 Lilly Foundation Fellowship and heis a member of the New York Academy of Sciences, IEEE (Electron Devices), APS,AAPT, and Sigma Xi research societies. He has also received more than 12 cer-tificate of appreciation and recognition for his professional activities and a best

paper award from Design Automation conference in 2001 for his work on elec-tromagnetic properties of interconnects and defects in ICs, a best paper award fromInternational Conference on Intelligent Robots and Systems in 2004 for his workon Human–Machine Interface, and a best paper award from ISQED for his work onNEMS Processors.