Sinara: Scalable Control for Quantum DevicesJ.W. Britton [0,6], A. Agrawal [6], D.T. Allcock [1], J.M. Amini [2], C. Ballance [3], S.

BouHabib [5], S. Bourdeauducq [4], T.P. Harty [3], R. Jordens [4,7], G. Kasprowicz [5], F.

Kermarrec [4], J. Mizrahi [2], D.H. Slichter [1], W. Zhang [3]

The Advanced Real-Time Infrastructure for Quantum physics

(ARTIQ) is a control system for quantum information

experiments. It features a high-level programming language

called ARTIQ Python in which logic for complex experiments

can be expressed. Experiment code is compiled and executed

on dedicated FPGA hardware with nanosecond timing

resolution and microsecond branching latency. The system

was designed to meet the requirements of feedback-based

algorithms in trapped ion processors including quantum errorcorrection. github.com/m-labs/artiq

This poster discusses Sinara, an open source suite of high

performance FPGA-based hardware designed for trapped ion

qubit systems using ARTIQ. Sinara includes low phase-noise

software-defined radios with 600 MHz analog bandwidth and

support for ARTIQ microsecond branching latency. Other

Sinara peripherals include many-channel DACs, ADCs and

ns-resolution digital IO. All peripherals are integrated with

ARTIQ. github.com/m-labs/sinara

[0] Army Research Lab, Adelphi, MD, US

[1] NIST, Boulder, CO, US

[2] IonQ Inc., College Park, MD, US

[3] University of Oxford, Oxford, UK

[4] M-Labs Ltd., Hong Kong, HK

[5] Warsaw Technical University, Warsaw, PL

[6] University of Maryland, College Park, MD, US

[7] QuARTIQ, Berlin, GR

S. Debnath (2016)

timing

ARTIQ Python language expresses how to implement Native gates

ARTIQ SoC + Sinara Hardware gives classical control

ARTIQ OS

user interface, scheduler, logging, parameter database, device management

Scaling to N qubits requires: • N 2-tone RF sources • O(N^2) waveforms for gates• measurement-based feedback

Motivation: Duke-UMD approach

Core Device

…gateware… ARTIQ OS Overview

core deviceFPGA

Master* scheduler* compiler* datasets

command line tools

logging database

(InfluxDB, Grafana)

controller 1

Novatech 409B

ThorlabsTDC & TPZ

PDQ DACS

NI 6733 DACs

TTL In

DDS AD9914

git repository(holds experiments)

Windows/Linux hardware

controller 2

SAWG

TTL In/Out

FPGA

experiment datastore

(HDF5, file system)

GUI

controls

worker(executing)

worker(preparing)

pipeline’d workers compile, upload, RPCs

worker(analysis)

PMTs

syn

chro

niz

atio

n

VHDCI Carrier

Sayma

RTIO

USB

PCI/PXI

USB

TCP/IP

processes on PCs

non-deterministic devices

deterministic devices controlled by RTIO/DRTIO

gateware

link

link

link

Core FPGA SoC

Kernel CPU

(mor1kx RISC)

L2 Cache(block RAM)

DDR3SDRAM

Serial

Ethernet MAC (1 Gb)

Wis

hb

on

e B

us

1 (

32

-bit

)

FLASH

JTAG

COM CPU(mor1kx RISC)

Wis

hb

on

e B

us

2AMPSoC“mailbox”

Memory Controller

(64 Gbps)

link

RGMII transceiver

HardwareRTIO

fiber or copper

PHYPHY examples:• Urukul (DDS)• SAWG• TTL_In• TTL_Out• SPI

HW examples:• Urukul EEM • Sayma PCB• BNC EEM• SMA EEM• Novo EEM

DR

TIO

Satellite FPGA RTIO

DRTIODist. DMA

DDR3SDRAM

eg Metlino/Kasli

eg Sayma using distributed DMA

RTIO Core

OutputManager

InputManager AsyncFIFO

AsyncFIFORTLink

FIFO contains N slots:• 64-bit time stamp (1ns)• data slot• address slot

PHYlink

FIFO Depth:• reconfigurable • typically 32 to 512 slots

DAC Output is

𝑎1(𝑡𝑖)

𝑓1(𝑡𝑖)

𝑝1(𝑡𝑖)

𝑎2(𝑡𝑖)

𝑓2(𝑡𝑖)

𝑝2(𝑡𝑖)

𝑓0(𝑡𝑖)

𝑝0(𝑡𝑖)

+ 𝑢0

𝑢0(𝑡𝑖)

Smart Arbitrary Waveform Generator (SAWG)

Features• RTIO-defined waveforms

• two baseband DDS tones• up-conversion by parallel array of DUCs• cubic spline amplitude shaping• sample-accurate event timing gives

absolute phase control

• DMA playback from pre-recorded waveforms• modulation by RTIO

• uses +10 RTIO ports (not shown)• additive for frequency and phase• multiplicative for amplitude

• modulation by DSP• for closed-loop feedback using ADC• DSP switch yard• IIR and PID filtering• implementation parallels RTIO

modulation

SAWG waveform computation gateware

Saymasoftware defined radio for ARTIQ

• analog front-end (AFE) mezzanines• application-specific engineering • impedance matching, filters• IQ mixing, up/down conversion• LO from clock mezzanine or front

panel

Allaki AFE- 2 outputs: up to 3 GHz- 2 inputs: DC - 300 kHzNanoga AFE- 1 output: 2 DACs drive IQ mixer, 2.5 – 3.5 GHz- 2 inputs: baseband or mixed

Advanced Mezzanine Carrier (AMC)• Kintex Ultrascale FPGA• DDR3 SDRAM• SFP+, FMC, SATA, uTCA backplane• 16 multi-gigabit transceiver pairs to RTM

Rear Transition Module (RTM)• 2x AD9154 JESD204B DAC

• 4 ch, 1.2 GS/s, 2.4 GHz DAC clock• 16-bit samples• base band in 1st, 2nd or 3rd Nyquist

• 2x AD9656 ADC • 4 ch, 125 MS/s, 16-bit samples• DSP modulation for >100 kHz

closed-loop feedback on SAWG outputs

DMA direct memory access for Sinara

# obtain a handle to a named DMA sequence; record events

my_burst = DMA("my_burst")

with my_burst:

delay(10*ns)

ttl0.pulse(20*ns)

for i in range(100):

dds2.pulse(300*MHz + i*1*MHz, 220*ns)

# global timeline remains unaltered

# potentially in a new experiment, new kernel:

# get reference to recorded DMA sequence

my_pulse = DMA("my_burst")

t = now_mu()

for i in range(100):

ttl2.pulse(3*us)

my_pulse.play()

assert t + seconds_to_mu(100*(3*us + 250*ns)) == now_mu()

# release the DMA sequence

my_pulse.free()

Motivation: pre-load sequences that can be pre-computed to reduce required real-time DRTIO bandwidth

Features:• supports real-time modulation of SAWG by DRTIO and DSP• DMA sequences persist across kernels/experiments• Timestamps in sequence are relative to the beginning of the

sequence• N DMA engines permit playback of N DMA sequences in parallel;

now N=1• presently no for input DMA

Eurocard Extension Modules (EEM)Eurocard Extension Modules (EEMs) is a Sinara standard for low-cost, low-bandwidth, ns resolution peripherals that are controlled by ARTIQ DRTIO. The EEM bus provides• eight LVDS, one I2C, +12 V and +3.3 V• standard PHYs are: TTL, I2C and SPI

EEM DIO breakout

• SMA, TTL and RJ45 varieties

• 2 banks of 4 IO

• per bank galvanic isolation

• per channel impedance

selection 50 Ohm or 1K Ohm

• per channel directionality

selection

• 3 ns minimum pulse width

• commercial availability

Sayma clock mezzanine• HMC440 PLL, Crystek VCO, in 100 MHz, out 400 MHz to 3.2 GHz

W. Zhang

Distributed Real Time IO (DRTIO)DRTIO is a time and data transfer system that allows ARTIQ RTIO channels to be distributed among several satellite devices synchronized and controlled by a central master device.

The link is a high speed duplex serial line (> 4 Gb/s). A variety of transceivers are supported (Xilinx GTX/GTH and soft transceivers using regular FPGA IOs). The protocol is optimized to minimize latency and handles error conditions. DRTIO supports auxiliary low-priority traffic.

KC705(master)

Symmetricom5125A

KC705(satellite)

1310/1490nm SFPs

single G.652 fiber

62.5 MHz

Si5324(jitter atten.)

200 MHz

Clock-Recovery Test

DRTIO Switch- multiple satellites, one master (tree configuration) - clock domain spanning - <200 ns latency per switchWhite RabbitThe lower layers of DRTIO are similar to White Rabbit, with the following differences:- lower, deterministic latency- guaranteed cut-through switching- automatic enumeration- no Ethernet compatibility- only star or tree topologies are supported

RMS jitter 1 Hz to 1000 kHz is 50 psRMS jitter 1 Hz to 100 kHz is 18 ps

Kasli Core Device (M-Labs, WUT)• Artix 7 FPGA, SDRAM• 2 SFP, 2 SMA• 8 EEM extensions• clock-recovery

Grabber EEM (Hannover/PTB)• CameraLink• for Andor iXon and X3

SRTIO (Oxford)• multiplexed FIFOs for RTIO• simplified error detection logic

eases timing closure

ARTIQ SurveyExperiment type14 trapped ion8 neutral atom3 lattice defect 1 superconducting

Application domain11 sensing5 clocks11 computing & simulation4 communication

https://goo.gl/9Eopyx

Organization type

April 2017: 21 labs responded

DeploymentLabs with setups dependent on ARTIQ: 5

ForecastPlanned number of setups in your lab that will depend on ARTIQ in 2018. Total: 30

Sinara in Q4 2017

Sinara in 2018

Zotino DAC EEM• 32 ch, 16-bit, 1 MSPS• +/- 10 V, high stability• low-noise, 75 kHz filters

Novo ADC EEM• 8 ch, 16-bit, 1 MSPS (single ch)• variable gain (100 mV to 10 V)• differential input

RFPA• 8 ch RF power amplifier• 40 MHz to 500 MHz• 36 dBm output, per ch limit

CLK_BUF EEM• clock buffer• 1 in, 4 out• up to 1 GHz, < 100 fs jitter

Mirny EEM• 4 ch DDS up to 750 MHz RF• AD9910 or AD9912

All these components are led by Oxford.

UrukulNovoServo• new gateware/software• 1 Kasli, 2 Novo, 4 Mirny• ~100 kHz feedback BW

Stamper (ARL)• time to digital converter (TDC)• FPGA implementation:

• 1 ch/chip, ~50 ps RMS, 125 MHz/ch

• ACAM IC implementation• 2 ch/chip, 27 ps RMS, 40

MHz/ch