SIMULATIONPavan Gunupudi

ELEC 5402

Simulation

Used for design verification

Broad definition of simulation

Creation of software models of hardware

Evaluation of outputs of a system given inputs

Several types of simulation

Applicable at different levels of design hierarchy

Types of SimulationDevice level simulation

Single semiconductor device is simulated (eg. diode)

Charge distribution is calculated in time and three dimensions

Based on Finite Element Method (FEM) and Finite Difference Method (FDM)

Circuit level simulation

Simulate groups of transistors, diodes, resistors etc.

Eg. Spice, Signal integrity tools

Types of SimulationTiming level and macro-level simulation

Signals are still analog

Models are simplified to accommodate large netlists

Nonlinear elements are replaced with piecewise linear elements

Group of devices represented by a macro

Switch level simulation

Transistors are considered as switches

Signals almost digital (one, zero) - but they have signal strength to model parasitics

Types of SimulationGate level or logic level simulation

Gates are used instead of transistors for simulation

Signal flow is unidirectional

Register transfer level simulation

Synchronous circuits - clock controls registers being assigned

Registers store the state of the system

Combinational logic gates compute next state of registers

State transitions are of interest; other effects secondary

Types of SimulationSystem level simulation

Block of hardware specified through Verilog/VHDL

Simulation of such blocks is system-level simulation

Mixed-mode simulation

Circuit-blocks described in different abstraction levels

Simulators combine all levels of abstractions

Hardware software co-simulation

Certain parts hardware - Certain parts software

Parts of SimulatorKernel

Core of simulator that performs the evaluation

Computes signals at every point of interest

Input description

Netlists, schematics, VHDL, Verilog, EDIF format

Stimuli

Stimulus to circuit - usually present in netlist

Presentation of results

Tables, plots, animations etc.

Gate Level Simulation

Signal modelling

Gate modelling

Delay modelling

Simulation mechanisms

Signal/Gate Modelling

Digital Signals (one, zero)

Extra state for a signal

X (uninitialized); U (Unknown)

Some simulators have a notion of signal strength

Gate modelling

Truth table representation: Lookup involved

Subroutine representation: Boolean expression evaluation

Delay ModellingUse gate models with delays

Propagation delay: Assign a fixed delay for the gate; special cases zero delay; unit delay models

Rise/Fall delay models: Different delays for rise and fall times

Inertial delay models

(a)

(b)in_1

in_2 out

time’0’’1’

in_2 ’0’’1’

in_1

0 1 2 3 4 5 6 7 8 9

out

time’0’’1’

0 1 2 3 4 5 6 7 8 9

out

time’0’’1’

0 1 2 3 4 5 6 7 8 9(c)

If a pulse is thinner than a certain limit it has no effect on the output.

Connectivity: Cell-port-net is enough

Compiler Driven Simulators

Assign levels to nets

Level 0: Connected to inputs

Level 1: One gate away from inputs

Level 2: Two gates away from inputs

...

ABC

DE

F

n1n2n3

n4n5

n6

n7

n8n9

n1 ← A;n2 ← B;n3 ← C;n4 ← D;n5 ← E;n6 ← OR(n1, n2);n7 ← AND(n4, n5);n8 ← AND(n6, n3);n9 ← OR(n7, n8);F← n9;

Compiler Driven SimulatorsCompute level 0, then level 1, then level 2 etc.

Zero delay models

For unit delay models we need net values for previous points

Use two arrays: t and t-1

Swap arrays at each time point

Can be extended to mote than unit delay

Need max delay plus one number of arrays

time

’0’’1’’0’’1’

0 1 2 3 4n1

n2

n3

n4

n5

n6

n7

n8

n9

’0’’1’’0’’1’

’0’’1’’0’’1’

’0’’1’’0’’1’

’0’’1’

Event Driven SimulatorFew gates switching at any point; no point computing all signals

Change in input is an event which triggers change in only gates connected to it

If the output of these gates change, they in turn create another event which triggers other gates. So on and so forth ...

Such an approach intuitively would be faster than a compiler driven simulation

Practically - 100 times slower than compiler driven simulators

Advantage: Can incorporate various delay models

Event QueueEvent - three attributes

Time when event should occur

Nets that will change

New value assumed by net

Actions to be performed on event queue

Return earliest event and remove it from queue

Add an event at any time point

Event Queue

Choose Δt

All delays are multiples of Δt

Store events in an array

Storage...

time

currenttime

(n! 1)!t

n!t

(n" 1)!t

(n" 2)!t

(n" 3)!t

Cyclical Event Queue

Reuse locations

(Max delay+1) number of locations needed

First event triggers other events

Process events at each point and create new events

Repeat until end of simulation

currenttime

(n! L)!t n!t(n! 1)!t

(n! 2)!t

(n! 3)!t

time...

...

Pseudo-Codeevent driven simulation (){struct event queue *Q;Q ← new queue();“insert stimuli in Q”;“initialize: all network nodes connected to a memory to ’U’ and

all other nodes to ’X’”;for (t ← tstart ; t < tend ;) {current event← first event(Q);t ← current event->time;“process current event and add new events to Q attime t + appropriate delay”;

}}

Switch Level Simulation

Connectivity: Cell-port-net

Transistors are switches between drain and source

Signal strength models Rs and Cs

Signal has strength and value <s,v>; v → zero, one, X

Storage nets have a capacitance → strength

Input nets have a fixed voltage level; so they have the highest strength

Transistors also have strength; it represents the maximum strength that can pass through them

Bryant’s Model (Hayes)Signal strengths vary from 1,2,...,k,...,w

Strength is w for input signal

k < s < w for transistors

1 ≤ s ≤ k for a storage net

Selection of w, k and s for transistors and nets determines the model for a particular logic

eg. Static CMOS, nMOS and domino CMOS; all these are represented with w = 5 and k = 2

Logic Families

n0(5)

(3)

Vdd

(3)

(4)

(4)

A

B

(a) (b) (c)

A

B

Vdd

A

B

(3)

(3)

(3)

A

B

(3)

(3)

!

Vdd

(3)

(3)

VssVss Vss

n1(1)

n2(1)

Out Out

Out

n1(1)

n1(2)

n2(1)

n2(1)

n3(1)

n0(5)

n0(5)

n3(5) n3(5) n4(5)

! 1987 IEEE

Models for Logic Families

Static CMOS

Strengths → Supply nets: 5; Transistor: 3; Storage nets: 1

At any point the output node is either connected to Vss or Vdd through transistors

Hence the strength at output is always 3; eg: ⟨3,′ 1′⟩ or ⟨3,′ 0′⟩

Model for nMOS

Enhancement nMOS are used as transistors and depletion nMOS are used as resistors

Transistors block non-conducting → output gets ‘1’ from Vdd through depletion nMOS

Transistors block conducting → output gets ‘0’ from Vss through enhancement nMOS

Strengths → Supply nets: 5; depletion nMOS: 3; enhancement nMOS: 4; Storage nets: 1

Model for Domino CMOSThis logic works on a clock; Clock low: Output pre-charges; Clock high: Output is delivered

Delivers ‘1’ if A,B block is non-conducting; Delivers ‘0’ if A,B block is conducting

Consider when A,B block is conducting and A is ‘1’ and B is ‘0’

If net n2 has the same capacitance as n1, the charge stored on n1 will be shared; the output signal gets weaker

So in this logic the capacitance at n1 is larger than the capacitance at n2

This is represented by giving more strength to net n1 than net n2

Strengths → Supply nets: 5; Transistor: 3; Output net: 2; Other storage nets: 1

Simulation MechanismsThe circuit is not simulated as a whole

It is partitioned at places where there is unidirectional communication (eg. where a signal drives the gate of a transistor)

Interaction between these blocks is done using an event driven mechanism discussed previously

(a) (b)

Vdd

Vss

Vss

Vdd

Vdd

Vss

Vss

Vdd

’0’T

PartitioningTwo types of partitions

Static

Usual case (shown in (a))

Dynamic

Shown in (b)

Extra partitions can be formed due to known signal values

Advantages: Partitions are smaller

Disadvantages: Extra effort is required to partition

Making Partitions

Choose an arbitrary transistor

Visit all transistors connected to it’s source/drain

Do the same for each transistor visited

Do not visit transistors connected to ground

This forms a partition

Then start from transistors that are left over; repeat the same process

To form dynamic partitions, we do not visit transistors that are off; such transistors isolate some parts of the circuit

This will ensure smaller partitions but these partitions will change dynamically

AnalysisAll transistors connected in source-drain fashion; called channel connected

This can be represented using a graph G(V,E)

If u ∈ V then a signal on it can be given as ⟨σu, λu⟩; σu represents the signal strength and λu represents the signal level

For edge (u, v) ∈ E, εu,v is the strength of a transistor if it is conducting else it is zero

n0(5)

(3)BA(3)n1(1)

n2(1)

n3(5)

(3)A

B(3)

AnalysisTwo effects that we consider:

Signal flow along edge (u, v) ∈ E given signals on u and v

Signal on v ∈ V given all signals flowing along edges (u, v) ∈ E

Let σu→v denote the strength of signal flowing from u to v, then

σu→v = min(σu, εu,v)

Signal level will not change; just the strength will be affected

Points to Note

A transistor limits the strength of a signal passing through it to its own strength

Signals passing through a nonconducting transistor have a strength zero (i.e. signal value is zero)

In reality v might be stronger than u; then signal will flow from v to u; we pretend that signal flows in either way, without the results

AnalysisDistinguish between charged nets and driven nets

Driven netsCharged net

Vdd

Vss

For a driven nets:

�v = max

1im�ui!v

where v 2 V has edges (u1, v), (u2, v), . . . (um, v) 2 E connected to it.

For charged nets:

�v = max(�v, max

1im�ui!v)

Di↵erence is �v also is included; it could be the strongest.

SimulationConsistent application of these three rules we discussed will ensure estimation of correct signals in the circuit

Example where this fails

propagate from→ to state of n2 state of n3“initial state” 〈1,’X’〉 〈1,’X’〉n0 → n2 〈3,’1’〉 〈1,’X’〉n2 → n3 〈3,’1’〉 〈3,’1’〉n1 → n2 〈4,’0’〉 〈3,’1’〉n2 → n3 〈4,’0’〉 〈3,’X’〉

n0(5)

(3)

Vdd

(4)

Vssn1(5)

n2(1) n3(1)(3)

! 1987 IEEE

Correct answer for n3 is ⟨3,ʹ′ 0ʹ′⟩

Another RuleGive priority to the vertex with strongest signal for propagation of its signal to its neighbours.

Any vertex should not propagate its signal until all edges with stronger signals have not propagated their signal.

prop. from→ to contents of Q state of n2 state of n3“initial state” Q[5] = {n0, n1}, Q[1] = {n2, n3} 〈1,’X’〉 〈1,’X’〉n0 → n2 Q[5] = {n1}, Q[3] = {n2}, Q[1] = {n3} 〈3,’1’〉 〈1,’X’〉n1 → n2 Q[4] = {n2}, Q[1] = {n3} 〈4,’0’〉 〈1,’X’〉n2 → n0 ! Q[1] = {n3} 〈4,’0’〉 〈1,’X’〉n2 → n1 ! Q[1] = {n3} 〈4,’0’〉 〈1,’X’〉n2 → n3 Q[3] = {n3} 〈4,’0’〉 〈3,’0’〉n3 → n2 ! 〈4,’0’〉 〈3,’0’〉