Simulation and Optimization of SiC Field Effect Transistors14791/... · 2006. 3. 19. · SiC field-effect devices. The drawback of the Monte-Carlo method is the computational power

Simulation and Optimization of SiC Field Effect Transistors

KENT BERTILSSON

Doctoral Thesis Stockholm, Sweden 2004

KTH Microelectronics

and Information Technology

KTH Microelectronics

and Information Technology


Doctoral Thesis by

Kent Bertilsson

Laboratory of Solid State Devices (SSD)

Department of Microelectronics and Information Technology (IMIT)

Royal Institute of technology (KTH)

Stockholm 2004

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A dissertation submitted to the Royal Institute of Technology, Stockholm, Sweden, in partial fulfillment of the requirements for the degree of Doctor of Technology © Kent Bertilsson, 2004 ISRN KTH/EKT/FR-2004/8-SE ISSN 1650-8599 TRITA-EKT Forskningsrapport 2004:8

The majority of the work contained in this thesis has been performed at Mid-Sweden University, Department of Information Technology and Media at the Electronic Design Division in Sundsvall, Sweden.

This thesis is available in electronic version at http://media.lib.kth.se

Printed by Universitetsservice US AB, Stockholm, 2004

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Abstract Silicon Carbide (SiC) is a wide band-gap semiconductor material with excellent material properties for high frequency, high power and high temperature electronics. In this work different SiC field-effect transistors have been studied using theoretical methods, with the focus on both the devices and the methods used. The rapid miniaturization of commercial devices demands better physical models than the drift-diffusion and hydrodynamic models most commonly used at present. The Monte Carlo method is the most accurate physical methods available and has been used in this work to study the performance in short-channel SiC field-effect devices. The drawback of the Monte-Carlo method is the computational power required and it is thus not well suited for device design where the layout requires to be optimized for best device performance. One approach to reduce the simulation time in the Monte Carlo method is to use a time-domain drift-diffusion model in contact and bulk regions of the device. In this work, a time-domain drift-diffusion model is implemented and verified against commercial tools and would be suitable for inclusion in the Monte-Carlo device simulator framework. Device optimization is traditionally performed by hand, changing device parameters until sufficient performance is achieved. This is very time consuming work without any guarantee of achieving an optimal layout. In this work a tool is developed, which automatically changes device layout until optimal device performance is achieved. Device optimization requires hundreds of device simulations and thus it is essential that computationally efficient methods are used. One important physical process for RF power devices is self heating. Self heating can be fairly accurately modelled in two dimensions but this will greatly reduce the computational speed. For realistic influence self heating must be studied in three dimensions and a method is developed using a combination of 2D electrical and 3D thermal simulations. The accuracy is much improved by using the proposed method in comparison to a 2D coupled electro/thermal simulation and at the same time offers greater efficiency. Linearity is another very important issue for RF power devices for telecommunication applications. A method to predict the linearity is implemented using nonlinear circuit simulation of the active device and neighbouring passive elements. The work has contributed to a substantial improvement in the area of device simulation and increased efficiency in device design in general, but particularly for SiC RF power MESFETs. Keywords: SiC, Device simulation, RF, power, MESFET, self heating, linearity, drift-diffusion, Monte Carlo

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Acknowledgements Firstly, I would like to thank Professor Sture Petersson for accepting me as a Ph.D. student at KTH and for his efforts in building up the research activities at Mid-Sweden University. I would also like to thank my Supervisor Hans-Erik Nilsson for his excellent guidance. Without his engagement, encouragement, and wisdom, it would have been so much harder to conduct this work. I would like to thank Dr. Ervin Dubaric for all the valuable help during the first years of my Ph.D. studies. For the conference trips we have shared and to whom I was always welcome with stupid questions. I thank Dr. Mats Hjelm for all the valuable discussions concerning the Monte Carlo method and for his engagement in improving the code whenever it was requested. Thank you for all the hours you spent proof reading most of my work during this time.

I thank Dr. Chris Harris at INTRINSIC Semiconductor AB who has widened my perspective in the application area of SiC devices and with whom it has been a great pleasure to work.

I would like to thank Dr. Göran Thungström for lots of valuable discussions about practical and processing issues regarding semiconductor devices. I thank Claes Mattsson, with whom it has been a joy to work and also Magnus and Henrik who have always been available for discussions. The rest of the Electronics department is gratefully acknowledged, especially Fanny Burman for all her help with practical arrangements, which simplifyis every days work.

The financial support from the KK-foundation and Mid-Sweden University is gratefully acknowledged.

Finally, I thank my family Katarina, Isabelle and Lukas whom I love with all my heart. Thank you for all the support and joy you have given me in my spare time. My mother, father and brother who have always been there for me and all my friends, past and present, especially Mattias, Sören and Fabian with whom I have spent lots of memorable moments

Kent Bertilsson

Sundsvall, October 2004

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Table of contents Abstract............................................................................................. iii

Acknowledgements.............................................................................v

Table of contents ............................................................................. vii

Abbreviations and Acronyms.......................................................... xi

Notation............................................................................................ xii

List of figures and tables................................................................ xiii

List of Papers ................................................................................. xvii

1 Introduction .................................................................................1 1.1 Thesis Objectives ............................................................................ 2 1.2 Thesis Outline ................................................................................. 3

2 Field Effect Transistors...............................................................5 2.1 MESFET ......................................................................................... 5 2.2 MOSFETs ....................................................................................... 6 2.3 Figures of Merit .............................................................................. 8

3 Silicon Carbide...........................................................................11 3.1 SiC Material .................................................................................. 12 3.2 Transport Properties...................................................................... 13

3.2.1 Mobility ................................................................................. 13 3.2.2 Saturation Velocity ................................................................ 14 3.2.3 Band Gap ............................................................................... 14 3.2.4 Critical Electric Field............................................................. 14

3.3 SiC Polytypes................................................................................ 15 3.3.1 6H-SiC ................................................................................... 15 3.3.2 4H-SiC ................................................................................... 15 3.3.3 3C-SiC ................................................................................... 16 3.3.4 15R-SiC ................................................................................. 16 3.3.5 2H-SiC ................................................................................... 17

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3.4 Carrier Freeze Out......................................................................... 17 3.5 Thermal Conductivity ................................................................... 18 3.6 Surface Mobility ........................................................................... 19 3.7 Impact Ionization .......................................................................... 19 3.8 Minority Carrier Life time ............................................................ 21

3.8.1 Theoretical Device Performance ........................................... 21

4 Semiconductor Device Simulations..........................................25 4.1 Monte Carlo Method..................................................................... 26

4.1.1 Scattering events.................................................................... 29 4.1.2 Carrier heating ....................................................................... 29 4.1.3 Poisson’s equation ................................................................. 30

4.2 Hydro-Dynamic Model ................................................................. 30 4.3 Drift-Diffusion Model................................................................... 31 4.4 High-Field Transport .................................................................... 32 4.5 Time reduction in Monte-Carlo Simulations ................................ 33 4.6 Anisotropic Simulations................................................................ 34 4.7 SiC Device Simulations ................................................................ 35

4.7.1 Mobility and Saturation Velocity .......................................... 35 4.7.2 Relaxation Time..................................................................... 38 4.7.3 Impact Ionization Coefficients .............................................. 38

4.8 Drift-Diffusion versus Hydrodynamic model ............................... 39 4.9 Thermal effects ............................................................................. 40

4.9.1 Heat transfer simulations ....................................................... 41 4.9.2 Electrical simulations............................................................. 42

4.10 Linearity........................................................................................ 44 4.11 Semiconductor device optimization.............................................. 46

4.11.1 Optimization Goal ................................................................. 46 4.11.2 Optimization Algorithm......................................................... 47

5 Silicon Carbide Field-Effect Transistors.................................49 5.1 Lateral MESFETs ......................................................................... 49

5.1.1 Buffer Layer .......................................................................... 50 5.2 Vertical MESFETs........................................................................ 51

5.2.1 Parasitics ................................................................................ 52

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5.3 MOSFETs ..................................................................................... 53 5.3.1 Polytypes ............................................................................... 54 5.3.2 SiC face.................................................................................. 55 5.3.3 Surface orientation................................................................. 55

5.4 Applications for SiC Field Effect Transistors............................... 58

6 Summary of Papers ...................................................................61 Paper I. The Effect of Different Transport Models in Simulation of

High Frequency 4H-SiC and 6H-SiC Vertical MESFETs .... 62 Paper II. Monte Carlo simulation of vertical MESFETs in 2H, 4H

and 6H-SiC............................................................................ 62 Paper III. Simulation of Anisotropic Breakdown in 4H-SiC Diodes .... 63 Paper IV. Simulations of Submicron MOSFETs in 2H, 4H and 6H-

SiC......................................................................................... 63 Paper V. Full Band Monte Carlo Study of Bulk and Surface

Transport Properties in 4H and 6H-SiC ................................ 64 Paper VI. Numerical Simulation of Field Effect Transistors in 4H

and 6H-SiC............................................................................ 64 Paper VII. Optimization of 2H, 4H and 6H-SiC high-speed vertical

MESFETs .............................................................................. 65 Paper VIII. The power of using automatic device optimization, based

on iterative device simulations, in design of high-performance devices.............................................................. 65

Paper IX. Calculation of lattice heating in SiC RF power devices........ 66

7 Summary and Conclusions .......................................................67 7.1 Future Work.................................................................................. 68

7.1.1 Device simulations................................................................. 68 7.1.2 Device Optimization.............................................................. 69

7.2 Future trends for SiC devices........................................................ 69

References .........................................................................................71

Paper I ...............................................................................................81

Paper II .............................................................................................93

Paper III............................................................................................99

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Paper IV ..........................................................................................105

Paper V............................................................................................111

Paper VI ..........................................................................................119

Paper VII.........................................................................................135

Paper VIII .......................................................................................141

Paper IX ..........................................................................................149

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Abbreviations and Acronyms 2D/3D 2/3 Dimensions 2H,3C,4H,15R-SiC Different SiC polytypes ACCUFET Accumulation Mode FET CVD Chemical Vapor Deposition DD Drift-Diffusion DMOSFET Diffused MOSFET (Power device) FET Field Effect Transistor GaAs Gallium Arsenide GaN Gallium Nitride GEMS General Monte Carlo Simulation Tool HD Hydro dynamic JFET Junction FET LEMESFET Lateral Epitaxi MESFET LDMOSFET Lateral Diffused MOSFET (RF power device) MC Monte Carlo MESFET Metal Semiconductor FET (High frequency device) MOSFET Metal Oxide Semiconductor FET (High frequency

and/or high power device) MSG Maximum Stable Gain N2O Nitrous Oxide PBT Permeable Base Transistor (Vertically oriented

MESFET) RF Radio Frequency Schottky diode Metal semiconductor rectifying contact Si Silicon SIAFET Static Induction Accumulated FET SiC Silicon carbide SiO2 Silicon dioxide SIT Static induction transistor (Vertically oriented

MESFET) SOI Silicon On Insulator UMOSFET U-shaped MOSFET (Power device)

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Notation

α Impact ionization coefficient

β Fitting parameter ε Permittivity λ Thermal conductivity µ Mobility ρ Charge density σ Electrical conductivity τ Relaxation time τ0 Minority carrier lifetime τg Generation lifetime A Area CG Gate capacitance D Diffusion constant

(electrical) E Electric field EG Bandgap energy Ecrit Critical electric field J Current density F Force f Carrier distribution

function fT Unity current gain

frequency fMax Maximum frequency of

Oscillasion gm Transconductance

h Planck's constant ħ h/2π k k-vector (Position in k-

space) kB Boltzmann's constant LD Debye length MAG Maximum Available Gain MSG Maximum Stable Gain N Doping level m* Effective mass n electron concentration ni Intrinsic carrier

concentration neff Effective electron

concentration p Hole concentration PMax Maximum output power r Position in real space RTh Thermal resistance T Temperature tt Transit time v Carrier velocity vsat Carrier saturation velocity V Potential VBlock Blocking voltage w Depletion width

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List of figures and tables Fig. 2.1. Different MESFET topologies. A) The lateral MESFET is the

most widely used structure. B) A vertical MESFET is achieved by placing the gate fingers at the bottom of etched trenches. C) V-groove gate FET. ................................................... 6

Fig. 2.2. Different common MOSFET structures. The lateral MOSFET is the most widely used structure for small signal digital applications. The LDMOSFET dominates in applications for RF power devices. The D and UMOSFET are for high power devices at lower frequencies. ......................................................... 7

Fig. 2.3. Illustration of the high-frequencies figure of merits fT and fMax. .... 8 Fig. 2.4. Class A operation for a power amplifier. ....................................... 9 Fig. 3.1. Schematic structure for some different SiC polytypes................. 16 Fig. 3.2. Fraction of ionized carriers and the corresponding

conductivity for 4H-SiC using the donor energy level ED=52 meV [26] calculated from the mobility in ref [21] using eq 3.3. The solid line is calculated with full ionization at high doping levels. ............................................................................... 18

Fig. 3.3. Impact ionization coefficients for 4H-SiC in the direction parallel to the c-axis. .................................................................... 19

Fig. 3.4. Impact ionization coefficients for 4H-SiC in the direction perpendicular to the c-axis. .......................................................... 20

Fig. 4.1. Example from electron distribution in a Monte Carlo simulations of a vertical SiC MESFET........................................ 26

Fig. 4.2. Electron transport in 6H-SiC using the Monte Carlo method. (a) The band-structure for 4 conduction bands in 6H-SiC close to the band-minima in the M-point. The carrier movements are illustrated assuming an applied electric field of 1·105 V/cm in three crystal directions, without scatterings. (b) The velocity and position in real space for the same case...... 28

Fig. 4.3. Energy relaxation time as function of the electric field for electrons in 4H and 6H-SiC. ........................................................ 31

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Fig. 4.4. Carrier velocity and energy as function of electric field extracted from Monte Carlo simulations. The solid lines correspond to the best fit for the Caughey-Thomas transport model in (eq 4.9). Left) 4H-SiC. Right) 6H-SiC.......................... 32

Fig. 4.5. Comparison of simulation between a time-domain and a time-independent solution for the drift-diffusion equations. Left) Mid-channel concentration in a turned-on Si vertical MESFET. Right) IV characteristics for a Si MOSFET................ 33

Fig. 4.6. Electron velocity as function of the electric field for temperatures between 300 and 700K. The symbols are full-band Monte Carlo simulations and the lines are the best fit of high field transport parameters vsat and β in eq 4.9. ..................... 36

Fig. 4.7. Analytical model for the high field transport parameters vsat and β. The symbols are the extracted values from Fig. 4.6 and the solid lines represent the model in eqs 4.13-16. ...................... 37

Fig. 4.8. Thermal distribution on the surface layout for a device with 10 fingers each 200 µm long with 50 µm pitch, from heat transfer simulation........................................................................ 40

Fig. 4.9. Comparison between simulations without thermal effects, coupled electro/thermal simulations and the semi-coupled solution for a 2D case................................................................... 41

Fig. 4.10. Cross-section temperature distribution from a coupled electro-thermal simulation........................................................................ 42

Fig. 4.11. Output power density and lattice heating as function of the thermal resistance for SiC MESFET............................................ 43

Fig. 4.12. Linearity estimation. A) MESFET performance in the load-line B) Power amplifier circuit..................................................... 44

Fig. 4.13. Linearity estimation. A) Large signal non-linear transient analysis. B) Harmonic Distribution. C) POut=f(PIn). D) Enlargement of POut=f(PIn) around the 1 dB compression point. ............................................................................................ 45

Fig. 4.14. Comparison between Simplex and Simulated annealing in an optimization of 4H-SiC RF power MESFET............................... 46

Fig. 5.1. Two strategies to reduce the parasitics in vertical MESFETs. A) Etched and metallized trenches from the rear side decreases the drain-resistance. B) The vertical MESFET realized on top of a semi-insulating substrate. ............................. 52

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Fig. 5.2. Simple surface transport model. The carrier is reflected diffusly with the probability C and otherwise specular. .............. 54

Fig. 5.3. Surface transport model taking the surface steps into consideration. ............................................................................... 56

Fig. 5.4. Additional MOS structures manufactured in SiC a) ACCUFET [123] b) SIAFET [124]. ............................................ 57

Table 3.1. Material properties for some different semiconductors. .............. 12

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List of Papers Papers included in the thesis

1. K. Bertilsson, H-E. Nilsson, M. Hjelm, C. S. Petersson, P. Käckell, C. Persson, “The Effect of Different Transport Models in Simulation of High Frequency 4H-SiC and 6H-SiC Vertical MESFETs”, Solid-State Electronics, Vol 45 (5), 2001, pp. 645-653.

2. K. Bertilsson, E. Dubaric, H-E. Nilsson, M. Hjelm, C. S. Petersson, “Monte Carlo simulation of vertical MESFETs in 2H, 4H and 6H-SiC”, Diamond and Related Materials, No. 10, 2001, pp. 1283-1286.

3. K. Bertilsson, H-E. Nilsson, C.S. Petersson, “Simulation of anisotropic Breakdown in 4H-SiC Diodes”, Proceeding of 7th IEEE Workshop on Computers in Power Electronics -2000, Virginia Tech, Blacksburg, Virginia, USA, 16-18 July 2000. pp 118-120.

4. E. Dubaric, K. Bertilsson, H-E. Nilsson, “Simulations of Submicron MOSFETs in 2H, 4H and 6H-SiC”, Physica Scripta, Vol. T101, 2002, pp. 14-17.

5. M. Hjelm, K. Bertilsson, H-E. Nilsson, “Full Band Monte Carlo Study of Bulk and Surface Transport Properties in 4H and 6H-SiC”, Applied Surface Science No. 184, 2001, pp. 194-198.

6. H-E. Nilsson, K. Bertilsson, E. Dubaric, M. Hjelm, “Numerical Simulation of Field Effect Transistors in 4H and 6H-SiC”, Presented at The 3rd International Conf on Novel Appliation of Wide Bandgap Layers

7. K. Bertilsson, H-E. Nilsson, “Optimization of 2H, 4H and 6H-SiC high-speed vertical MESFETs”, Diamond and Related Materials No. 11, 2002, pp. 1254-1257.

8. K. Bertilsson, H-E. Nilsson, "The power of using automatic device optimization, based on iterative device simulations, in design of high-performance devices", Solid State Electronics Vol 48 (10-11), 2004, pp 1721-1725.

9. K. Bertilsson, C. Harris, H-E. Nilsson, "Calculation of lattice heating in SiC RF power devices", Solid State Electronics Vol 48 (12), 2004, pp. 2103-2107.

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Related Papers, not included in the thesis

1. K. Bertilsson, E. Dubaric, G. Thungström, H-E. Nilsson, C. S. Petersson, “Simulation of a low atmospherical noise four-quadrant position sensitive detector”, Nuclear Inst. and Methods in Physics Research, A, Vol 466 (1), 2001, pp. 183-187.

2. K. Bertilsson, M. Hjelm, H-E. Nilsson, C. S. Petersson, “Monte Carlo Simulation of 4H and 6H-SiC short channel MOSFETs”, Proceedings of HITEN 2001, pp. 79-80.

3. K. Bertilsson, H-E. Nilsson, “Optimization of 2H, 4H and 6H-SiC MESFETs for High Frequency Applications”, Physica Scripta T101, 2002, pp.75-77.

4. H-E. Nilsson, E. Dubaric, M. Hjelm, K. Bertilsson, “Simulation of photon and charge transport in X-ray imaging semiconductor sensors”, Nuclear Instruments and Methods in Physics Research A 487, 2002, pp.151-162

5. C. Mattsson, K. Bertilsson, G. Thungström, H-E. Nilsson, "Manufacturing and characterization of a modified four quadrant position sensitive detector for out-door applications", Nuclear Instruments and Methods in Physics Research A 531, 2004, pp. 134–139

1 Introduction The evolution within the area of computers and telecommunications seen today is based on and limited by the improvements that have been achieved in electronic device technology. To continue this rapid progress, the performance of electronic devices has to increase continuously. The method most commonly used to improve system performance is the scaling down of transistors. As the dimensions are reduced the individual device performances increase, allowing higher switching speeds of the system. With smaller dimensions the number of transistors also increases, and the functionality per unit area is improved. Although devices are becoming smaller and more advanced, the fundamental limits achievable with the devices and materials presently used are rapidly being reached. The performance of the devices is related to both their structure and the electrical transport parameters of the material. For power devices, device scaling is not the route to follow, as the breakdown voltage and consequently the output power is reduced. To increase the speed with maintained power, materials with better transport properties than those achieved by silicon can be used.

Device simulation is the most important tool for understanding and design of high performance devices. The accuracy of the models used at present in commercial software [1] such as the drift-diffusion (DD) and the hydrodynamic (HD) model is reduced when the device dimension is reduced. More advanced methods for device simulation become necessary to match the improvement rates achieved over the last few decades. A first principles method such as the Monte-Carlo (MC) method [2] is more exact than other methods but is also much more computationally demanding. One of the advantages of the MC method is that the efficiency increases as the devices reduce in size, whereas traditional methods are insufficient. Due to the accuracy of the method, Monte Carlo simulations can be used for the prediction of material properties that are difficult to measure and even for non existent materials. A problem which occurs with MC device simulations is that the majority of the time is spent on the calculation of transport in high-doped contact regions, which is of limited interest for the device performance.

2 CHAPTER 1. Introduction

Silicon Carbide is a new and interesting material for high speed, high temperature and high power electronics due to the favorable combination of transport parameters [3]. Silicon Carbide exists in numerous different lattice structures, so called polytypes, of which only a few have been exploited experimentally. The transport parameters, after many years of research, are still neither sufficient nor final. Better measurements using higher quality samples and better processing techniques are constantly being presented. One of the most important parameters for high power devices, the impact ionization coefficients, has been characterized thoroughly but with large quantitative differences.

One application area for SiC devices is in telecommunication systems, where the MESFETs are the most developed SiC switching devices and are now commercially available [4]. Vertically oriented MESFETs are also manufactured [5] but suffer from large parasitics, limiting their performance. SiC MOSFETs are also very interesting devices for the future, as, for the past decade, the oxide quality has been causing major concerns. In recent years strong improvements have been achieved in MOSFET channel mobility [6] and commercial devices will probably be available in the near future. However a great deal of theoretical understanding regarding the surface transport is, as yet, unavailable.

For RF power devices self heating and linearity are two fundamental problems and methods to study these effects are crucial. Self heating can be modeled in commercial software by coupled electro/thermal simulations [1] but as these ignore three-dimensional effects the methods are insufficient for device design. Little support is available from simulation tools for the estimation of the system level linearity of these devices. Large-signal transient-analysis at RF frequencies results in low convergence rates in the commercial software packages.

In device design of high performance devices, much time is spent optimizing the layout to achieve optimal performance. Device optimization is difficult even with advanced simulation software, as the influence of many different layout parameters must be evaluated and optimal performance is often achieved by having to take multiple trade-offs into consideration.

1.1 Thesis Objectives The aim for this thesis is to significantly improve the methods for design of semiconductor devices in general and SiC RF power MESFETs in particular. Better transport models for silicon carbide are required. Efficient and accurate models for self-heating and linearity are highly wished for.

Knowledge regarding the impact of the use of different transport models in device simulation particularly in new materials, such as SiC, is generally

1.2 THESIS OUTLINE 3

limited. Through the use of simulations of identical short channel vertical MESFETs, the influence of the different models can be studied. The transport parameters are critical for accurate device simulations and from a variety of sources, mainly measurements, but also Monte-Carlo simulations, the most critical parameters are determined.

Using the Monte Carlo method, theoretical predictions can be made of material properties even for non-existent materials. In this work the suitability of the polytype 2H-SiC for device fabrication is studied by means of Monte Carlo Simulations. The outcomes of such studies are valuable as they act as the basis for decisions regarding which new materials require the input of effort.

The impact ionization process is investigated bringing together different measurements and theoretical calculations. Device simulations are performed to attempt to explain features observed in measurements and thus, it is hoped that a clearer situation of the picture will emerge.

A vertical MESFET shows very good intrinsic high-frequency properties, much better than that offered by manufactured devices. Parasitics cause the majority of differences observed and methods to reduce these are thus studied, which could improve the situation for vertical MESFETs.

Surface transport in SiC MOSFET devices is necessary for Monte Carlo simulations of these devices. In this work simplified models for the surface transport have been implemented and evaluated. Improved ways to reduce the computational requirements for Monte-Carlo device simulations is highly desirable. A time-domain drift-diffusion model that could be used in contact regions of the device is one possible solution and such a tool is implemented and evaluated in this work.

One aim of this work is to simplify the design process by developing a tool for automatic optimization using iterative device simulations. Better models for self-heating and linearity are also important for efficient device design, and, preferably, these should be accessible from the optimization tool. Both the accuracy and the computational efficiency are critical for such models.

1.2 Thesis Outline The thesis is arranged with a general introduction to field effect transistors in chapter 2 and silicon carbide in chapter 3. Chapter 4 is an introduction to device simulation together with the improvements accomplished by this work.

In Chapter 5 a review of SiC MESFETs that have been manufactured and modeled is presented. In this section the devices simulations conducted in this work are presented.

4 CHAPTER 1. Introduction

Chapter 6 contains a summary of the papers included in this thesis and the impact they have had on the research

In the last chapter the work is summarized and concluded. Some topics for consideration, which are a natural continuation of this work, are also presented.

2 Field Effect Transistors

2.1 MESFET MESFET (Fig. 2.1) is an abbreviation of MEtal Semiconductor Field Effect Transistor. The channel is depleted by a voltage applied to the gate contact, which is a rectifying Schottky junction between the gate metal and the channel. With a negative gate potential the channel is depleted, the current is reduced, and it reaches zero at the threshold voltage, VTh. The MESFET is very similar to the JFET (junction FET), where the gate Schottky-contact is replaced by a p-n junction.

A MESFET transistor can be designed using different topologies, as illustrated in Fig. 2.1. The most common MESFET design is to align the channel in a moderately doped conducting layer at the surface. The gate contact is a Schottky junction formed on top of the channel; the drain and source are ohmic contacts formed on a highly doped material. Either semi-insulating or p-type bulk material is used. The applied gate voltage depletes the channel from the surface down towards the bulk. A MESFET can also be oriented in the vertical direction, with the gate formed by metal in etched trenches. The advantage of this structure is that the channel length is not limited by the lithographic resolution, and shorter channels can be accomplished. The channel is depleted in the lateral direction from the gate fingers, which are located on the opposite sides of the channel. To achieve low parasitic drain resistance, the transistor structure is placed on high-doped substrate. One main drawback of this structure is the large capacitance between the gate pad and the high-doped substrate and the large parasitic drain resistance. As the channel is depleted from both sides, a reduced applied voltage is required to deplete the channel. The transconductance, (gm), defined in equation (2.1) is therefore higher than for a lateral MESFET with the same channel thickness.

konstVGS

DSm

DSdVdI

g=

= (2.1)

6 CHAPTER 2. Field Effect Transistors

n+

n+

ND

Drain

Gate

Oxide

GateSource Drain

n+ n+

Nch

Pbuf

Semi-insulating Bulk

B)A)

GateSource Drain

n+Nch

P or Semi-insulating Bulk

C)

n+

Source

Fig. 2.1. Different MESFET topologies. A) The lateral MESFET is the most widely used structure. B) A vertical MESFET is achieved by placing the gate fingers at the bottom of etched trenches. C) V-groove gate FET.

2.2 MOSFETs MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. The operation of the MOSFET is totally different to that of a MESFET. In an n-type MOSFET the semiconductor below the gate is lightly to moderately p-doped. By applying a positive potential to the gate, the P-doped layer is depleted and electrons are attracted to the gate forming an inversion layer, which constitutes the channel. A thin insulator prohibits a current from passing through the gate and a carrier inversion occurs close to the insulator surface.

For an N channel MOSFET a positive gate voltage is required to open the channel. This is very suitable for digital circuits, which are very simple for this technology, and MOSFETs are the most widely used transistors in present day consumer electronics. For low power digital electronics a symmetrical lateral MOSFET is used (Fig. 2.2).

The main difference between small-signal and power MOSFETs, such as the D-, U- and LD-MOSFET, is the existence of a drift layer between the gate and drain in the power device. In the drift layer the potential difference is distributed thus reducing the maximal electric field in the transistor. Due to the lower electric field, increased drain voltages are allowable and the high power performance improves. The DMOSFET can be designed as both a

2.2 MOSFETS 7

n+ n+

p

Source

Gate

Drain

n+ n+

p

Source

Gate

Drain

n+

n-

n+ n+

p p

Source

Gate

Drain

n+

n-

p+ substrate

p

n+ n+

p+ substrate

p

n+n

p -sinker+

n+

SourceGate

Drain

pp-

MOSFET LDMOSFET

DMOSFETUMOSFET

Fig. 2.2. Different common MOSFET structures. The lateral MOSFET is the most widely used structure for small signal digital applications. The LDMOSFET dominates in applications for RF power devices. The D and UMOSFET are for high power devices at lower frequencies.

lateral and a vertical device, both of which have a lateral channel, but which have different drift layer orientations.

For RF power applications the more complicated LDMOS structure is used, whilst for high power applications a vertical device such as the DMOSFET is preferred to increase the breakdown voltage even further. The channel in the DMOSFET is aligned horizontally below the oxide but as it reached the n- region the current turns vertically in the drift layer. In the UMOSFET structure both the channel and the drift region is aligned vertically. This allows higher packing density and reduced on-state resistance than the DMOSFET, which has caused its recent increase in popularity.

8 CHAPTER 2. Field Effect Transistors

1 10

5

10

15

20

25

30

35

40

[dB

]

f [GHz]

MSG/MAGh

21

Fig. 2.3. Illustration of the high-frequefMax.

x

2.3 Figures of Merit In the device community many devices exbehavior and performance. To make a compait is important to use a method for ranking high frequency devices there are two domingain frequency (fT) and the maximum oscillaThe unity current-gain frequency (fT) is deficurrent-gain (h21) drops to unity. It can be caratio of the transconductance and the gate cap

G

mT C

gfπ2

=

The unity current gain frequency is often useis almost always given in a high-frequency for its widespread use is the simplicitmeasurements and simulations.

A better figure of merit than fT is the maximwhich is the highest frequency where the devIt is calculated as the frequency where the 'mbecomes unity. MAG is the available gain unthe input and the output.

fT fMa

0 50

ncies figure of merits fT and

ist, each with totally different rison between different devices, the devices’ performances. For ant features, the unity current-tion frequency (fmax) (Fig. 2.3). ned as the frequency where the lculated approximately from the acitance.

(2.2)

d for device comparison, and it device publication. One reason y of calculating fT in both

um oscillation frequency (fmax), ice can be used as an amplifier. aximum available gain' (MAG) der matched conditions, both at

2.3 FIGURES OF MERIT 9

ID

IDmax

IDQ

IDmin

VK VDSQ VDSmax

VGSmax

VGSQ

VGSmin

VTh

Fig. 2.4. Class A operation for a power amplifier.

For high power devices an important parameter is the maximal power (PMax) that can be delivered to a load. In this work PMax is calculated assuming a class A operation, which means that the quiescent point is set symmetrically within the current and voltage range (Fig. 2.4) giving a maximal voltage and current swing.

2

max KDSDSQ

VVV += (2.3)

( ) ( )

2minGSDKD

DQVIVII +

= (2.4)

VDSmax is the maximal allowed drain-source voltage and VK is that voltage-drop in the on-state. VGSmin is the lowest allowed gate voltage for the signal, close to the threshold voltage, which for n-channel MESFET is a negative value. Assuming maximum current and voltage swing, PMax can be estimated by:

( ) ( ) ( )( )88

minmax GSDKDKDSPPPPMax

VIVIVVIVP −−== (2.5)

To compare device structures the output power per unit length is often used and is simply calculated as the PMax divided by the device width and consequently is given in W/mm.

3 Silicon Carbide Silicon carbide (SiC) is a very promising material for use in high-performance semiconductor devices. Among the most important transport parameters for electronic devices are the mobility (µ), saturation velocity (vsat), breakdown electric field (Ecrit), and thermal conductivity (λ). The mobility describes the mean velocity that the electrons and holes travel with when an electric field is applied. At low electric fields the velocity increases proportional to the field. At higher fields the proportionality is lost and the velocity is saturated at vsat. When the electric fields exceed Ecrit, the impact ionization becomes large, rapidly increasing the current, which destroys the material if the current is not limited. The thermal conductivity does not directly affect the performance, but with a good thermal conductivity it is easier to conduct the heat away from the chip to a heatsink. As the mobility and saturation velocity are reduced at high temperatures, a high thermal conductivity indirectly gives better performance for power devices.

In Table 3.1 the transport properties are listed for SiC and the most commonly used semiconductor materials. The advantages of SiC over Si are the twofold increase in saturation velocity, tenfold increase in breakdown fields, and the more than doubling of thermal conductivity. The carrier mobility in silicon carbide is somewhat lower than in silicon, but in general the transport parameters give silicon carbide devices better performance than comparable silicon devices.

SiC process technology has until recently been very immature and this has delayed a commercial breakthrough by several years. The process is continuously improving, and is presently reaching a level where commercial SiC devices are actually obtainable. Compared to silicon, SiC is very expensive, the wafers are of low quality, and they are difficult to process. However, both the material quality and the process maturity are improving rapidly, and the price is expected to drop, when large volume commercial devices are introduced into the market.

For SiC devices to be commercially successful, they have to offer improved performances to those achieved by using silicon technology. Power Schottky diodes [7] and Microwave MESFETs [4] are recently commercially

12 CHAPTER 3. Silicon Carbide

available SiC devices, which have to be able to compete with other technologies, both in price and performance. High-temperature electronics is another field, where silicon cannot compete above 300°C, due to the large intrinsic carrier concentration. In only a few years, SiC devices are expected to dominate high-temperature electronics. As the market share of SiC devices increases, it is assumed that other high frequency, high temperature, and high power switching devices will follow.

3.1 SiC Material Silicon carbide has been known for a long time to have good electrical properties, but until recently the material quality has not been acceptable for commercial devices. The major defects, which have stalled the development, are known as micropipes. These are formed during the growth process, and are formed throughout the whole wafer thickness, and totally ruin a device. It is now possible to find commercial wafers, which contain less than 5 micropipses/cm2 [8], thus making it possible to manufacture single devices with a high yield. Recently the crystal growth techniques have been improved even further and virtually defect free crystals are in sight [9]. For large integrated circuits and high-power devices, which require a large defect-free area, high quality is a must. The limitation of the active device or circuit size is calculated as the reciprocal of the micropipe density, and is now 0.2 cm2, which gives a 50% probability of a micropipe-free device. Other critical defects are dislocations, where about 0.1-10% is disastrous for device functionality [10]. Another problem discovered recently, is that of stacking faults growth during the operation of p-n junction diodes [11]. This is disastrous for bipolar devices as the stacking faults grow by means of the recombination energy. Unipolar devices do not suffer from stacking fault problems and in bipolar devices the effect is reduced through increased crystal quality. Recently a pin-diode has been operated for over 1000 hours without degradation [12].

Table 3.1. Material properties for some different semiconductors.

Si GaAs GaN 3C-SiC 4H-SiC 6H-SiC

vsat cm/s 1.0·107 2.0·107 2.5·107 2.0·107 2.0·107 2·107

µ0n Vs/cm2 1350 8500 800 750 950 420

EG eV 1.12 1.4 3.39 2.2 3.2 3.0

ni300K cm-3 1·1010 1.8·106 1.9·10-10 6.9 8.2·10-10 2.3·10-6

Ecrit MV/cm 0.3 0.4 3.3 1 2.2 2.5

λ W/cmK 1.7 0.5 1.3 3.6 3.7 4.9

3.2 TRANSPORT PROPERTIES 13

As the material quality increases, the main obstacle to the production of SiC commercial devices is the price of the material and the processing. However, as the production volumes of commercial SiC devices increase, both the material and production cost are reduced.

Silicon carbide is a new material, and the processes involved are different to those of silicon, and some of the process steps are still in their infancy. SiC is a very hard material and almost inert, which makes SiC processing problematical. Implantation of dopants is difficult to perform [13], especially p-type [14], and the etch rate is slow [15]. Schottky [16] and Ohmic [17] contacts are now fairly well developed processes in SiC. SiC epitaxial layer growth is also well established, and bulk wafers with an epitaxial layer structure are supplied from wafer manufacturers. Hence, the etching of structures in epitaxial layers is the most common method for the manufacture of SiC devices. SiC has SiO2 as its naturally occurring oxide, although the quality of the oxide layer reported is not as good as for silicon, suffering from both a low surface mobility and low breakdown strength. This is large drawback for MOSFET devices which would be very promising for high-temperature electronic devices. However, much research is focused on this particular area and the quality is constantly increasing.

3.2 Transport Properties A large part of this work has been devoted to discovering reliable transport parameters for different SiC polytypes, mainly 4H-SiC. For reliable estimations of device performance, this is very important, since the transport parameters have a large influence on the simulation results. Published measurements are the main source of information used in the tuning process of the transport models. The immature nature of silicon carbide, and lack of measurements for many transport properties, implies that the available set of transport parameters is incomplete. For additional transport parameters full-band Monte Carlo simulations are used to extract important parameters. The full band Monte Carlo model is based on theoretical calculations of the band structure, and can be used to extract many properties that are difficult to extract from measurements. In the Monte Carlo model a few parameters for scattering probabilities are matched against mobility measurements, thus the extracted values depend to some extent on measurements.

3.2.1 Mobility The mobility is a number that defines how easily the electrons and holes can be moved in an electric field. Due to random scattering within the crystal, the velocity does not increase with constant acceleration as in a vacuum. The electron velocity rather quickly reaches an equilibrium mean-velocity proportional to the mobility and the electric field.


Ev ee µ−= (3.1)

The mobility in SiC is somewhat lower than for silicon and much lower than in high-mobility materials, such as GaAs. The low mobility in SiC devices is compensated for by operation at larger electric fields taking advantage of the higher carrier velocity. To some extent the mobility can be described using the same models as those used for silicon. The parameters for the mobility models are collected from measurements for a temperature dependent mobility model [18]. In Paper IX, this model has been improved by adding temperature dependencies for the high field transport parameters vsat and β, extracted from Monte Carlo simulations.

3.2.2 Saturation Velocity At high electric fields the velocity ceases to be proportional to the electric field, due to increased scattering. The velocity saturates at vsat, which for SiC is approximately twice the value for silicon. A high saturation velocity allows faster devices with shorter switching times.

3.2.3 Band Gap The band gap is a forbidden zone in the energy spectra for a crystal. Without a band-gap the crystal is a metal, and with a large band-gap the crystal is an insulator. A semiconductor has a band-gap up to a few eV. For some traditional semiconductors the band gaps are: 1.11 eV for Si, 0.7 eV for Ge, and 1.4 eV for GaAs.

Many of the favorable transport parameters in SiC are related to the large band-gap, which is of the order of 3 eV. For such a large band gap the intrinsic carrier concentration is negligible at temperatures up to 600 degrees Celsius. The intrinsic carrier concentration is responsible for the thermal noise, and also partly responsible for the leakage current, which are both very small in large band-gap materials. The minimum energy required to create an electron-hole pair is equal to the band-gap that in SiC falls within the 3 eV range corresponding to a photon with wavelength close to 400 nm. SiC devices are thus also insensitive to the main part of the visible spectrum, making SiC suitable as a detector material for UV radiation with minimal noise from the visible background [19].

3.2.4 Critical Electric Field For high electric fields the carrier energy is increasing, and, as the energy exceeds the band-gap, the probability of an impact ionization event increases. In an impact-ionization event the carrier knocks out one electron from the valence-band, creating an electron-hole pair (EHP). As the energy

3.3 SIC POLYTYPES 15

must be conserved, the energy for the incident carrier is reduced by the band-gap energy plus the initial energy for the created electron and hole.

The critical electric field is related to the impact ionization rate, which increases as the carrier energy exceeds the band-gap. Due to the large band-gap the critical electric field is thus about 10 times higher in SiC than for small band-gap materials, such as Si and GaAs. With high Ecrit devices can be much smaller for the same voltage, alternatively operate at much higher voltages.

3.3 SiC Polytypes Silicon carbide exists in hundreds of different polytypes, the most common being 3C-, 4H- and 6H-SiC. Furthermore, islands of 15R can be found on 4H and 6H wafers, and small crystals of 2H-SiC have been grown [20]. The digit in the name is the number of double layers (one Si and one C layer) in the primitive lattice cell; and the character gives the type of crystal symmetry. H stands for hexagonal, C for cubic and R for rhombohedral. A schematic view of some of the different SiC polytypes is presented in Fig. 3.1. In the hexagonal structure a clear distinction exists between the different directions in the lattice. The direction parallel to the central axis in the hexagonal structure is called the crystal axis, or c-axis. In commercially available wafers the c-axis is normally oriented perpendicular to the surface, usually being a few degrees off axis. The transport parameters for the most common SiC polytypes, together with some other semiconductors, are presented in Table 3.1.

3.3.1 6H-SiC 6H-SiC has a large anisotropy due to the long repetition length in the crystallographic lattice. The mobility in the direction perpendicular to the c-axis (commonly parallel to the surface) is four times greater than in the c-axis direction [21]-[23]. Compared with Si the mobility in 6H-SiC is about 25% in the direction perpendicular to the c-axis, and 7% in the direction parallel to it. The saturation velocity for 6H-SiC is 2⋅107 cm/s in the direction perpendicular to the c-axis, but only 0.6⋅107 cm/s in the direction parallel to it.

3.3.2 4H-SiC The low-field mobility for 4H-SiC is about half that of silicon with a small anisotropy (20% higher in the direction parallel to the c-axis) [21][22][24]. The anisotropy in 4H-SiC depends on the electric field, and at high electric fields the saturation velocity is 20% lower in the c-axis direction.


Fig. 3.1. Schematic structure for some different SiC polytypes.

4H-SiC and 6H-SiC are the most mature polytypes and they are the ones which have been characterized most thoroughly. The transport properties are better for 4H-SiC and, at present, this polytype forms the basis for most of the commercial products.

3.3.3 3C-SiC 3C-SiC has an advantage as it is able to be grown on silicon substrates, however at the moment with reduced quality. This allows for the possibility in the future of integration of 3C-SiC devices with silicon technology on the same chip. Another advantage is that 3C-SiC does not suffer from stacking faults growth, as these tend to grow towards 3C-SiC. 3C-SiC has larger electron mobility than for 4H-SiC but has reduced hole mobility. The main disadvantages when compared to other polytypes are the lower band-gap and breakdown field and the advantage of replacing existing silicon devices is strongly reduced.

3.3.4 15R-SiC 15R-SiC is very complex, namely 15 atomic layers ordered in a rhombohedral structure. A few years ago, much attention was focused on 15R-SiC, owing to improved experimental MOSFET performance when compared to the other polytypes. These devices have been manufactured on 4H- or 6H-SiC, where pieces of 15R-SiC were found. Mono-crystalline 15R-SiC wafers are however not a reality in the near future.

3.4 CARRIER FREEZE OUT 17

3.3.5 2H-SiC 2H-SiC is not a commercially available substrate, but small mono-crystalline pieces have been grown [20]. Monte Carlo simulations predict that the performance perpendicular to the c-axis direction is similar to 4H-SiC, but the mobility is better in the parallel to the c axis direction (similar to silicon) [25].

3.4 Carrier Freeze Out The large band-gap is in most cases favorable, but it also causes one of the largest disadvantages of SiC, namely the energetic deep doping levels. The energy levels for the doping materials used in silicon carbide are located at a significant distance from the band-edge, and at low temperatures a fraction of the carriers are not thermally activated, i.e. they are instead frozen in the band-gap without being ionized. The best dopant in SiC is nitrogen (n-type), which is a donor located in the range of 50-80 meV [26][27] from the conduction band-edge. For P-type doping Al is often used, with an ionization energy above 200 meV [26]. The ionization energy should be compared to the mean thermal energy for the carriers at room temperature, kBT=25.9 meV. Poisson statistics determine the donor freeze out. The number of free carriers is calculated according to (2.2).

kT

EED

eff DF

eg

Nn −

⋅+=

1 (3.2)

ND is the doping level, g is the degeneration factor, EF is the Fermi energy, and ED is the energy relative to the band-edge for the doping atom. The fraction of ionized carriers as a function of the doping level is shown in Fig. 3.2. At low doping levels most of the carriers are ionized at room temperature, but the fraction is reduced at higher levels. The reason for this behavior is due to the Fermi-level, which is also a function of the doping concentration. At low doping levels the Fermi-level is located in the middle of the band-gap, which gives a negative number in the exponent, which accordingly approaches zero.

The Fermi energy approaches the band edge as the doping concentration grows, and the fraction of ionized carriers is reduced. However, in high- doped materials the impurity energy level also decreases, which is not taken into account in Eq. 3.2. In Fig. 3.2 the fraction of ionized electrons and conductivity for 4H-SiC as a function of the doping level is shown. The conductivity is calculated from the concentration of electrons / holes (n/p), the mobility (µ), and the electron charge, (q).

he pqnq µµσ += (3.3)


1015

1016

1017

1018

1019

1020

10−2

1

102

104

Res

istiv

ity [Ω

cm]

Doping concentration [cm−3]10

1510

1610

1710

1810

1910

20−0.4

−0.2

0

0.2

0.4

0.6

0.8

1

1.2

Fra

ctio

n Io

nize

d C

arrie

rs

Fig. 3.2. Fraction of ionized carriers and the corresponding conductivity for 4H-SiC using the donor energy level ED=52 meV [26] calculated from the mobility in ref [21] using eq 3.3. The solid line is calculated with full ionization at high doping levels.

The metal, non-metal transition is predicted to occur at 5.6·1018 cm-3 [28]. At high doping levels the incomplete ionization is modeled as a linear transition from incomplete ionization below ND=1·1018 cm-3 to full ionization at ND=1·1019 cm-3 and above [29] which reduced the resistivity one order of magnitude for highly doped SiC.

3.5 Thermal Conductivity The thermal conductivity for SiC is close to that for copper, a quality that is very important in power semiconductor devices in order to transport the heat from the power dissipated in the device.

For high power devices the thermal effects constitute one of the main limiting factor of the performance. One of SiC´s competitors is gallium-nitride (GaN), which is a material with similar properties to those of SiC but which are less mature. One drawback of GaN is the even lower thermal conductivity than that in silicon (1.3 W/cmK). However, GaN is often grown on SiC substrates, with its better thermal conductivity. Nevertheless, the GaN-SiC interface has lower thermal conductivity than GaN itself [30] which leads to a degradation of the performance.

3.6 SURFACE MOBILITY 19

2 3 4 5 6 7 8 9 1010

2

103

104

105

106

107

Impa

ct io

niza

tion

coef

ficie

nt [1

/cm

]

Inverse electric field [10−7 cm/V]

Expr. Konstantinov et al. elec.Expr. Konstantinov et al. holesExpr. Raghunathan et al. holesExpr. Hatakeyama et al. elec.Expr. Hatakeyama et al. holesMC Elec., no band tunnelingMC Holes, no band tunnelingMC Elec., KI modelMC Holes, KI model

Fig. 3.3. Impact ionization coefficients for 4H-SiC in the direction parallel to the c-axis.

3.6 Surface Mobility The surface mobility describes the transport in the inversion layer of a MOSFET device and is critical for device performance. Pioneering experiments have given very poor values for the surface mobility in SiC devices in the range of 10 cm2/Vs. The low mobility is related to the high defect density in the oxide-semiconductor interface and doubts about SiC MOSFETs as commercial devices have been expressed in many quarters. The mobility is presently reaching values above 150 cm2/Vs [6] and commercial MOSFETs are expected to appear in the market shortly. The surface mobility for silicon carbide MOSFETs is discussed in more detail in section 5.3.

3.7 Impact Ionization For high-power devices the impact ionization process is very important for accurate predictions of the high power performance. In silicon carbide the impact ionization is not fully understood, even though the process has been studied throughout the last two decades [31]-[43]. Many of the pioneering measurements reported a positive temperature coefficient of the impact ionization coefficient. As the impact ionization heats the lattice, such a behavior would further increase the impact ionization. This would be a very serious problem, causing local hot spots, unstable operation and thermal runaway, destroying the device. In later measurements the impact ionization coefficient shows a negative temperature dependency and thus the positive


2 3 4 5 610

4

105

106

Impa

ct io

niza

tion

coef

ficie

nt [1

/cm

]

Inverse electric field [10−7 cm/V]

MC Overlaptest ElecMC Overlaptest HoleHatakeyama ElecHatakeyama Hole

Fig. 3.4. Impact ionization coefficients for 4H-SiC in the direction perpendicular to the c-axis.

sign presented previously was mainly contributed to by the presence of deep levels in the samples used.

In Fig. 3.3 the most important measurements and calculations of the impact ionization coefficients in the c-axis direction in 4H-SiC are presented. The two most important measurements performed until recently have been made by Konstantinov et. al. [37] and by Raghuantan and Baliga [38]. There is a significant contradiction between these two measurements as the reported impact ionization coefficients differ by approximately a factor of 5. Theoretical studies report that the large anisotropy in the impact ionization coefficients is expected [39]. In paper III it has been shown that both measurements [37] and [38] could be unified and explained by large anisotropic impact ionization coefficients. However, at high impact ionization direct optical transitions in the subbands [40] or through midgap levels [41] is present producing luminescence. If the higher impact ionization rates reported by Konstantinov et. al. had been be caused by anisotropic impact ionization rates, then it would be expected that the luminescence during breakdown would be localized near the edges, which is not the case in the measurements where the light emission is nearly uniform [42].

Recent measurements [43] support the theory regarding anisotropic impact ionization coefficients and reported 60% reduced breakdown voltage in devices fabricated on ( 0211 ) wafers compared with (0001) devices.

3.8 MINORITY CARRIER LIFE TIME 21

Newly developed models for the advanced transport including band-to-band tunneling [44][45] predict less anisotropy than previous models. In the c-axis direction the model includes band-to-band tunnelling and gives impact ionization coefficients close to the values reported by Konstantinov et.al. and Hatakeyama et.al. The reported values in the direction perpendicular to the c-axis direction are presented in Fig. 3.4. The theoretical calculations here are based on a simpler and a less correct model. The impact ionization coefficients are of the same order as reported by Hatakeyama, but electrons dominates rather than the holes reported in the measurements.

3.8 Minority Carrier Life time In many devices the performance is directly dependent upon the lifetime of the minority carriers. The minority carrier lifetime (τ) is strongly related to the crystal quality and defects, which reduces the lifetime considerably. The lifetime of SiC has been investigated in several experiments over the past few years [46]-[51]. The highest reported values are up to 2 µs at room temperature, which is achieved in thick (40-60 µm) CVD grown epitaxial layers [48][49]. The lifetime decreases with the epitaxial layer thickness and for a 10 µm thick epitaxial layer the lifetime is 0.2 µs because of both higher surface and junction recombination rates. It should be mentioned that in thin, doped channel layers the lifetime is even smaller than these values. An increased surface recombination rate is very commonly seen in semiconductor device technology due to dangling bonds caused by imperfections at the surface termination. In SiC an increased recombination rate is also observed in the metallurgic junction between the epilayer and the substrate. By introducing a lifetime shorter than 1 ns in the volume closer than 0.1 µm to the metallurgic junction, contradictions between steady-state and transient current can be explained [51] using simulations. A highly reduced lifetime is also observed in the junction region in the measurements presented in refs [46] and [48]. A reduced lifetime in the junction region can be an advantage for switching diodes and is sometimes created deliberately in silicon diodes by irradiation. The reverse recovery time is reduced, which increases the switching speed. This is preferable to a reduced lifetime within the whole base region of the diode, which increases the series resistance and consequently increases the forward losses.

3.8.1 Theoretical Device Performance A simple calculation is performed to illustrate the benefits that can be accomplished using SiC instead of Si. Assuming that a diode is to be manufactured that must be able to withstand a minimal blocking voltage of VBlock, the depletion width (w) for a diode with a single sided depletion region at high voltages can be expressed as


Crit

Block

D

Block

EV

qNV

w ==ε2

(3.4)

ND is the doping concentration, ε the permittivity of the semi-conductor and q the electron charge. The blocking voltage is then ECrit times the depletion width, w. Squaring both terms in equation 3.5 gives the following form.

DCrit

Block

qNEV ε2

2 = (3.5)

The critical electric field is 10 times higher for SiC than for silicon, allowing a 100 times higher doping concentration for the same breakdown voltage.

The transit time, tt, is the time it taken for a carrier to travel across a device, which can be approximated to

sat

t vwt = (3.6)

The saturation velocity in SiC is twice as high as that for Si and the depletion width is reduced 10 fold according to eq 3.5. This gives a transit time which is reduced by a factor of 20 compared to its silicon counterpart.

The current density, J, is dependent on the carrier concentration, ND, and the saturation velocity.

satD vqNJ = (3.7)

As the doping level could be kept two orders of magnitude higher than for silicon and vsat is twice the silicon value, the current density is 200 times higher for the SiC device.

The required device area (A) for a given current is directly proportional to the current density and is 200 times lower for the SiC device. The junction capacitance (C) is proportional to the area divided by the depletion width. The depletion width is 1/10 in SiC giving a capacitance reduction by a factor of 20 for the SiC device compared to a silicon device with the same current.

The leakage current for a p+-n junction can be described as the sum of the diffusion current and the generation current in the depletion region.

g

i

D

i

p

p wqnNnD

qJττ

+=2

(3.8)

Dp is the diffusion constant, τp the minority carrier lifetime, ni the intrinsic carrier concentration and τg the generation lifetime. The intrinsic carrier

3.8 MINORITY CARRIER LIFE TIME 23

concentration is 1020 times smaller in large band-gap materials such as SiC when it is compared to Si. This term dominates both contributions, which gives a very small leakage-current compared to that of a similar device manufactured in silicon.

A similar diode manufactured in SiC instead of Si can thus be manufactured on an area which is 200 times smaller and be 20 times faster with negligible leakage current.

Assume instead that a diode with maximum blocking voltage has to be designed. According to eq 3.6 the tenfold increase in Ecrit allows a 100 times increase in blocking voltage for the same doping level. It should be noted that at present the crystal quality is not as good as for silicon and doping levels below 5⋅1015 cm-3 are difficult to realize. However, Schottky diodes with blocking voltage of 4.9 kV and pin-diodes with blocking voltage as high as 8.6 kV have been successfully demonstrated [52].

Another drawback that has not been accounted for in this example is the donor freeze-out due to incomplete ionization. The fraction of ionized carriers at room temperature is shown in Fig. 3.2 as a function of the doping concentration. The current density is thus reduced in a similar manner. However at low doping-levels, which are used in the base region of high voltage diodes, the fraction of ionized carriers is still high.

Similar calculations can be performed for any of the known semiconductor devices and a mature process technology would ensure a strong position for SiC in the semi-conductor devices industry for high-performance devices.

4 Semiconductor Device Simulations Semiconductor device simulations have become a very important tool for device design due to the large development cost for new technologies. In device design the performance of an individual transistor is simulated, and the layout is optimized for the best performance based on given restrictions. The device performance is described by macroscopic values such as current, voltage, and capacitance. These macroscopic values depend on a number of microscopic values within the device, which all have to be known before the device performance can be calculated.

The basic idea with regards to semiconductor simulations is to apply a potential or current to some defined terminals, and to calculate the behavior of the microscopic properties, such as carrier concentration, velocity, carrier energy, and potential, within the device. Each of these quantities depends on the position in space, and a grid (mesh) is defined in the device, usually in 2-dimensions. The third dimension is in most cases regarded as being uniform, and the device parameters are all expressed in terms of per unit of length. In this section the most fundamental parts of semiconductor device simulations are described. For a more in-depth treatment ref. [53] is recommended.

The potential (V) is in most cases calculated from Poisson’s equation, which is usually solved numerically by a coupled system of partial differential equations, PDEs.

ερ

−=∇ V2 (4.1)

The potential depends on the charge density distribution (ρ) within the device and the permittivity (ε). The electric field (E) is calculated from the gradient of the potential.

VE −∇= (4.2)

Device simulation methods are divided into two groups; Particle based and concentration based. In particle based simulations the trajectory of individual carriers is calculated, whilst in concentration based methods, the carrier concentration is calculated. In the particle-based Monte-Carlo method,

26 CHAPTER 4. Semiconductor Device Simulations

Fig. 4.1. Example from electron distribution in a Monte Carlo simulations of a vertical SiC MESFET.

different levels of approximations are introduced to deal with the problem’s complexity. Today the most advanced models are based on the full band Monte Carlo method with k-vector dependent scattering rates, and band-to-band tunneling between subbands included. Concentration based methods are categorized according to the level of approximations used. The most commonly used models are different hydrodynamic models and the drift-diffusion method.

4.1 Monte Carlo Method In the Monte Carlo method the trajectory of every individual particle is calculated under the influence of the electric field, the semiconductor band structure, and scattering processes, which are selected randomly at each scattering event. In Fig. 4.1, examples of the carrier distribution in a device simulation of a SiC vertical MESFET are shown. Both the position in real space and the carrier energy are shown. The larger dots correspond to electrons that are localized in the 2nd band. Using a large number of particles, the result is a good approximation to the transport in real devices. The Monte Carlo method is the most accurate technique available for device simulations. It is, however, very computationally consuming due to the large

4.1 MONTE CARLO METHOD 27

number of carriers and the detailed description of the underlying physical models.

The Monte Carlo simulation program is based on three important parts: the band structure, a number of scattering models, and a method for solving Poisson’s equation. In the full band Monte Carlo simulator developed at Mid-Sweden University (GEMS), the band structure is implemented as a lookup table, containing the energy and energy gradient in the irreducible wedge of the Brillouin zone. A number of symmetry operations are defined to transform each point in the Brillouin zone to the irreducible wedge and back again. The band structures used in this work are based on band-structure calculations presented in references [54]-[56]. The scattering processes considered in the simulations are: acoustic phonon scattering, polar-optical phonon scattering, optical intervalley phonon scattering, as well as ionized and non ionized impurity scattering. For the acoustic and optical phonons, the coupling constants are obtained by fitting the mobility as a function of temperature from bulk simulations to experimental data [21][22].

The potential is calculated self consistently from the charge distribution using Poisson’s equation, eq. 4.1, where the charge from each single carrier is distributed across the nearest mesh cells. In this way the information about its position within the cell is accounted for. The electric field is determined from the potential gradient (Eq. 3.2). From the electric field the velocity in k space (vk) is calculated according to Eq. 4.3.

h

qEvk−

= (4.3)

The velocity in real space (v) is determined from the k-vector energy gradient, Eq. 4.4.

εkv ∇=h

1 (4.4)

In Monte Carlo simulations, small devices have an important advantage in that a reduction in the number of carriers also gives a reduction in computational time compared to larger devices. It should be noted that small devices are the most difficult to simulate accurately using regular drift-diffusion or hydrodynamic device simulators due to the limitations in these models.

The strength of the Monte Carlo method is the high detail level of the underlying physics, where relatively few approximations have to be made and there are few empirical parameters involved. This makes it possible to use the Monte Carlo method to extract material parameters, which are


0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

M ΓL K

Ene

rgy

[eV

]

M−Γ (x)M−K (y)M−L (z)

K

HL

M

A

Γ

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4−2

0

2

4

6

8

time [ps]

Vel

ocity

[107 c

m/s

]

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.40

0.05

0.1

0.15

0.2

time [ps]

Pos

ition

[µm

]

(a) (b)

Fig. 4.2. Electron transport in 6H-SiC using the Monte Carlo method. (a) The band-structure for 4 conduction bands in 6H-SiC close to the band-minima in the M-point. The carrier movements are illustrated assuming an applied electric field of 1·105 V/cm in three crystal directions, without scatterings. (b) The velocity and position in real space for the same case.

difficult or impossible to measure. This has been a great advantage in the study of SiC properties, where many of the transport parameters have not been experimentally determined. In this work the Monte-Carlo method has been used for studies in the polytypes 2H [25], 4H [24] and 6H-SiC [23].

In Fig. 4.2 an example of the electron transport in 6H-SiC is illustrated. 6H-SiC is a material with hexagonal symmetry and where the conduction band minimum is at the M-point in the Brillouin zone. In 6H-SiC the unit cell is very long in the c-axis direction, see Fig. 3.1. The dimensions of the Brillouin zone are calculated by a Fourier transformation of the real space unit cell, resulting in a very short distance between the M and L points in k-space. The band-structure from the conduction band minima in the M-Γ, M-K and M-L directions is shown in Fig. 3.1a, where the anisotropy is obvious. The effective mass is a direct measure of the curvature of the band structure in band minima, and is calculated as:

2

2*

dkd

mεh

= (4.5)

This means that a small curvature corresponds to a heavy particle with low mobility according to Eq. 4.5. In Fig. 4.2 the movement of electrons in 4H-SiC is illustrated in three orthogonal directions assuming constant electric

4.1 MONTE CARLO METHOD 29

field and no scattering events. Where the condition of a constant field applies, a carrier moves with constant velocity in k-space which is illustrated in Fig. 4.2a by symbols separated by 50 fs in time. A carrier reaches the zone boundary in the M-L direction first. As a carrier is crossing the zone boundary in the L point it reenters at the –L point and changes from the 1st to the 2nd band (Changes direction in the irreducible wedge in k-space). Next time it passes the L-point it changes back from the 2nd to the 1st band and after reaching the M point it starts all over again. This cycle has some interesting features in real space as shown in Fig. 4.2b. The velocity becomes negative after it passes the M-point in k-space for the first time. The carrier is thus moving in the opposite direction to that expected due to the electric field. After one full cycle the carrier has returned to the original position and appears not to have moved at all. This phenomenon is called Bloch oscillation and occurs in all directions provided there is no scattering.

4.1.1 Scattering events In order to understand the carrier transport in semiconductor devices more features must be added, namely scatterings, which are very important for accurate carrier transport in semiconductors. The importance of scattering events is illustrated by the previous example and is required for the electrical transport in semiconductors except for very short distances where scattering free (ballistic) transport is possible. High scattering rates decrease the mobility, since the carrier velocity is, in most cases, reduced by scattering events. The carrier moving in the material will sooner or later interact (scatter) with other carriers, impurities, or lattice vibrations (phonons). In these scattering events the position in k-space changes abruptly and the carrier can either gain or lose energy depending on the type of scattering. In real space the momentum changes abruptly, giving the carrier a new velocity and direction.

4.1.2 Carrier heating One more interesting point that can be explained from Fig. 4.2a, is the anisotropy of carrier heating. Assume a carrier which is moving in an electric field in the M-L direction. In order to achieve carrier energy above 0.2 eV the electron must reach band 3 or 4, which is only possible by means of several scattering events that give the carrier a total additional energy of 1 eV. Such a chain of events is very unlikely, and the carrier energy is thus limited to energies below 0.2 eV for the main part of the carriers. Carriers moving in the M-Γ direction can reach several eV accelerated by the electric field alone, which gives a much higher mean carrier energy. Consequently, the impact ionization rates are expected to be much higher, and the electric breakdown field lower, in the M-Γ direction (perpendicular to the c-axis).


4.1.3 Poisson’s equation The potential within the device is calculated from the carrier concentration using Poisson's equation (4.1). The mesh in the device simulator has to resolve the Debye length, LD [57].

d

D NqkTL 2

ε= (4.6)

As the carriers might travel for too long before they will affect the electrical field, oscillations not existing in the real device might occur in the simulation if this condition is not fulfilled. As the Debye length is very short in high-doped regions, the Debye length condition requires a dense mesh for accurate simulations of contact regions, which are often of limited interest for the device operation. A non uniform mesh may also result in artificial forces [58] on the carriers in Monte Carlo simulations if the carrier is not distributed over the neighboring mesh cells correctly. In GEMS the mesh needs to be both uniformly spaced and the Debye length resolved in the highest doped areas. For a large device this leads to an extremely large mesh size, and the solution of the Poisson’s equation totally dominates the simulation time.

Monte Carlo simulations are hence used only for the active part of the device, including as little as possible of the contact regions. The doping levels in the contact are also kept relatively low to allow a less dense mesh without oscillations.

4.2 Hydro-Dynamic Model Electrical device simulations are based on the Boltzmann transport equations (BTE). BTE is a bookkeeping equation for the probability of finding a carrier in a specific time and place in both real and k-space.

( tstfff

tf

collkr ,,krFv +

∂∂

=∇⋅+∇⋅+∂∂ ) (4.7)

BTE describes the dynamics of the carrier distribution function (f) in both real (r) and momentum (k) space. F is Force, s is the generation and recombination function, t is time, and v is velocity.

From Boltzmann’s transport equations a number of balance equations can be derived, which individually describe different physical properties, such as the carrier density, carrier momentum, energy density, and the energy flux. Carrier position and energy change in time and space are described by the balance equations. The models using the balance equation for both carrier and energy are called hydrodynamic models.

4.3 DRIFT-DIFFUSION MODEL 31

105

106

0

10

20

30

40

50

60

70

80

90

100

Electric Field [V/cm]

Ene

rgy

rela

xatio

n tim

e [fs

]

4H−SiC ⊥ c4H−SiC || c 6H−SiC ⊥ c6H−SiC || c

Fig. 4.3. Energy relaxation time as function of the electric field for electrons in 4H and 6H-SiC.

The energy flow is characterized by the energy relaxation time (τrel), which gives the time constant for the energy loss by scattering. In the hydrodynamic models used relaxation time is approximated by a constant. The constant relaxation time approximation is valid at low fields, when the dominant scattering mechanism is elastic or isotropic.

In SiC the polar-optical scattering mechanism is dominant, and it is neither elastic nor isotropic. The relaxation time, displayed in Fig. 4.3 for 4H and 6H-SiC, has been extracted from Monte-Carlo simulations. It is clear that τ is both anisotropic and field dependent and if the hydrodynamic model should be used for SiC a field dependent relaxation time should be used.

4.3 Drift-Diffusion Model The most computationally efficient transport model is the drift-diffusion model. This is an approximation, where the diffusion term is simplified. The diffusion is in general a function of the gradient of both the carrier density and carrier temperature. In the drift-diffusion approximation the influence of the carrier temperature gradient is ignored, and only the carrier density gradient is considered. This of course has some implications for the results produced. The validity of the approximation is acceptable, as long as the variations in the carrier temperature are moderate. At low-field transport, and near-equilibrium conditions, the drift-diffusion approach successfully describes the carrier transport. The model can also be used for high-field transport, as long as the gradient in the carrier-temperature is small.


104

105

106

106

107

Car

rier

velo

city

[cm

/s]

Velocity ⊥ C Velocity || C Mean Energy ⊥ CMean Energy|| C

104

105

106

0

2

4

6

8

10

12

14

16

Car

rier

tem

pera

ture

[100

0K]

Electrical Field [V/cm]10

410

510

610

5

106

107

Car

rier

velo

city

[cm

/s]

Velocity ⊥ C Velocity || C Mean Energy ⊥ CMean Energy|| C

104

105

106

0

2

4

6

8

10

12

14

Car

rier

tem

pera

ture

[100

0K]

Electrical Field [V/cm]

Fig. 4.4. Carrier velocity and energy as function of electric field extracted from Monte Carlo simulations. The solid lines correspond to the best fit for the Caughey-Thomas transport model in (eq 4.9). Left) 4H-SiC. Right) 6H-SiC.

4.4 High-Field Transport For high electric fields the number of scattering events increases, resulting in a saturation of the mean carrier velocity. In a device simulation the mean carrier velocity is expressed as the mobility multiplied by the electric field and for this reason the mobility for high electric fields is reduced.

Ev µ= (4.8)

For high-field drift-diffusion simulations the Caughey-Thomas expression for mobility (µ) is commonly used.

ββ

µ

µµ 1

0

0

1⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛+

=

satvE

(4.9)

This gives the overall form for the transition for the mean velocity from µ0E at low field to vsat at high electric fields, where µ0 is the low field mobility. The curvature parameter β is used for tuning the transition for medium fields. In Fig. 4.4 the carrier velocity as a function of the electrical field extracted from full-band Monte-Carlo simulations is shown for both 4H- and 6H-SiC.

In the hydrodynamic model the electric field is replaced by an effective field, which depends on the carrier temperature (u), lattice temperature (u0) and

4.5 TIME REDUCTION IN MONTE-CARLO SIMULATIONS 33

0 2 4 6 8 1010

15

1016

1017

Distance (µm)

Ele

ctro

n co

ncen

trat

ion

Time Independent SolTime Domain Solution

0 1 2 3 4 50

50

100

150

VD

[V]

I D [m

A/m

m]

Time Independent SolTime Domain Solution

Fig. 4.5. Comparison of simulation between a time-domain and a time-independent solution for the drift-diffusion equations. Left) Mid-channel concentration in a turned-on Si vertical MESFET. Right) IV characteristics for a Si MOSFET.

relaxation time (τrel). The temperature-dependent mobility in the hydrodynamic model is calculated as.

( )ββ

τµ

µµ 1

020

0

23

1⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎦

⎤⎢⎣

⎡−+

=

uuv relsat

(4.10)

4.5 Time reduction in Monte-Carlo Simulations The main drawback of the Monte Carlo Method is the large computational power required. This demand increases for large devices because of the increased number of carriers. To reduce the simulation time required, super-particles [2] are often used instead of simulating each electron and hole. For realistic device simulations high-doped areas are still a problem, since most of the carriers are located in these regions. The high-doped regions are usually working as low resistive regions, and are not of major importance for transport within the device. In these cases it may be wasteful to spend most of the simulation time for these high-doped regions. One way to reduce the simulation time is to use adaptive carrier scaling [59], where the carrier scaling factor is handled dynamically within different regions of a device with a large scale factor in high-doped regions. A way to reduce the simulation time further is to use a high-level model such as the drift-diffusion [60] model locally or initially.


Commercial drift-diffusion simulators calculate time-independent solutions for the transport equations. However, a time-independent solution is not necessary for regional incorporation with an ensemble Monte Carlo simulator, since this is itself a time-domain solution. It is thus sufficient to solve the drift-diffusion equation in the time domain. This substantially simplifies the incorporation of a drift-diffusion model, and the two models can be used in different parts of a device.

In this work a time dependent drift-diffusion simulator is developed to evaluate the concept and verify that the time dependent solution agrees with commercial semi-conductor simulation software using the same models. In Fig. 4.5 a comparison between the two models is shown for the carrier concentration in a Si vertical MESFET and for an IV plot for a Si MOSFET. The two models are in good agreement and the time dependent model can thus be integrated into the Monte-Carlo framework so that it could be used in contact and bulk regions in device simulations. A simpler way of incorporation DD with MC is to use the model in the start-up of a simulation and in this way start the Monte-Carlo simulation from a steady-state solution reducing the time until the simulation converges.

4.6 Anisotropic Simulations As discussed in previous sections many of the transport parameters in SiC are anisotropic due to the hexagonal lattice, which has to be accounted for in device simulations. In drift-diffusion and the hydrodynamic model in the Medici package used in this work [1] this is implemented as a constant scaling factor for the mobility (and other parameters) in the x-, y- and z-directions, which is based on ref [61]. This model can be used for SiC with fairly good results, if the transport properties are handled with great care. To achieve the best results the transport model should be tuned for transport parallel to the current direction. In the perpendicular direction the anisotropic factor should be chosen for the best low-field mobility agreement. In both 2H- and 6H-SiC the anisotropy is fairly constant, which gives good results even if the current is not purely one-dimensional. In 4H-SiC the anisotropy changes from 80% to 120% (Fig. 4.4), which gives inaccurate results using a constant scaling factor in a device with two-dimensional current flow. A better way to describe the anisotropy would be to have separate values of the constants in the mobility expression for the two directions. It is however not a problem in devices as long as the channel is straight as the electric field in the contact regions is low.

4.7 SIC DEVICE SIMULATIONS 35

4.7 SiC Device Simulations One main problem for SiC device simulation has been the shortage of reliable measurements of many of the transport parameters. Furthermore, anisotropic transport models have to be used, contrary to isotropic materials such as Si and GaAs. The degree of anisotropy is not constant, which is assumed in the anisotropic model used in Medici. In SiC the mobility, saturation velocity, relaxation time, and impact ionization coefficients are some of the parameters, all being anisotropic. Mote-Carlo simulations predict a negative differential mobility for high electric fields. No measurements are performed at such high fields and the implemented high-level mobility models cannot be fitted against the calculations.

In paper I the influence of mobility and saturation velocity is studied in 4H- and 6H-SiC device simulations. In the same paper the relaxation time is reported to be both anisotropic and electric-field dependent. The influence of anisotropic impact ionization coefficients in 4H-SiC has been studied in Paper III.

Some theoretical works on SiC devices are presented both as simulations [62]-[71] and device modeling [72]-[75]. The simulations are used for predictions of the SiC device performance, evaluation of new device concepts, understanding of measurements, and for studies of simulation methods. Device modeling can be divided into two categories: physics-based models and empirical models. The physics-based model relies on physical device parameters, and preferably uses no empirical data. The advantage of physics-based models is that it can be used both for rapid optimization of device structures, as well as circuit simulations. It is however often very difficult to extract a physical model for state-of-the art devices, since the short-channel effects and two-dimensional effects cannot be ignored. In this case device design and optimization can be performed instead, using iterative device simulations, a more computer-time consuming task but still fully possible.

It is simpler to extract an accurate empirical model for a device, but such a model can only be used for circuit simulations, and only a few conclusions can be drawn regarding how the device dimensions affect the performance.

4.7.1 Mobility and Saturation Velocity The anisotropic transport properties of SiC are generally not constant, and in some cases parameters even change from less to more than unity, meaning that the most favorable transport direction changes with the applied field. Hence, a model of the field dependent anisotropy is necessary to accurately describe the transport in SiC. This is not possible using constant mobility anisotropy. To minimize the errors the transport properties have to be


104

105

106

106

107

Electric field [V/cm]

Mea

n ca

rrie

r ve

loci

ty [c

m/s

]T=300K

T=700K

Fig. 4.6. Electron velocity as function of the electric field for temperatures between 300 and 700K. The symbols are full-band Monte Carlo simulations and the lines are the best fit of high field transport parameters vsat and β in eq 4.9.

altered, depending on the orientation of the device. Accordingly, two sets of transport parameters are used: one for transport parallel to the c-axis, and one for the perpendicular direction (parallel to the surface on a (0001) wafer). In a device where the current is mostly confined within one direction this approximation is still very good. In devices where the channel is one dimensional and, for instance, contact regions are localized in the perpendicular direction, the method gives good results as the field in the contact regions is low. In a more two-dimensional device, such as the DMOSFET, this approximation gives an incorrect transport picture, and the influence of the incorrect model can be estimated from the difference in the high/low field anisotropy. The only way to solve this problem is to use better anisotropic models of the transport properties.

In 4H-SiC the anisotropy in mobility is fairly small and switches from below to above one. At N=1⋅1017 cm-3 the low field mobility is 730 cm2/Vs parallel to the c-axis and 610 cm2/Vs in the perpendicular direction. The corresponding saturation velocities are 1.7⋅107 and 2.0⋅107 cm/s. With a constant factor for the anisotropy, it is not possible to achieve the correct transport in the direction perpendicular to the main current direction, where only the low field parameters are valid. However, in this direction the electric field is often low, and the approach can be used with good accuracy. The mobility models used in the device simulations are based on extraction

4.7 SIC DEVICE SIMULATIONS 37

300 350 400 450 500 550 600 650 7001.2

1.4

1.6

1.8

2

2.2

2.4

2.6x 10

7

Temperature, T [K]

Sat

urat

ion

velo

city

, vsa

t [cm

/s]

300 350 400 450 500 550 600 650 7000.7

0.8

0.9

1

1.1

1.2

1.3

1.4

β

||C⊥Cβv

sat

Fig. 4.7. Analytical model for the high field transport parameters vsat and β. The symbols are the extracted values from Fig. 4.6 and the solid lines represent the model in eqs 4.13-16.

from state-of-the-art measurements by Roschke and Schwierz [76]. Small modifications are made to fit the parameters into the models available in the Medici package. The equations for the used low field mobility are:

( )

( ) ( ) 76.0

10276.0

300

4.2300

0171

4095040

⋅

−

−

⊥+

−+=

totNT

T

cnµ (4.11)

( )

( ) ( ) 76.0

10276.0

300

4.2300

||0171

48114048

⋅

−

−

+

−+=

totNT

T

cnµ (4.12)

In Paper IX this model has been improved including the temperature dependency of the high-field mobility-parameters, vsat and β. The parameters are extracted from full band Monte Carlo simulation results shown in Fig. 4.6, together with the best fit to the high-field mobility according to Eq. 4.9. The extracted values, as a function of the temperature, are shown in Fig. 4.7 together with values from a standard expression for vsat (Eq. 3.13-14), and a linear model for β (Eq. 3.15-16).

( )( )60023.011077.2 7

T

ev csat

+

⋅=⊥ (4.13)


( )( )60030.011055.2 7

|| T

ev csat

+

⋅= (4.14)

(4.15) Tc310160.0 −

⊥ ⋅+=β

(4.16) Tc4

|| 10301.1 −⋅+=β

In 6H-SiC the anisotropy is large and almost constant. Parallel to the c-axis the mobility is 69 cm2/Vs at N=1⋅1017 cm-3 and is 330 cm2/Vs in the perpendicular direction. The corresponding saturation velocities are 0.6⋅107 and 2.0⋅107 cm/s. Any attempt to simulate device performance with isotropic transport models in 6H-SiC would not be accurate. A constant anisotropy model gives satisfactory results in most cases due to the very large anisotropy which does not change significantly with the electric field.

4.7.2 Relaxation Time The relaxation time has been extracted from Monte Carlo simulations in Paper I, and is shown in Fig. 4.3. From the figure it is clear that the energy relaxation cannot be regarded as a constant, which is the case in the models used. The relaxation time is also very anisotropic for high electric fields due to the band structure properties of 4H- and 6H-SiC. As shown in Fig. 4.2a, the energy bands are separated in the direction parallel to the c axis, which gives low mean energy in this direction, see Fig. 4.4. As the energy loss in scatterings is fairly constant a low energy particles relaxes more quickly even though the scattering probability is lower than for particles with high energy. Consequently, the relaxation time is not increased for high fields in the direction parallel to the c-axis due to the initially small mean carrier energy.

Compared to silicon the relaxation time is very short in SiC, of the order of 0.02-0.05 ps, while it is 0.2 ps in Si due to the presence of polar-optical scattering in SiC.

4.7.3 Impact Ionization Coefficients The impact ionization process needs to be characterized further for accurate modeling of the breakdown process in SiC. 4H-SiC is the polytype, where the anisotropic impact ionization has been studied most thoroughly. In SiC devices the influence of anisotropic impact ionization coefficients can be very strong. The band structure of SiC indicates that the impact ionization coefficients should be very anisotropic, which is observed in full band Monte Carlo simulations. In paper III the influence of anisotropic impact ionization is studied, and the strength of the effect is shown. More recent

4.8 DRIFT-DIFFUSION VERSUS HYDRODYNAMIC MODEL 39

state-of-the-art calculations including band-to-band tunneling, gives a reduced but still significant anisotropy in the impact ionization coefficients. For the direction parallel to the c-axis the values observed by Hatakeyama et. al. (eq. 4.17-18) are in reasonable agreement with those measurements made by Konstantinov et al. and the theoretical calculations (Fig. 3.3). One important discrepancy is however the different slope for the impact ionization coefficients.

⎟⎟⎠

⎞⎜⎜⎝

⎛ ⋅−⋅=

Ecn

78

||103.3exp1076.1α (4.17)

⎟⎟⎠

⎞⎜⎜⎝

⎛ ⋅−⋅=

Ecp

78

|108.1exp1041.3α (4.18)

In the direction perpendicular to the c-axis the only available measurement has been performed by Hatakeyama et. al. (eq. 4.19-20). Available theoretical calculations predict ionization rates of the same magnitude but with different slope and a higher rate for electrons. However, these calculations do not include band-to-band tunneling and the results are thus much less reliable than the results in the c-axis direction.

⎟⎟⎠

⎞⎜⎜⎝

⎛ ⋅−⋅=⊥ Ecn

77 1070.1exp1010.2α (4.19)

⎟⎟⎠

⎞⎜⎜⎝

⎛ ⋅−⋅=⊥ Ecp

77 1060.1exp1096.2α (4.20)

4.8 Drift-Diffusion versus Hydrodynamic model The drift-diffusion model is very time efficient for semiconductor device simulations. For silicon simulations the drift-diffusion model is insufficient for very small devices, where non-local effects become more pronounced. In these cases the hydrodynamic model is better for use involving predictions of device performance. The hydrodynamic model involves a significantly increased computational effort, and is mainly used for submicron devices. For device simulations in 4H-SiC devices, the drift-diffusion model has been shown to give accurate results even for submicron devices. This is related to the tenfold reduction in relaxation time compared to that of silicon, which means that that the maximum distance for non-local effects is much shorter than in silicon. The range for non-local effects, which can be approximated by the relaxation time multiplied by the saturation velocity, is only a few nanometers in SiC. This means that the drift-diffusion model is adequate for


−0.2

0

0.2 −0.3 −0.2 −0.1 0 0.1 0.2 0.3

340

350

360

370

380

[mm][mm]

Tem

pera

ture

[K]

Fig. 4.8. Thermal distribution on the surface layout for a device with 10 fingers each 200 µm long with 50 µm pitch, from heat transfer simulation.

SiC devices down to dimensions around 0.1 µm. In simulations of smaller devices, a hydrodynamic model with a non-constant relaxation time, or preferably the Monte-Carlo method, should be used for accurate results.

4.9 Thermal effects Semiconductor devices that are operating at high power levels are inevitable heated by the power dissipation. It is important that simulations can calculate this effect properly in order to predict the device performance. The heating effect is one of the most important limiting factors for RF power-devices, which for SiC devices have been studied both using analytical models [77] and 2D coupled electro-thermal simulations [78].

The lattice heating requires a sparse layout of the device to allow sufficient heat transfer from the dissipated power. Lattice heating for SiC MESFETs is studied in paper IX, where the electro thermal problem is solved consistently. The heat transfer has to be treated in three dimensions for correct thermal effects. Today it is not realistic to simulate RF power devices in three dimensions, due to the dense mesh required in the cross section of the device together with the multi-finger layout required for high power. Instead, the heat transfer problem is solved separately in 3D, and coupled by the thermal resistance with the electrical device simulation performed in 2D.

4.9 THERMAL EFFECTS 41

0 10 20 30 40 50 600

0.1

0.2

0.3

0.4

0.5

VD [V]

I D [A

/mm

]

Finger pitch, ∆F=100µm

∆F=20µm

DD simulation without thermal effectsCoupled DD and thermal simulationDD simulation using heating model

Fig. 4.9. Comparison between simulations without thermal effects, coupled electro/thermal simulations and the semi-coupled solution for a 2D case.

4.9.1 Heat transfer simulations The stationary heat transfer is described by

( ) qTk =∇∇− (4.21)

T is the temperature, k is the thermal conductivity and q is heat sources. In the case without internal source and constant thermal conductivity it is reduced to the Laplace equation:

(4.22) 02 =∇ TThe heat transfer simulation is performed in 3D using FEMLAB [79] using heat sources with a power density of PD

HT placed on the top corresponding to the device layout. The temperature of the rear surface is constant and other surfaces are isolated. The temperature distribution in the device fingers and substrate/cell periphery for such a simulation is shown in Fig. 4.8. The thermal resistance can then be expressed as the relation between the lattice heating and the dissipated power.

HTD

MaxTh P

TR = (4.23)


300

320

340

360

380

400

420

440

0 20 40

04

08

01

20

16

02

00

24

02

80

32

0

430

435

440

445

21 22 23 24 25 26 27 28 29 3020

Gate DrainSource

Fig. 4.10. Cross-section temperature distribution from a coupled electro-thermal simulation.

As the power density is given in W/mm the thermal resistance is consequently expressed in mmK/W. Using this equation for the thermal resistance, a scalar value is achieved, which implies that the temperature in different device fingers must be approximated with a constant.

The approximation is necessary unless the electrical simulation is divided into small segments and that both electrical and thermal simulations are repeated for a few steps until they converge. As the power is increased slightly in the parts where the temperature is less than TMax, it should consequently give increased heating in these parts. The introduced error is thus a slightly increased temperature in the outer parts of the layout than in reality and consequently a small underestimation of the total output power.

4.9.2 Electrical simulations A drift-diffusion model is used for the electrical simulation, where the electro/thermal coupling is achieved via the thermal resistance alone. The simulation temperature is given by:

DissThMax PRT = (4.24)

The power dissipation can either be calculated simply as P=U·I for the actual terminal voltage or through the use of any other voltages. This is very important, in for instance RF power devices, where the power dissipation can be calculated more correctly from the bias point and the signal

4.9 THERMAL EFFECTS 43

0 5 10 15 204.2

4.4

4.6

4.8

5

5.2

5.4

Equivialent thermal resistance, RTh

[K/W⋅mm]

Pow

er d

ensi

ty, P

Max

[W/m

m]

0 5 10 15 20300

350

400

450

500

550

600

←

→

Latti

ce te

mpe

ratu

re, T

[K]

Fig. 4.11. Output power density and lattice heating as function of the thermal resistance for SiC MESFET.

amplitude, rather than from the simulated terminal voltage. The simulation of the relation ID=f(VD)|VG=VGmax is required to estimate the output power (Fig. 2.4). For this IV curve, the lattice heating is calculated from the corresponding quiescent point by:

( )( )

4minmax DDDK

DQDQDissIIVVIVP ++

== (4.25)

The semi-coupled electro-thermal model is validated against a fully coupled model for a two-dimensional problem and the results are shown in Fig. 4.9. Very good agreement is shown in the figure between the two methods. The same graph also shows the importance of using the lattice heating calculation, as the current drops dramatically due to the increased temperature.

A cross section of the device for the fully coupled electro-thermal simulation is shown in Fig. 4.10. The finger pitch and bias point are selected to give the same situation as for the 3D heat-transfer simulation in Fig. 4.8. Comparing these two figures, two things should be noted: 1) The lattice heating is 146˚C in the 2D case, while taking 3D effects into consideration the heating is just 83˚C. 2) The temperature variation in the cross section of a device is 8˚C (5%), while in the 3D surface layout the temperature varies by 26˚C (31%). Three dimensional effects is thus much more important to consider than cross sectional variations in the temperature.


10 8 6 4 2 0 20

0.2

0.4

0.6

0.8

1

1.2

1.4g

m=49.9 mS/mm

CG

=419 fF/mmID

=302 mA/mmfT=18.9 GHz

Id=f(Vg)

5ohmRgen

50

RloadCg=f(Vg)Vgen2.0 GHz

0.1uH

80V

Fig. 4.12. Linearity estimation. A) MESFET performance in the load-line B) Power amplifier circuit.

In Fig. 4.11 the output power and the lattice heating are shown as a function of the thermal resistance. With the large temperature variations at the surface according to Fig. 4.8, the accuracy of constant temperature approximation must be investigated further. The maximum and minimum temperature in Fig. 4.8, and when combined with Fig. 4.11, correspond to equivalent thermal resistances of 7 and 5 mmK/W. In these cases the output power is 4.95 and 5.1 W/mm, i.e. the introduced error in output power is less than 3%. The power dissipation is likewise scaled and the heating achieved in Fig. 4.8 is thus accurate.

By super-positioning of small device segments working at different temperatures, parameters that are more dependent on the temperature can also be studied.

4.10 Linearity Linearity is very important for many applications in wireless communication systems to avoid mixing between neighboring channels. The main sources of the nonlinearities in MESFETs are found in the gate-capacitance and transconductance. The depletion width is proportional to the square root of the applied voltage. Both the capacitance and transconductance are directly related to the depletion width, which makes them nonlinear. The non-linearity can be improved by channel engineering. A thin and highly doped channel is better for the linearity, than a thick and low doped channel [80]. Ideally, the channel doping profile should be delta shaped, but this is of course not possible to implement. A major problem is that a higher doping

4.10 LINEARITY 45

0 0.5 1 1.5 2-50

0

50

100

150

V

t [ns]

GenGateLoad

0 2 4 6 8 10-10

0

10

20

30

40

50

P [d

Bm

]

f [GHz]

GenGateLoad

10 15 20 25 30 35 4010

20

30

40

50

PO

ut [d

Bm

]

PIn [dBm]

Carrier1st Harmonic2nd Harmonic

32 33 34 35 36 3744

45

46

47

48

49

50

PO

ut [d

Bm

]

PIn [dBm]

Carrier1st Harmonic2nd Harmonic

Fig. 4.13. Linearity estimation. A) Large signal non-linear transient analysis. B) Harmonic Distribution. C) POut=f(PIn). D) Enlargement of POut=f(PIn) around the 1 dB compression point.

level reduces the breakdown voltage, as it becomes more difficult to deplete the gate-drain region.

Assuming a purely resistive load, the transistor operation follows the load line in Fig. 2.4 fairly well. By extraction of the nonlinear device parameters in the load line from device simulations (Fig. 4.12a), the system performance can be estimated by large-signal transient analysis. For each time step the gate-voltage determines the correct values for the gate capacitance and drain current. The results from the simulated circuit (Fig. 4.12b) are shown in Fig. 4.13. In the output of the transistor the signal is clearly compressed. Based on FFT analysis, the harmonic distribution (Fig. 4.13b) and the output power as a function of the input power are shown in Fig. 4.13c,d. For this device the 1 dB compression point occurs at 47 dBm (50 W) output power, where the gain is 11 dB.


0 100 200 300 400 5000

0.5

1

1.5

2

2.5

3

3.5x 10

10

Number of simulations

f T [H

z]

Nelder MeadSimulated Annealing

0 100 200 300 400 5000

0.5

1

1.5

2

2.5

3x 10

9

Number of simulations

MS

G x

f T x

PM

ax [d

B⋅H

z⋅W

/mm

]

Nelder MeadSimulated Annealing

Fig. 4.14. Comparison between Simplex and Simulated annealing in an optimization of 4H-SiC RF power MESFET.

The calculations are still preliminary, and have to be validated against measurements before they can be used quantitatively in the design stage of new devices.

4.11 Semiconductor device optimization A large part of this work has focused on device optimization in the design of semiconductor devices. In paper VII the concept of device optimization is introduced, where the optimization is implemented to solve a specific task. The concept has been further developed as a general tool, where the device and the optimization criteria and algorithms can easily be changed independently of each other. An important feature is the possibility of activation/ deactivation of the variables that are optimized, from a run-to-run basis. This can speed up the total optimization by initially optimizing only the most critical parameters before optimizing all parameters.

4.11.1 Optimization Goal One difficult aspect of the device optimization is to determine what is really optimal from the application point of view. For RF power devices both high frequency properties and the power handling capabilities have to be considered. In this work the output power is estimated according to Eq. 2.5. For high frequencies both fT and the RF gain (MSG) at the carrier frequency are important. In the present study combinations of these parameters (fT, fT·PMax, MSG·PMax, fT·PMax·MSG) are used as the optimization goals. Using fT alone results in devices with very low breakdown voltage, and consequently is not suitable for power devices.

4.11 SEMICONDUCTOR DEVICE OPTIMIZATION 47

Second-order effects such as linearity and device heating can also be of great importance for the final application. Incorporating such details into the optimization during the device design offers a clear competitive advantage, and makes it possible to increase the market share for the manufactured devices. The importance of estimating these effects as rapidly as possible is thus critical and the methods described in the previous chapter for self heating and linearity are thus very interesting.

4.11.2 Optimization Algorithm Both a local (Simplex) [81] and global (Simulated Annealing) [82] optimization algorithm are included in the optimization tool. In paper VIII both of them are shown to be important for the tool functionality. Simplex converges more rapidly than Simulated Annealing but as it is a local method, it can be caught in local maxima. Optimal performance in RF power devices is obtained by a trade-off between frequency and power. In such cases the optimization criteria often contain numerous local extreme points, and local optimization methods are thus insufficient. Simulated annealing is an efficient global optimization algorithm, which is required for such tasks. In Fig. 4.14 a comparison between the two optimization algorithms is shown. Both algorithms give the same performance when optimizing fT alone, but in the more complex case Simplex does not converge to the global maximum.

5 Silicon Carbide Field-Effect Transistors In recent years numerous SiC devices have been manufactured [83]-[124]. The device with highest fT so far reported is a lateral 4H-SiC MESFET with fT=22 GHz [83]. For a vertical MESFET the best achieved performance is fT=7 GHz [100]. Early SiC MOSFET devices had poor performances due to difficulties with the inversion channel mobility at the oxide. Still, RF performance as high as fT=7 GHz is achieved, with just 30 cm2/Vs surface mobility [119]. However, the surface mobility has been increased and SiC MOSFETs will probably be commercially available within the next few years. The surface mobility is not a problem in MESFET devices, since the channel conductivity relies on bulk transport properties.

5.1 Lateral MESFETs Lateral MESFETs (commonly just called MESFETs) have been widely explored by several different groups [83]-[97]. The MESFET is the SiC device type that has offered the best RF-performance of those manufactured until now [83]. State-of-the-art devices are manufactured on semi-insulating substrates, which give low parasitic gate capacitance. A p- buffer layer is introduced between the channel and the substrate, to give better control of the threshold voltage and avoiding carriers to penetrate into the substrate. The lateral MESFET is commonly produced in a straightforward manner based on the etching of an epitaxial structure.

In paper VII an optimization of vertical MESFETs has been performed, resulting in a device which for agrees favorably with the manufactured devices. Assuming a lithographic resolution of 0.2 µm, the best performance achievable is fT=25 GHz. There are few parasites in SiC MESFETs, but a reduction of the gate-source spacing could increase the performance slightly. The state-of-the-art device is manufactured with 0.45 µm gate length and 0.2 µm gate-source spacing. In lateral transport, 4H-SiC is about 30% better than 6H-SiC. A 2H-SiC device could be slightly better than a 4H-SiC device. However, the difference is not sufficiently large to encourage the development of 2H-SiC wafers. The transport properties of 3C-SiC suggest device RF performances similar to those in 4H-SiC but with a reduced

50 CHAPTER 5. Silicon Carbide Field-Effect Transistors

breakdown voltage. The advantage of 3C-SiC is the possibility to grow on silicon substrates to integrate SiC power devices with Si logic circuits. However, the thermal conductivity is thus reduced on the Si substrate, degrading the performance for power devices, especially as the temperature must be kept at a level allowed by the silicon circuits.

5.1.1 Buffer Layer Large transconductance (gm) is required for high-frequency operation. For large gm in a MESFET the channel has to be restricted to just a thin layer, otherwise the channel cannot be modulated efficiently by a small gate signal. The channel restriction can be achieved by introducing a p-n junction beneath it. For n-channel MESFETs a p-type substrate can be used. The doping level of the substrate is also of importance. In the channel, electrons are pushed away from the Schottky gate down into the substrate. With high-doped bulk material, the depletion region in the channel-bulk interface is smaller, giving a higher electric field and more efficient shielding of the channel. In a lightly doped substrate carriers penetrate more deeply than when high doping is used. As a result the threshold voltage increases at higher drain bias due to less gate control of the channel. A highly doped p-substrate is thus recommended for a well-defined threshold voltage. One drawback of a p-type substrate is the parasitic pad capacitance between the pad and the substrate. The increased parasites, particularly the gate capacitance, reduce the high-frequency performance of the device considerably. Much better performance can be achieved if the channel is placed on top of an insulator, where the pad capacitance is minimal. When an insulator is used, the channel can also be fully depleted with no substrate conduction. In recent years SiC semi-insulating substrates have been successfully manufactured [125]-[126], and are now commercially available. The semi-insulating material, which is created by the introduction of deep-level impurities such as vanadium, reduces the minority carrier lifetime to the nano-second region. A problem that occurs with such a substrate is the presence of traps, with both short and long lifetimes. Trapping in the semi-insulating substrate, results in a drift in the drain current with a time-scale of minutes. The explanation is that as the traps are charged they deplete the channel from underneath [85]. The traps recombine stochastically, increasing the 1/f noise [87] during pinch-off significantly due to the substrate conductivity.

The effects from the substrate on the channel are reduced introducing a p-type buffer region between the two layers. The carriers in the buffer layer reduce the high-frequency performance, and consequently a lightly doped layer is preferable, which must be thick to prevent penetration into the semi-insulating substrate. With this configuration short channel effects dominate

5.2 VERTICAL MESFETS 51

the device performance and a high doped layer is optimal to enhance the pinch-off characteristics. A high doped p-layer will also reduce the breakdown voltage as most of the potential difference between source and drain will be localized just beneath the drain contact as the p-buffer layer form a low resistive path. The breakdown voltage will thus be determined by the channel thickness and doping.

An innovative device design presented by Konstantinov et.al [99], the lateral epitaxi (LE) MESFET, utilizes a highly doped p-buffer layer only under the gate contact. The advantage is that much higher p-buffer doping can be used which suppresses the short channel effects well and still enables a high breakdown voltage as the gate and drain are separated by a low doped p-layer.

5.2 Vertical MESFETs To increase the transconductance it is desirable to modulate the channel from both sides. In a lateral structure it is problematic to design a device which has a two-sided channel depletion.

Orienting the channel vertically, a two-sided depleted channel can be obtained using a rather simple process. The vertical MESFET (Fig. 2.1b) is often called a static induction transistor (SIT) or a permeable base transistor (PBT). These devices have been discussed for a long time [127], but have never been a commercial success. Their structure is identical but, different parts of the IV-characteristics are used. Over the last decade many vertical MESFETs in SiC have been manufactured [100]-[106].

The vertical channel orientation of a MESFET has some advantages compared with that of the lateral. The length of the channel in a vertical MESFET is not limited by the lithographic resolution, making it possible to create a very short channel with a moderate resolution. In the vertical MESFET the channel is surrounded by gate contacts on both sides of the channel. The two-sided depletion approximately doubles the trans-conductance compared to that of a single-sided gate. Even though the channel length is independent of the lithographic resolution, it is of importance. The gate capacitance, which is important for high-frequency operation, increases with the width of the gate-trench. For a large gate-spacing the doping concentration has to be kept low to make it possible to switch off the device. A low channel doping also reduces the maximal current in the device and therefore also the power density. The extremely short gate makes short channel effects more dominant than in vertical devices.

For vertical MESFETs 4H-SiC is far better than 6H-SiC devices. There is approximately a fivefold difference in performance, due to very low mobility


n+

n+lbulk

Source

Drain

lbulkeff

Gate pad

n+

Source

Drain

Gate pad

Semi-insulating Bulk

ND

ND

tox

n+

B)A)

Gate Gate

Gate Gatelz

lz

Fig. 5.1. Two strategies to reduce the parasitics in vertical MESFETs. A) Etched and metallized trenches from the rear side decreases the drain-resistance. B) The vertical MESFET realized on top of a semi-insulating substrate.

in the direction parallel to the c-axis in 6H-SiC. In 2H-SiC the mobility is higher in this direction and 2H-SiC devices are expected to be about 20% better than similar 4H-SiC devices. One drawback of the vertical MESFET is the worse planarity, which is assumed to reduce the yield in device manufacturing.

5.2.1 Parasitics The main problems concerning the state-of-the-art devices are, however, still related to the parasitics in the drain resistance and gate capacitance. The gate pad is usually placed in the gate metal-layer, where there is a large parasitic capacitance between the pad and the highly dopey substrate. By increasing the gate-drain spacing, which reduces the intrinsic high frequency performance of a vertical MESFET, the capacitance is reduced. This means that the design of an optimal vertical MESFET is not straightforward, since optimal device performance is achieved by a trade-off with the gate-drain spacing. The drain resistance also degrades the device performance and increases with a reduced channel and gate width. More trade-off situations must be considered in the design of a vertical MESFET than for a lateral MESFET and device design is thus more difficult.

In paper VII the geometry of vertical MESFETs including parasitics has been optimized by iterative 2-dimensional drift-diffusion simulation. The best performance achieved assuming 0.2 µm lithographic resolution is fT=7.5

5.3 MOSFETS 53

GHz [100] which is close to the value obtained experimentally. Without reducing the parasitics the performance of vertical MESFETs can thus not be increased by scaling.

If the parasitics could be reduced, vertical MESFETs would be an interesting candidate for high-power, high-temperature and high-speed electronics. Two different ways of obtaining this are exploited by simulations in paper VII and shown in Fig. 5.1. In the first device trenches are etched and metallized from the rear side of the wafer, and the gate pad are placed on top of a field-oxide layer. In this way both the drain resistance and the gate capacitance are reduced significantly. The unity current gain frequency (fT) can in this way be increased from 7.5 to 34 GHz. It may, however, be difficult to manufacture this device, since it is very difficult to etch deep trenches in SiC. As an alternative the vertical MESFET could be manufactured on a semi-insulating substrate with all three contacts on the top side of the wafer. This device suffers from a distributed drain resistance and fringe effects, which may reduce the performance for power devices. The high-frequency performance is however good and fT as high as 43 GHz has been achieved in simulations. The drawback, from a processing point of view, is that the planarity is worse and the metallization may be difficult to perform.

5.3 MOSFETs The advantages of SiC power MOSFETs over the corresponding Si Devices have been known for a long time [107]. They are: high current density, low on-state resistance, high breakdown-voltage, and a high allowable operational temperature. Many studies have been carried out in the SiC MOSFET area over the past years [107]-[124]. Until recently the performance of manufactured MOSFETs had been limited by the oxide quality achievable. The oxide problems are: low surface mobility, low breakdown voltage, and gate oxide leakage. There is a quality difference depending on SiC polytypes, crystalline face, and processing used.

In a MOSFET device an electric field is applied perpendicular to the channel, which is parallel to the direction of the gate oxide. The electric field is necessary to create the population inversion, but the mobility is reduced due to the large number of surface scatterings and trapping in defect levels. This is known as the surface mobility and it decreases with increased electric field perpendicular to the oxide. However, the channel carrier density in the channel also increases with the same electric field due to enhanced population inversion. For high performance MOSFET devices, it is thus necessary to obtain a high surface mobility, which is required for high transconductance.


Random

α =αi r

Prob=1-C

Prob=Cα =

Fig. 5.2. Simple surface transport model. The carrier is reflected diffusly with the probability C and otherwise specular.

In power MOSFETs for low-frequency applications, the blocking voltage and the on-resistance are two of the most important parameters. The blocking voltage gives the maximum allowable voltage for device operation; and here SiC has an advantage over Si. A low on-state resistance allows a large current with small circuit losses and less power dissipation in the device. The on-state resistance is inversely proportional to the mobility, which must be sufficiently high for practical applications.

The surface mobility is thus a critical parameter for both high-power, high frequency, and of course microwave power MOSFETs.

5.3.1 Polytypes In SiC the experimentally obtained surface mobility is low, and is different for each polytype [107][109]. The mobility values extracted from identical devices manufactured in 4H, 6H and 15R-SiC are 5, 37 and 50 cm2/Vs respectively. In later experiments the surface mobility has been improved significantly. In 4H-SiC the surface mobility has now reached 150 cm2/Vs for 4H-SiC [6] and 95 cm2/Vs for 6H-SiC [110]. The origin of the low surface mobility is related to the number of traps [111][112] in the SiC-SiO2 interface. The SiO2-SiC interface-states are located around 2.9 eV above the valence band in all three polytypes [109]. For 4H-SiC these levels are located within the band-gap, and accordingly contribute to many of the interface traps. Both 6H-SiC and 15R-SiC, have band-gaps close to 3 eV and the interface state distributions are mainly situated within the conduction band.

In paper IV, Monte Carlo simulations are performed on a MOSFET structure, and surface mobilities are extracted. The surface mobility model in Fig. 5.2 has been used for silicon [113] with good results. It is based on a combination of diffuse and specular scattering. For diffuse scattering the direction of the carrier is selected randomly, while for specular scattering the

5.3 MOSFETS 55

reflected angle is equal to the angle of incidence. The type of scattering is selected randomly using a fixed probability. With this model it has been shown that the surface mobility is also related to the anisotropy of the bulk mobility. The surface mobility for a 6H-SiC device aligned perpendicularly to the c-axis is not as sensitive to increased fraction of diffuse scattering. This is related to the low bulk mobility in the c-axis direction for 6H-SiC, which reduces the number of surface scattering events, and increases the mean time between scatterings (relaxation time), (τ) in the region where the surface scattering dominates. The mobility, which is directly proportional to τ is thus also increased.

*m

qτµ = (5.1)

The effective mass, (m*) is inversely proportional to the curvature of the band structure in k-space.

5.3.2 SiC face The surface mobility depends not only on which face of the SiC lattice wafer is being used, but also on the anisotropy in the current direction on the surface [114]. The ( 0211 ) face has been giving higher surface mobility than the conventional (0001) Si-face, especially for 4H-SiC. The surface mobility in this case is increased from 5 (45) to 95 (115) cm2/Vs for 4H (6H)-SiC. On the ( 0211 ) face, the channel can be oriented both parallel to the c-axis and perpendicular to it. In this case the anisotropy is related to the bulk anisotropy of the bulk material, and in 4H (6H)-SiC the mobility in the c-axis direction is 1.17 (0.32) times the value in the direction perpendicular to the c-axis. The mobility is higher in the ⟨ 0011 ⟩ direction of the ( 0211 ) face than in the same direction on the ( )0001 face. Assuming that the surface mobility was given only by the anisotropy in the bulk material, it follows that the surface mobility in 6H-SiC on the (0001) face ought to be higher than on the ( 0211 ) face, since the mobility perpendicular to the channel is lower on the (0001) face.

By post-oxidation of the 4H-SiC ( 0211 ) face, the surface mobility has reached 110 cm2/Vs [115]. Recent results on the conventional (0001) Si-face have reported a surface mobility of 150 cm2/Vs [6] by gate oxidation in N2O surroundings.

5.3.3 Surface orientation The surface mobility is also reported to be anisotropic for different channel orientations on the (0001) Si face [116] in 6H-SiC. In the direction parallel


1

direction of incoming carrier

surfacenormal 1

l1

l2

surfacenormal 2 2

Fig. 5.3. Surface transport model taking the surface steps into consideration.

to the surface steps, the measured surface mobility is 50 cm2/Vs, while it is just 23 cm2/Vs in the perpendicular direction. Interestingly, both these orientations are perpendicular to the c-axis direction and the corresponding bulk mobility is nearly isotropic. Many substrates are manufactured slightly off-axis, 8° for 4H-SiC, and 3.5° for 6H-SiC. Because of the finite size of the crystal unit cell the resulting surfaces are not perfectly plane. The anisotropic surface mobility cannot be explained by the just the off-axis orientation combined with the anisotropic bulk mobility, as the angles are too small. Instead this anisotropic surface mobility is thus directly related to the surface properties. A 3.5° off-axis orientation gives a surface step at each 16th atom, and 8° every 7th. The surface steps are terminated by C-atom dangling bonds that increase the defect density. Apart from the dangling bonds, the surface roughness is also important for the surface mobility since carriers moving parallel to the steps experience a smoother surface than those moving perpendicular to the steps.

In paper V, a Monte Carlo model (Fig. 5.3) is presented, which includes the surface roughness effects of the surface steps. In this model the surface scatterings are randomly divided into two parts with different probabilities, representing scattering against the two perpendicular surfaces in the step. Scatterings on the two surfaces are both treated as constants but are dealt with by using different fractions of specular and diffuse scattering. The simulations show that the mobility in the direction perpendicular to the surface steps is very sensitive to the crystal off-axis angle. In the direction parallel to the surface steps, the dependency is more moderate. For 6H-SiC the surface mobility parallel to the surface steps is 50 cm2/Vs, and it is 23

5.3 MOSFETS 57

Gm GmGp GpSource

Gp

Drain

p+p+

p+ p+p+

n+

n+

n-

n-

n+

n+

n-

p

n

Gate

Source

Drain

Fig. 5.4. Additional MOS structures manufactured in SiC a) ACCUFET [123] b) SIAFET [124].

cm2/Vs in the perpendicular direction to the steps. The simulated anisotropy for the surface mobility is 2.5, which is in reasonable agreement with the measured value of 2.2. However, the simulated mobility level is approximately five times higher than the reported value obtained from measurements, and this discrepancy is explained by interface states, which are not considered in the Monte Carlo simulations. The carriers are trapped in the interface states for short periods of times, causing a considerable reduction in their effective mobility.

Recently, the oxide quality has been considerably improved with surface mobility exceeding 100 cm2/Vs, and SiC MOSFETs are rapidly approaching commercial viability.

Another way to improve the channel mobility in SiC MOSFETs, is to keep the electrons away from the SiC-SiO2 interface. This can be achieved by using a buried channel [117], which has resulted in a channel mobility reported to be as high as 140 cm2/Vs. In MOSFETs manufactured with a thick gate-oxide (9000 Å), the inversion layer mobility is 160 cm2/Vs for 4H-SiC and 110 cm2/Vs for 6H-SiC [118]. On the other hand, both these solutions give less control over the channel, and consequently give low transconductance and poor high-frequency performance.

4H-SiC RF Power MOSFETs with fT as high as 7 GHz have been manufactured [119]. The effective mobility of these devices is only 30 cm2/Vs, which clearly shows the potential for SiC MOSFETs for RF Power applications.


SiC MOSFETs are very promising for high-power devices, provided the problem of channel mobility can be solved. Different groups have manufactured SiC power MOSFETs in recent years [120]-[124]. SiC MOSFETs devices can be manufactured in numerous ways, both with lateral and vertical channel orientation, which in experiments have shown blocking voltages above 4 kV.

In addition to the standard structures shown in Fig. 2.2, a few other interesting structures have been manufactured (Fig. 5.4). In an n-channel accumulation mode MOSFET (ACCUFET), the channel is a thin n-doped layer, with a p-type region located a short distance beneath it (Fig. 5.4a). At zero gate-bias the n-channel is fully depleted by the built in fields from the p-n junction below, and from the gate electrode. Applying a positive bias to the gate contact creates an accumulated channel just beneath the oxide interface.

The SIAFET [124] (Fig. 5.4b) is a four-terminal device with two gate electrodes (GM and GP). Under positive GM-bias it works in a manner similar to that of an ACCUFET. By applying a positive GP-bias, two of the effects of on-resistance can be reduced: 1) The depletion region near the buried p+ gate is reduced, which widens the channel. 2) Injection of minority carrier from the buried gate. The SIAFET can work as a three-terminal device connecting diodes between the two gates.

5.4 Applications for SiC Field Effect Transistors One driving application for RF power devices is in the output stage in base stations for the third generation mobile telephone systems. SiC MESFET devices offer a better performance when compared to silicon devices for the same application, with respect to the power level, as well as gain and impedance matching. This enables construction of RF output stages that can replace silicon technology using fewer external components and a much simpler cooling system.

The main drawback concerning the devices used at present relates to the linearity required by the 3rd generation mobile systems. Today, advanced signal processing is used to compensate for the nonlinearity in the RF power amplifiers. This has created an enormous market pull to deliver new devices, which simultaneously have the required power, frequency, and linearity. The technology that best fulfills these requirements will be adopted by system suppliers, which in turn will achieve a very large market share. Silicon technology (LDMOSFETs) is stretched close to its theoretical limitations, and it is unlikely that silicon can be improved to that extent. Silicon Carbide has superior material properties compared to silicon, and has more room for a trade-off until the desired linearity is achieved.

5.4 APPLICATIONS FOR SIC FIELD EFFECT TRANSISTORS 59

Another application category for high-speed power devices are switched AC-DC and DC-DC converters. The high-frequency performance is here not as critical as for telecommunication systems, but the breakdown voltage and the on-state resistance should be improved. The market for these products is enormous, and it is today totally dominated by silicon MOSFETs. With the switching speed used today it is difficult for SiC devices to compete with silicon technology. The desire is to increase the switching frequency beyond 1 MHz, enabling very small designs, where present day bulky inductors and capacitors can be replaced by much smaller counterparts. For these products SiC becomes a very interesting material with its high switching speed and breakdown voltage. To increase the switching speed the magnetic material must also be developed. Prototypes presently exist for materials up to 5 MHz, but the goal is to manufacture magnetic material operating up to 50 MHz. The important parameters for switched power supplies is the on-state resistance (RDSon), breakdown voltage, and switching times.

6 Summary of Papers In this work the performance of field effect transistors in silicon carbide is studied using device simulations. Nine papers are included in this thesis, which cover different aspects of this topic. They cover the range from extraction of transport parameters to design and simulation of SiC devices. The papers have advanced the research in device design methods using optimization methods and efficient simulation of device heating. SiC RF power devices are used as a test bench for device optimization but the tool developed can be used for any other material or application Additionally this work has increased the understanding of the simulation aspects of SiC devices.

The first paper in this work is dedicated to the evaluation of existing transport models for SiC device simulation.

In the papers I-VI, device simulations are used as a tool to investigate different aspects of the carrier transport in SiC. The Monte Carlo model is used in papers I, II, IV, V and VI as a tool to study device performance both from a microscopic and macroscopic perspective.

In paper III the drift-diffusion model is used to study the breakdown behavior in 4H-SiC using an anisotropic model of the impact ionization parameters. This gives an interesting explanation of the background to the differences between the experiments performed up to that time. Recent measurements indicate that the impact ionization coefficients are in fact anisotropic but not as much as indicated in this paper. Better theoretical models also give less anisotropy than that initially reported.

Papers VII-VIII, focus on device design for SiC devices. The method used is iterative drift-diffusion simulation for optimization of the design parameters to provide maximal device performance. The method is shown to be very efficient in the design of new semiconductor devices with regards to optimizing the device layout for a specific application. This is a quick method available for the validation of the suitability of new device concepts for a given application, and an excellent aid in the design stage of the final device layout.

62 CHAPTER 6. Summary of Papers

In the final paper, a method for simulation of self heating in RF power devices is presented based on 2D electrical simulations together with 3D thermal simulations. This method is more accurate and much faster than previous methods such as 2D coupled electro-thermal solutions. Additionally the available set of transport parameters have been upgraded with temperature dependency of the high-field transport parameters.

Paper I. The Effect of Different Transport Models in Simulation of High Frequency 4H-SiC and 6H-SiC Vertical MESFETs

Author List: K. Bertilsson, H.-E. Nilsson, M.Hjelm, C. S. Petersson, P. Käckell, C. Persson.

Reference: Solid State Electronics 45 (2001), pp 645-653.

Authors Contribution: Major part of the work.

In this paper the drift-diffusion, hydrodynamic and Monte-Carlo transport models have been evaluated for simulations of SiC devices in 4H and 6H-SiC. It is shown that the drift-diffusion model is as good as the hydrodynamic model (with constant relaxation time) for SiC device simulation. This is due to the very short relaxation time in SiC when compared with silicon. The drift-diffusion model can be used with accurate results for shorter channel-lengths in SiC devices than in silicon. The relaxation time as a function of the electric field is extracted from full-band Monte Carlo simulations and it is shown that it is both strongly field-dependent and anisotropic.

Paper II. Monte Carlo simulation of vertical MESFETs in 2H, 4H and 6H-SiC

Author List: K. Bertilsson, E. Dubaric, H.-E. Nilsson, M. Hjelm, C. S. Petersson

Reference: Diamond and Related Materials 10 (2001), pp 1281-1286.

Authors Contribution: Major part of the work

A comparison of simulated device performance is investigated for vertical MESFETs in 2H-, 4H-, and 6H-SiC. In the paper an ideal device is assumed, and it is shown that ideal vertical MESFETs have much better performance than lateral MESFETs. The best published results for vertical MESFETs report fT=7 GHz. This paper points out that the performance of the manufactured SiC vertical MESFETs is limited by parasitics.


Paper III. Simulation of Anisotropic Breakdown in 4H-SiC Diodes Author List: K. Bertilsson, H.-E. Nilsson, C. S. Petersson

Reference: Proceeding of 7th IEEE Workshop on Computers in Power Electronics -2000, Virginia Tech, Blacksburg, Virginia, USA, 16-18 July 2000, pp 118-120.


An anisotropic impact ionization model is used in simulations of breakdown characteristics in SiC diodes. The impact ionization coefficients are extracted from Monte Carlo simulations [39], and then used in the drift-diffusion simulations. In these drift-diffusion simulations the same structures as in the experimental characterization of the impact ionization coefficients are used. It is shown that the discrepancies between the two measurements can be explained by anisotropic impact ionization coefficients.

Paper IV. Simulations of Submicron MOSFETs in 2H, 4H and 6H-SiC Author List: E. Dubaric, K. Bertilsson, H-E. Nilsson

Reference: Physica Scripta, Vol. T101, 2002, pp. 14-17

Authors Contribution: Performing Monte Carlo simulations of surface transport and for the MOSFET devices and analysing data.

It is shown that short-channel SiC MOSFETs can reach excellent high frequency performance, assuming that the surface mobility can be improved to levels close to those common in silicon. The paper also gives a possible explanation of the better surface mobility reported previously for 6H-SiC when compared to 4H-SiC. Assuming that the two materials have the same low oxide quality, the high anisotropy of the 6H-SiC bulk mobility reduces the number of surface scatterings significantly, which contributes to less surface mobility degradation.


Paper V. Full Band Monte Carlo Study of Bulk and Surface Transport Properties in 4H and 6H-SiC

Author List: M. Hjelm, K. Bertilsson, H-E. Nilsson

Reference: Applied Surface Science No. 184, 2001, pp. 194-198.

Authors Contribution: Participation in discussions of the model and the results.

Bulk and surface transport parameters are studied using the full band Monte Carlo simulator. The bulk transport is studied with applied electric fields in a number of angles from parallel to the c axis to perpendicular to it. Interestingly, in highly anisotropic materials such as 6H-SiC, the carrier movement direction differs from the direction of the electric field. This effect is strongest for electric fields applied at about 10-30° from the c-axis direction. In a short range of angles the current vector differs by more than 45° from the electric field vector. The surface mobility is studied using a new model taking the effect of surface steps into consideration. A similar anisotropy to that experimentally observed in SiC MOSFETs [116] is obtained with the model.

Paper VI. Numerical Simulation of Field Effect Transistors in 4H and 6H-SiC

Author List: H-E. Nilsson, K. Bertilsson, E. Dubaric, M. Hjelm

Reference: Journal of WIDE BANDGAP MATERIALS, Vol. 9,No. 4, 2002 pp. 293-305

Authors Contribution: Running the simulation of the MESFET devices and participated in discussions and evaluation of results

An overview of SiC device modeling that has been performed at Mid-Sweden University is presented. The results are based on Monte-Carlo, drift-diffusion and hydrodynamic models. The paper includes bulk simulations as well as short channel MOSFETs and vertical and lateral MESFETs.


Paper VII. Optimization of 2H, 4H and 6H-SiC high-speed vertical MESFETs

Author List: K. Bertilsson, H-E. Nilsson

Reference: Diamond and Related Materials No. 11, 2002, pp. 1254-1257.


The optimization concept is used in the design of SiC vertical MESFETs including major parasitics. Using a traditional layout, the optimized value for fT reaches 7.5 GHz. It is shown that the performance cannot be increased as much as for lateral MESFETs using increased lithographic resolution. This is due to the large parasitic gate-pad capacitance and drain resistance, which are the limiting factors for fT. Two strategies are proposed to reduce the parasitics in vertical SiC MESFETs. Based on these strategies two optimized structures are also presented, which show increasing fT with improved lithographic resolution as expected. With 0.2 µm lithographic resolution fT reaching 43 GHz is obtained.

Paper VIII. The power of using automatic device optimization, based on iterative device simulations, in design of high-performance devices

Author List: K. Bertilsson, H-E. Nilsson.

Reference: Solid State Electronics Vol 48 (10-11), 2004, pp 1721-1725.

Authors Contribution: Most of the work.

The optimization concept has been extended to a toolbox, where the devices or optimization parameters and goal can easily be changed. This enables efficient validation of different device concepts for a specific application. It is shown that global optimization algorithms are preferable, especially in cases where one or more trade-offs have to be considered in the optimization process. Different optimization goals suitable for RF power devices are suggested and it is important that both RF characteristics (fT, fMax, MSG) and power performance (PMax) are considered simultaneously. The layout achieved for the different goals is presented and analyzed.


Paper IX. Calculation of lattice heating in SiC RF power devices Author List: K. Bertilsson, C. Harris, H-E. Nilsson

Reference: Solid State Electronics Vol 48 (12), 2004, pp. 2103-2107.


A new and more computationally efficient method for simulation of RF power devices, including self heating, is proposed. The method is based on 2D device simulation combined with 3D heat-transfer simulation. From the heat transfer simulation the thermal resistivity is calculated for the device chip. In the device simulation the device temperature is coupled by the temperature increment given by the power dissipation over the thermal resistance of the device. The method is validated against a fully coupled electro/thermal solution in two dimensions, giving in this case good correspondence. It is not realistic at present to perform fully coupled solutions in three dimensions for RF power devices. In the paper it is shown that the thermal effects have to be treated in 3 dimensions to obtain a realistic picture of their influence on the device performance. The proposed method is thus better suited for the task than fully coupled solutions, giving both better accuracy and computational efficiency.

7 Summary and Conclusions Silicon Carbide devices have a promising future for high-temperature and high-power electronic devices.

The transport models and parameters still need to be characterized further to increase the accuracy of predictions made by SiC device simulations. Much debate has been focused on the impact ionization coefficients for different SiC polytypes. Most recent research has been conducted using 4H-SiC and the understanding increases constantly and several measurements and calculations also point in this direction.

For commercial products the main obstacles are the expense of mono crystalline SiC and the defects associated with the SiC crystal. The quality is constantly increasing, and it can be assumed that the price will be reduced as the production volumes increase. For microwave power-devices the encapsulation is also an important part of the cost. As it is the same as for silicon devices the higher breakdown voltage and better high temperature performance simplifies much of the device surrounding, such as load matching and cooling system. In silicon technology large arrays of MOS capacitors are used for matching purposes and in SiC technology these would not be necessary. SiC devices are thus a competitive alternative to their Si counterparts.

This work has opened new and improved methods for design and simulation of semiconductor devices. The available set of transport parameters have been extracted from different measurements and extended to incorporate temperature dependencies of high field transport parameters for 4H-SiC. It has been shown that the drift-diffusion model gives reasonable accuracy down to at least 0.2 µm due to the short relaxation time. Monte-Carlo simulations of 2H-SiC show that the performance could be slightly improved by using 2H-SiC in the direction parallel to the c-axis compared to the use of 4H-SiC. The advantage is however not significant enough to encourage large investments in the crystal growth.

The impact ionization process is still not fully understood, however, several different sources are pointing in similar directions reporting highly anisotropic impact ionization coefficients. In the direction perpendicular to

68 CHAPTER 7. Summary and Conclusions

the c-axis only one measurement is available and there are no reliable calculations so the parameters might need to be tuned in the future as better experiments are performed.

Self heating is important in RF power devices and must be included in the design stage. Fully coupled electrical/thermal simulations are inadequate in two dimensions and unrealistic in 3D. An efficient way for self heating calculation is developed using a combination of 3D thermal simulations and 2D electrical simulations. The method gives better predictions regarding the heating, and requires less simulation time compared to that involved in coupled 2D simulations and the method can thus be incorporated into the optimization phase of the device design.

To perform this work three different tools have been developed: 1) A time domain drift-diffusion device simulator. 2) A circuit simulator handling nonlinear elements. 3) An optimization tool for efficient device design.

To increase the computational efficiency for device simulations using the Monte-Carlo method, passive parts of the devices could be modeled using much simpler drift-diffusion equations. As the Monte-Carlo method is, by its nature, a time-domain solution this is also sufficient for the drift-diffusion part. A time-domain drift-diffusion simulator is developed to study the feasibility of the model, and good correspondence has been established for different devices with a commercial time-independent solution.

The system linearity of a power amplifier is estimated directly from device simulations using non-linear circuit transient analysis. For telecommunication systems the linearity is perhaps, at present, the most important factor requiring improvement. The need to estimate the system linearity directly from simulations is thus critical.

Device optimization by iterative simulations is used in the design of RF power devices with promising results. As the computational performance steadily increases, the use of optimization in device design is expected to be frequently used in the future.

7.1 Future Work There is still some important work required to further improve the design methods.

7.1.1 Device simulations Semiconductor simulation is a valuable tool for material characterization and device layout optimization. For material characterization first-order principle simulations, for instance based on the Monte-Carlo model, are required to extract unknown material properties. The Monte-Carlo method is also an

7.2 FUTURE TRENDS FOR SIC DEVICES 69

excellent tool for studies of internal phenomena in semiconductor devices, as well as extraction of device characteristics. For realistic MOSFET simulations the surface mobility model should however be improved further.

The most accurate device-simulation model used at present is the multi-band transport model. It is necessary to use the multi-band model at high electric fields for a better understanding of the breakdown mechanisms in SiC devices. The drawback of the Monte-Carlo method is the computational requirement necessary for device simulation. It may be a CPU-month for a simple IV-characterization of a transistor. The time domain drift-diffusion simulator should thus be included in the GEMS framework so that passive parts of the simulated devices could be solved in a significantly simpler manner.

7.1.2 Device Optimization In a device layout optimization 100-1000 simulations are required, which makes the Monte-Carlo method unsuitable. It is necessary to have a short simulation time to achieve a reasonable optimization time for a device. For SiC devices the drift-diffusion model is the best candidate for this purpose, due to the fast simulation time and its accuracy even for short devices.

Second order effects should be integrated into the device optimization, such as the developed methods for self heating and linearity. Additional effects such as wave propagation effects are interesting to incorporate into the design stage to obtain a better picture of the influence of phase differences in the device. This could possibly be achieved by either a lumped element approach or integration of the active element in some electromagnetic simulator. The dynamics of the heating is also important particularly at low frequencies but also in the case for RF frequencies, as the envelope of the signal might be much lower than the carrier itself.

The device optimization used here is only for SiC RF power devices, but should be extended to new materials, devices and applications. As the tool is implemented in an object oriented style this could easily be accomplished. The biggest challenge is to define new optimization goals that are critical for the specific application.

7.2 Future trends for SiC devices Silicon Carbide will most certainly be used widely for some specific applications within a few years. Today, SiC is used as a substrate for blue LEDs in GaN / InGaN. The main disadvantage at present for SiC devices is the price and long term stability, making it difficult to compete with large volume Si devices. Volume products are therefore required to reduce the price for SiC substrates and processing. These volume products have to be

70 CHAPTER 7. Summary and Conclusions

devices that outperform their silicon counterparts. For high-temperature applications SiC has a tremendous advantage over Si in its large band gap. Silicon devices can operate to about 150°C, which can be extended to the 200-300°C range using silicon on insulator technology [128]. For silicon carbide the high-temperature range can be extended further to over 600°C using standard devices. Immaturities in packaging technology are still a problem for these high temperatures. Commercial devices operating for a long time at 600°C with large thermal cycles are thus still not commercially available. For high-temperature logics the SiC MOSFETs are most suitable. Assuming that the problems concerning the gate-oxide layer can be solved, SiC may find a necessary volume product in automobile electronics. Other interesting applications are base stations for mobile communication systems and switched power supplies working at increased frequency. SiC Schottky diodes and MESFETs are commercially available and more and significantly better devices are expected to follow.

References [1] www.synopsys.com

[2] C. Jacoboni, P. Lugli, "The Monte Carlo Method for Semiconductor Device Simulation", Springer-Verlag Wien New-York, 1989.

[3] A. Elasser, T. P. Chow, “Silicon Carbide Benefits and Advantages for Power Electronics Circuits and Systems”, Proceeding of the IEEE, Vol. 90, No. 6, june 2002.

[4] www.cree.com

[5] J. P. Henning, A. P Przadka, M. R. Melloch, J. A. Cooper Jr, ”A Novel Self-Aliged Fabrication Process for Micrwave Static induction Transitors in Silicon carbide”, IEEE elec. Dev. Lett. Vol. 21, No. 12, 2000, pp. 578-580.

[6] H.Ö. Ólafsson, G. Gudjónsson, P.-A. Nilsson, E. Ö. Sveinbjörnsson, H. Zirath, T. Rödle and R. Jos, "High field effect mobility in Si face 4H-SiC MOSFET transistors", IEE. elec. letter., Vol. 40, No. 8, 2004

[7] www.infineon.com

[8] Cree research “Silicon Carbide Product Specification”, version 981218.05,

[9] D. Nakamura, I. Gunjishima, S. Unjishima, S. Yamaguchi, T. Ito, A. Okamoto, H. Kondo, S. Onda, K. Takatori, "Ultrahigh-quality silicon carbide single crystals", Nature 430, 2004, 1009 – 1012.

[10] V. Dimitrev, S. Trendakova, N. Kuznetsov, N. Savkina, A. Andreev, M. Rastegaeva, M. Mynbaeva, A. Morozov, ”Large area silicon carbide devices fabricated on SiC wafers with reduced micropipe density”, Mtrl. Sci. and Eng. B61-62, 1999, pp. 446-449.

[11] U. Lindefelt, H. Iwata, Book chaper in: W.J. Choyke, H. Matsunami, G. Pensl, "Silicon Carbide, Recent Major Advences", Springer-Verlag, Berlin, 2004.

[12] M. K. Das, J. J. Sumakeris, S. Krishnaswami, M. J. Paisley, A. K. Agarwal, A. Powell, "Latest Advances in High Voltage, Drift Free, 4H-SiC PiN Diodes", International Semiconductor Device Research Symposium, 2003, pp.:364-365

[13] J. B. Tucker, M. V. Rao, O. W. Holland, P. H. Chi, G. C. B. Braga, J. A. Freitas, Jr. N. Papanicolaou, “Material and n-p junction characteristics os As- and Sb-implanted SiC”, Diamond and Related Material 9, 2000, pp. 1887-1896.

[14] J. Pernot, J. Camassel, S. Contreras, J. L. Robert, J. M. Bluet, J. F. Michaud, T. Billon, “Control of Al-implantation doping in 4H-SiC”, Matrl. Sci. and Eng. B80, 2001, pp. 362-365.

72 REFERENCES

[15] C. Richter, K. Espertshuber, C. Wagner, M. Eickhoff, G. Krötz, “Rapid plasma etching of cubic SiC using NF3/O2 gas mixtures“, Matrl. Sci. and Eng. B46, 1997, pp.160-163.

[16] S.-K. Lee, C-M. Zetterling, M. Östling, ”Schottky diode formation and charaterizationof titanium tungsten to n- and p-type 4H silicon carbide ”, J. Appl. Phys. 87(11), June 2000, pp. 8039-8044.

[17] S.-K. Lee, C-M. Zetterling, M. Östling, J. P. Palmquist, H. Högberg, U. Jansson, “Low resistivity ohmic contacts to n- and p-type 4H-silicon carbide”, Solid-State Electronics Vol 44, 2000, pp. 1179-1186

[18] M. Roschke, F. Schwiertz, “Electron mobility Models for 4H, 6H, and 3C SiC”, IEEE trans. Elec. Dev. Vol. 48, No. 7, 2001, pp1442-1447.

[19] F. Draghici, F. Mitu, G. Brezeanu, M. Badila, C. Boianceanu, P. Agache, I. Enache, "Electrical and Optical Behaviour of the SiC Photodetectors", Semiconductor Conference, Proc. of 2002. CAS International, Volume: 1 , 8-12 Oct. 2002

[20] W. M. Vetter, W. Huang, P. Neudeck, J. A. Powell, M. Dudley, ”Synchrotron white-beam topography studies of 2H-SiC crystals”, J. Crystal Growth 244, 2001, pp. 269-273.

[21] W. J. Schaffer, G. H. Negley, K. G. Irvine, J. P. Palmour, “Conductivity anisotrophy in epitaxial 6H and 4H SiC”, MRS Proceedings No. 339, Material Researsh Society, 1994, pp. 595-600.

[22] I. A. Khan, J. A. Cooper Jr, “Measurement of High-Field Electron Transport in Silicon Carbide”, IEEE transaction on electron devices Vol. 47, No. 2, 2000, pp. 269-273.

[23] H-E. Nilsson, M. Hjelm, C. Fröjdh, C. Persson, U. Sannemo, C. S. Petersson, “Full Band Monte Carlo simulation of electron transport in 6H-SiC”, Journal of applied physics, Vol. 86, No. 2, 1999, pp. 965-973.

[24] H-E. Nilsson, U. Sannemo, C. S. Petersson, “Monte Carlo simulation of electron transport in 4H-SiC using a two band model with multiple minima”, Journal of applied physics Vol. 80, No 6, 1996, pp.3365-3369.

[25] H-E. Nilsson, M. Hjelm, “Monte Carlo simulation of electron transport in 2H-SiC using a three valley analytical conduction band model”, Journal of applied physics Vol. 86, No 11, Dec 1999, pp. 6230-6233

[26] W. Götz, A. Schöner, G. Pensel, W. Suttrop, W. J. Choyke, R. Stein, S. Leibenzeder, "Nitrogen donors in 4H-silicon carbide", Journal of Applied Physics 71 (7), April 1993, pp. 3332-3338.

[27] A. Schöner, S. Karlsson, T. Schmitt, N. Nordell, M. Linnarsson, K. Rottner, ”Hall effect investigation of 4H-SiC epitaxial layers on semi-insulating and conducting substrates”, Material Science and Engineering B61-62, 1999, pp. 389-394.

REFERENCES 73

[28] C. Persson, U. Lindefelt, B. E. Sernelius, "Doping-induced effects on the band structure in n-type 3C-, 2H-, 4H- , 6H-SiC, and Si.", Phys. Rev. B 1999;60;16479.

[29] S. Selberherr "MOS Device Modeling at 77K", IEEE Trans. Elec. Dev. 1989;36:8:1464-1474.

[30] C. Harris, AMDS, Private Communications.

[31] H. Albrecht, R. Müller, “The Anamalous Avalanche Breakdown“, IEEE trans. On Elec. Dev. 27 (5) May 1980, pp. 970-977.

[32] Yu. A. Vodakov, A. O. Konstantinov, D. P. Litvin, V. I. Sankin, ”Avalanche ionization in silicon carbide p-n junctions”, Sov. Tech. Phys. Lett. 7(6), June 1981, pp. 301-302.

[33] A. P. Dmitriev, A. O. Konstantinov, D. P. Litvin, V. I. Sankin, ”Impact Ionization and Superlattice in 6H-SiC”, Sov. Phys. Semicond. 17(6), June 1983, pp. 686-689.

[34] A. O. Konstantinov, “’Hot’ luminescence due to electric breakdown of p-n junctions in silicon carbide” ”, Sov. Phys. Semicond. 21(4), April 1987, pp. 410-413.

[35] M. M. Anikin, S. N. Vainshtein, M. E. Levinshtein, A. M. Strel’chuk, A. L. Syrkin, ”Negative temperature coefficients of the breakdown voltage in silicon carbide p-n junctions”, Sov. Tech. Phys. Lett. 14 (3), march 1988, pp. 243-244.

[36] M. M. Anikin, M. E. Levinshtein, I. V. Popov, V. P. Rastegaev, A. M. Strel’chuk, A. L. Syrkin, ”Temperature dependence of the avalanche breakdown voltage of silicon carbide p-n junctions”, Sov. Phys. Semicond. 22(9), Sept 1988, pp. 995-998.

[37] A. O. Konstantinov, Q. Wahab, N. Nordell, U. Lindefelt, “Ionization rates and critical fields in 4H silicon carbide“, Appl. Phys. Lett. 71(1), July 1997, pp 90-92.

[38] R. Raghunathan, B. J. Baliga, “Temperature dependence of hole impact ionization coefficients in 4H and 6H-SiC”, Solid-State Electronics 43, 1999, pp. 122-211.

[39] H.-E. Nilsson, E. Bellotti, K. F. Brennan, M. Hjelm, ”A Full Band Monte Carlo Study of High Field Carrier transport in 4H-SiC”, Materials Science Forum Vols. 338-342, 2000, pp. 765-768.

[40] A. O. Konstantinov, "Hot luminiscence due to electric breakdown of p-n junctions in silicon carbide", Sov. Phys. Semicond. 21(4), 1987, pp.410-414

[41] C. Banc, E. Bano, T. Ouisse, O. Noblanc, C. Brylinski, "Hot-Carrier Luminicence in 4H-SiC MESFETs", Mtrl. Sci. Forum Vols. 389-393, 2002, pp. 1371-1374.

[42] A. O. Konstantinov, Private Communication.

74 REFERENCES

[43] T. Hatakeyama, T. Watanabe, K. Kojima, N. Sano, K. Shiraishi, M. Kushibe, S. Imai, T. Shinohe, T. Suzuki, T. Tanaka, K. Arai, "Impact Ionization Coefficients of 4H-SiC", Material Science Forum Vols 457-460, 2004, pp. 673-676

[44] H.-E. Nilsson, A. Martinez, U. Sannemo, M. Hjelm, E. Bellotti, K. F. Brennan, ”Monte carlo simulation of high field hole transport in 4H-SiC including band to band tunneling and optical interband transistion”, Physica B 314, 2002, pp. 68-71

[45] M. Hjelm, H.-E. Nilsson, A. Martinez, K. F. Brennan, E. Bellotti, "Monte Carlo study of high-field carrier transport in 4 H-SiC including band-to-band tunneling", Journal of Appl. Phys. Vol. 93, No 2, pp. 1099-1107

[46] A. Galeckas, J. Linnros, M. Frischolz, K. Rottner, N. Nordell, S. Karlsson, V. Grivickas, ”Investigation of surface recombination and carrier lifetime in 4H/6H-SiC”, Material Science and Engineering B61-62, pp. 239-243, 1999

[47] A. Galeckas, O. Tornblad, J. Linnros, B. Breitholtz, ”Direct Observation of Excess Carrier Distribution in 4H-SiC Power Diodes”, IEEE Electron Device Letters, Vol. 20, No. 6, pp 295-297, 1999.

[48] P. Grivickas, A. Galeckas, J. Linnros, M. Syväjärvi, R. Yakimova, V. Grivickas, J. A. Tellefsen, ”Carrier lifetime investigation in 4H-SiC grown by CVD and sublimation epitaxy”, Mtrl. Sci. in Semiconductor Processing 4, pp 191-194, 2001

[49] J. P. Bergman, “Carrier lifetimes in SiC, studied by time resolved photoluminiescence spectroscopy”, Diamond and related Materials 6, pp. 1324-1328, 1997.

[50] P. A. Ivanov, M. E. Levinshtein, K. G. Irvine, O. Kordina, J. W. Palmour, S. L. Rumyantsev, R. Singh, ”High hole lifetime (3.8µs) in 4H-SiC diodes with 5.5kV blocking voltage”, Electronic Letters, Vol. 35, No. 15, pp 1382-1383, 1999.

[51] M. E. Levinshtein, T. T. Mnatsakanov, P. Ivanov, J. W. Palmour, S. L. Rumyantsev, R. Singh, S. N. Yurkov, “’Paradoxes’ of Carrier Lifetime Measurements in High-Voltage SiC Diodes”, IEEE trans. Elec. Dev., Vol. 48, No. 8, pp. 1703-1709, 2001

[52] Singh, R.; Cooper, J.A., Jr.; Melloch, M.R.; Chow, T.P.; Palmour, J.W, "SiC power Schottky and PiN diodes", IEEE Trans. on Electron Devices, Vol. 49, No. 4, pp. 665–672, 2002

[53] M. Lundstrom, Fundamentals Of Carrier Transport, Second Edition, Cambridge University Press, 2000.

[54] P. Käckell, B. Wenzien, F. Bechstedt, "Electronic properties of cubic and hexagonal SiC polytypes from ab initio calculations", Phys. Rev. B 50, pp. 10761-10768, 1994

REFERENCES 75

[55] C. Persson, U. Lindefelt, "Relativistic band structure calculation of cubic and hexagonal SiC polytypes", J. Appl. Phys. Vol. 82, pp. 5496-5508, 1997

[56] Bellotti, E.; Nilsson, H.; Brennan, K.F.; Ruden, P.P.; Trew, R, "Monte Carlo calculation of hole initiated impact ionization in 4H phase SiC", Journal of Applied Physics Vol. 87, pp. 3864, 2000

[57] R. W. Hockney and J. W. Eastwood, "Computer simulation using particles", Adam Hilger,New York, 1988,

[58] K. Hess, "Monte Carlo Device Simulation: Full Band and Beyond", Kluwer Academic Publishers, 1991.

[59] M. Hjelm, "Monte Carlo Simulations of Homogeneous and Inmomogeneous Transport in Silicon Carbide", Doctoral Thesis, KTH, Stockholm, Sweden, 2004, http://media.lib.kth.se.

[60] M. B. Patil, Y. Ohkura, T. Toyabe, S. Ihara, "Note On Cpupling the Drift-Diffusion and Monte-Carlo Models for MOSFET Simulation", Solid-State Electronics Vol. 38, No. 4, pp. 935-936, 1995.

[61] U. Lindefelt, "Equations for Electrical and Electrothermal Simulation of Anisotropic Semiconductors", J. Appl. Phys Vol. 76, No. 7, pp. 4162-4167.

[62] V. Khemka, T. C. Chow, R. J. Gutman, ”Voltage Handling Capability and Microwave Performance of a 4H-SiC MESFET – A Simulation Study”, Material Science Forum Vols. 264-268, 1998, pp. 961-964

[63] C. Codreanu, M. Avram, E. Carbunescu, E. Iliescu, “Comparisson of 3C-SiC, 6H-SiC and 4H-SiC MESFETs performance”, Materials Science in Semiconductor Processing 3, 2000, pp. 137-142.

[64] M. Huang, I. D. Mayergoyz, N. Goldsman, “Numerical simulation of small.signal microwave performance of 4H-SiC MESFET”, Solid-State Electronics 44, 2000, pp. 1281-1287.

[65] M. Huang, N. Goldsman, C.-H. Chang I. D. Mayergoyz, J. M. McGarrity, D. Woolard, “Determining 4H silicon carbide electronic properties through combined use of device simulation and metal-semiconductor field-effect-transistor terminal characteristics”, Journal of Applied Physics Vol. 84, No. 4, 1998, pp. 2065-2070.

[66] M. Lades, W. Kaindl, N. Kaminski, E. Niemann, G. Wachutka, ”Dynamics of Incoplete Ionized Dopants and Their Imact on 4H/6H-SiC Devices”, IEEE Transaction on Electron Devices, Vol. 46, No. 3, 1999, pp. 598-604

[67] F. Nallet, A. Sénès, D. Planson, M. L. Locatelli, J. P. Chante, J. P. Taboy, “Electrical and Electrothermal 2D Simulations of a 4H-SiC High Voltage Current Limiting Device for Serial Protection Applications”, Proc. of Power Semiconductor Devices and ICs, 2000, pp. 287-290

76 REFERENCES

[68] N. Arssi, M. L. Locatelli, D. Planson, J. P. Chante, V. Zorngiebel, E. Spahn, S. Scharnholz, ”Study Based on the Numerical Simululation of a 5 kV Asymmetric 4H-SiC Thyristor for High Power Pulses Application“, Proc. Of Semiconductor Conference, CAS 2001, vol.2, pp. 341-344

[69] A. Mihaila, F. Udrea, G. Brezeanu, G. Amaratunga, “A numerical comparison between MOS control and junction control high voltage devices in SiC technology”, Solid-State Electronics, Volume 47, No. 4, pp. 607-615, 2003

[70] J. H. Zhao, X. Li, K. Tone, P. Alexandrov, M. Pan, M. Weiner, ”Design of a novel planar normally-off power VJFET in 4H-SiC”, Solid-State Electronics, Volume 47, Issue 2, Pages 377-384, 2003

[71] H. Sakata, M. Zahim, ”Device Simulation of SiC-GTO”, Proc of Power Conversion Conference, 2002, Vol 1, pp. 220-225

[72] F. Schwierz, M. Roschke, J. J. Liou, G. Paasch, “Theoretical Investigation of the Electrical Behaviour of SiC MESFETs for Microwave Power Amplification“, Material Science Forum Vols. 264-268, 1998, pp. 973-976.

[73] S.P. Murray, K.P. Roenker, "An analytical model for SiC MESFETs", Solid-State Electronics Vol. 46, 2002, pp. 1495–1505

[74] F. Schwierz, M. Kitter, H. Förster, D. Schipanski, “The potential of SiC and GaN for application in high speed devices“, Diamond and related Materials 6, 1997, pp. 1512-1514.

[75] M. S. Shirokov, R. E. Leoni, C. J. Wei, J. C. M. Huang, ”Breakdown Effects on the Performance and Reliability of Power MESFETs”, Technical Digest 1996, 18th Annual Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, pp. 34-37, 1996

[76] M. Roschke, F. Schwierz, "Electron Mobility Models for 4H, 6H, and 3C SiC.", IEEE Trans. Elec. Dev. Vol. 48, No. 7, 2001, pp. 1442-1447.

[77] A. S. Royet, T. Ouisse, B. Cabon, O. Noblanc, C. Brylinski, "Self-Heating Effects in Silicon Carbide MESFETs", IEEE Trans. Elec. Dev. Vol. 47, No. 11, 2000, pp. 2221-2227.

[78] W. Liu, E. Danielsson, C.-M. Zetterling, M. Östling, "Electro-Thermal Investigation of High Power Silicon Carbide Transistors", Proc. 4th IEEE Int. Symp. on High Density Packaging and Component Failure Analysis in Electronics Manufacturing (HDP’ 02), 2002, pp.175-178.

[79] www.comsol.com

[80] George D. Vendelin, Microwave Circuit Design Using Linear and Nonlinear Techniques, John Wiley and Sons, 1990.

[81] Nelder J. A., Mead R., "A simplex method for function minimization", Comput. J. Vol. 7, 2000, pp. 308-313.

[82] Ingber L. "Very fast simulated re-annealing. Mathematical Computer Modeling", Vol. 12, No. 8, 1989; pp.967-973.

REFERENCES 77

[83] S. T. Allen, R. A. Sadler, T. S. Alcorn, J. W. Palmour, C. H. Carter Jr., "Silicon Carbide MESFET's for high-power S-band applications", Proceedings of the IEEE int. Microwave Symposium Digest, Vol. 3, 1997, pp. 57-60.

[84] J. Eriksson, N. Rorsman, H. Zirath, R. Johansson, Q. Wahab, S. Rudner, “A Comparisson between Physical Simualtions and Experimental Results in 4H-SiC MESFETs with Non-Constant Doping in the Channel and Buffer Layers”, Material Science Forum Vols. 353-356, 2001, pp. 699-702.

[85] D. Siriex, D. Barataud, R. Sommet, N. Noblanc, Z. Ouarch, Ch. Brylinski, J. P. Teyssier, R. Quere, ”Charaterization and modeling of nonlinear trapping effects in power SiC MESFETs”, 2000 IEEE MTT-S International Microwave Symposium Digest., Vol 2 , pp.765-768, 2000

[86] O. Noblanc, C. Arnod, C. Dua, E. Chartier, C. Brylinski, “Progress in the use of 4H-SiC semi-insulating wafers for microwave power MESFETs”, Material Science and Engineering B61-62, 1999, pp. 339-344.

[87] C. Banc, A. S. Royet, T. Ouisse, E. Bano, O. Noblanc, C. Brylinski “Noise Bahaviour of 4H-SiC MESFETs at Low Drain Voltages”, Material Science Forum Vols. 353-356, 2001, pp.703-706.

[88] C. Brisset, O. Noblanc, C. Picard, F. Joffre, C. Brylinski, “4H-SiC MESFETs Behavior After high Dose Irradiation”, IEEE Trans on Nuclear Science Vol. 47, No. 3, 2000, pp. 598-603.

[89] P. Å. Nilsson, A. M. Saroukhan, J. O. Svedberg, A. Konstantinov, S. Karlsson, C. Adås, U. Gustafsson, C. Harris, N. Rorsman, J. Eriksson, H. Zirath, “Charaterization of SiC MESFETs on Conducting Substrates”, Material Science Forum Vols. 338-342, 2000, pp. 1255-1258

[90] S. Sriram, R. Barron, A. W. Morse, T. J. Smith, G. Augestine, A. A. Burk Jr., R. C. Clarke, R. C. Glass, H. M. Hobgood, P. A. Orphanos, R. R. Siergiej, C. D. Brandt, M. C. Driver, R. H. Hopkins, “High Efficiency Operation of 6H-SiC MESFETs at 6 GHz”, Digest. 1995 53rd Annual Device Research Conference, pp. 104-105, pp-1995

[91] K. Moore, M. Bhatnagar, C. Weitzel, L. Pond, T. Gehoski, T. Chatham, “Temperature Dependent Small- and Large-Signal Performance of 4H-SiC MESFETs“, Material Science Forum Vols. 264-268, 1998, pp. 957-960.

[92] K. Moore, C. Weitzel, K. Nordquist, L. Pond III, J. Palmour, S. Allen, C. Carter. Jr., “Bias Dependence of RF Power Charateristics of 4H-SiC MESFETs”, Proceedings of 1995 IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, pp. 40-46, 1995

[93] O. Noblanc, E. Chatier, C. Arnodo, C. Brylinski, “Microwave Power MESFET on 4H-SiC” Diamond and Related Materials 6, 1997, pp. 1508-1511.

78 REFERENCES

[94] S. T. Allen, W. L. Pribble, R. A. Sadler, T. S. Alcorn, Z. Ring, J. W. Palmour, “Progress in high power SiC microwave MESFETs”, IEEE International Microwave Symposium Digest, Piscataway, NJ, USA, Vol 1, 1999; pp.321-324

[95] R. A. Sadler, S. T. Allen, T. S. Alcorn, W. L. Pribble, J. Sumakeris, J. W. Palmour, L. T. Kehias, “SiC MESFET with Output Power of 50 W CW at S-Band”, Device Research Conference Digest, pp. 92-93, 1998.

[96] S. T. Allen, J. W. Palmour, V. F. Tsvetkov, S. J. Macko, C. H. Carter Jr, C. E. Weitzel, K. E. Moore, K. J. Nordquist, L. L. Pond III, “4H-SiC MESFETs on High Resistivity Substrates with 30 GHz fmax”, Digest. 1995 53rd Annual Device Research Conference, pp. 102-103, 1995

[97] S. Sriram, G. Augestine, A. A. Burk Jr, R. C. Glass, H. M. Hobgood, P. A. Orphanos, L. B. Rowland, T. J. Smith, C. D. Brandt, M. C. Driver, R. H. Hopkins, ”4H-SiC MESFET´s with 42 GHz fmax”, IEEE Electron device Letters Vol. 17, No. 7, 1996, pp. 369-371.

[98] N. Rorsman, J. Eriksson, H. Zirath, "Fabrication, Charaterization, and modelling of SiC MESFETs", Mtrl. Sci. Forum Vols. 338-342, pp. 1259-1262, 2000

[99] A. O. Konstantinov, C. I. Harris, P. Ericsson, "High-Performance Silicon Carbide MESFET Utilizing Lateral Epitaxy", Mtrl. Sci. Forum Vols. 389-393, 2002, pp. 1375-1378.

[100] J. P. Henning, A. Przadka, M. R. Melloch, J. A. Cooper Jr., “Design and Demonstration of C-Band Static Induction Transistors in 4H Silicon Carbide”, IEEE Device Research Conference, 1999.

[101] Y. M. Sung, J. B. Casady, J. B. Dufrene, A. K. Agrawal, “A review of SiC static induction transistor development for high-frequency power amplifiers”, Solid-State Electronics 46, 2002, pp. 605-613

[102] R. C. Clarke, A. W. Morse, P. Esker, W. R. Curtice, “A 16W, 40% efficient, Continuous Wave, 4H-SiC, L-band SIT”, Proc of 2000 IEEE/Cornell Conference on High Performance Devices, 2000, pp. 141-143.

[103] R. R. Siergiej, R. C. Clarke, A. K. Agrawal, C. D. Brandt, A. A. Burk Jr, A. Morse, P. A. Orphanos, “High Power 4H-SiC Static Induction Transistors”, Int Electron Device Meeting Tech Dig, 1995, pp. 353- 356.

[104] R. J. Bojko, R. R. Siergiej, G. W. Eldridge, L.-S. Chen, A. W. Morse, J. Ostop, P. M. Esker, B. Barron, R. C. Clarke, C. D. Brandt, “Recent Progress in 4H-SiC Static Induction Transistors For High Frequency Power Generation”, IEEE Device Research Conference Digest,1997, pp. 96-97.

[105] R. C. Clarke, R. R. Siergiej, A. K. Agrawal, C. D. Brandt, A. A. Burk Jr, A. Morse, P. A. Orphanos, “30 W VHF 6H-SiC Power Static Induction Transistor”, Proceedings of 1995 IEEE/Cornell Conference on Advanced High Speed Semiconductor Devices and Circuits, pp. 47-55, 1995.

REFERENCES 79

[106] S. Hatzikonstantinidou, H.-E. Nilsson, C. Fröjdh, C. S. Petersson, W. Kaplan, “Processing and charaterization of a PBT device using seft-aligned CoSi2“, Semicond. Sci. Tech. 9, 1994, pp. 2272-2277.

[107] M. Bhatnager, B. J. Baliga, "Comparison of 6H-SiC, 3C-SiC, and Si for Power Devices", IEEE Trans. on Elec. Dev. Vol. 40, No. 3, 1993, pp. 645-655.

[108] H. Yano, T. Kimoto, H. Matsunami, M. Bassler, G. Pensl, ”MOSFET Performance of 4H-, 6H-, and 15R-SiC Processed by Dry and Wet Oxidation”, Material Science Forum Vols. 338-342, 2000, pp. 1109-1112.

[109] R. Schörner, P. Friedrichs, D. Peters, D. Stephani, "Significantly Improved Performance of MOSFET’s on Silicon Carbide Using the 15R-SiC Polytype", IEEE elec.Dev. Lett. Vol. 20, No. 5, pp 241-244, 1999.

[110] R. Kosugi, S. Suzuki, M. Okamoto, S. Harada, J. Senzaki, K. Fukuda, ”Strong Dependence of the Inversion Mobility of 4H and 6H SiC (0001) MOSFETs on the Water Content in Pyrogenic Re-Oxidation Annealing”, IEEE Elec. Dev. Lett. Vol. 23, No. 3, pp. 136-138, 2002.

[111] N. S. Saks, S. S. Mani, A. K. Agrawal, ”Interface Trap Profile Near the Band Edges in 6H-SiC MOSFETs”, Mtrl. Sci. Forum Vols.338-342, pp. 1113-1116, 2000.

[112] Y. Zeng, A. Softic, M. H. White, “Characterization of Interface traps in Subtreshold Regions of Implated 6H- and 4H-SiC MOSFETs“, Solid-State Electronics, Vol. 46, No. 10, pp. 1579-1582, 2002

[113] E. Sangiorgi, M. R. Pinto, "A semi-empirical model of surface scattering for Monte Carlo simulation of silicon n-MOSFETs", IEEE Trans. on Electron Devices, Volume. 39, No. 2 ,pp. 356–361, 1992

[114] H. Yano, T. Hirao, T. Kimoto, H. Matsunami, K. Asano, Y. Sugawara, ”Anisotropy on Inversion Channel Mobility in 4H- and 6H-SiC MOSFETs on ( )0211 Face”, Material Science Forum Vols. 338-342, pp 1108-1108, 2000.

[115] J. Senzaki, K. Kojima, S. Harada, R. Kosugi, S. Suzuki, K. Fukuda, “Excellent Effects of Hydrogen Postoxidation Annealing on Inversion Channel Mobility of 4H-SiC MOSFET Fabricated on ( )0211 Face”, IEEE Elec. Dev. Lett., Vol. 23, No. 1, pp. 13-15, 2002.

[116] S. Scharnholz, E. Stein von Kamienski, A. Gölz, C. Leonhard, H. Kurz, “Dependence of Channel Mobility on the Surfa Step Orientation in Planar 6H-SiC MOSFETs “, Material Science Forum Vols 264-268, pp. 1001-1004, 1998

[117] S. Harada, S. Suzuki, J. Senzaki, R. Kosugi, K. Adachi, K. Fukuda, K. Arai, “High Channel Mobility in Normally-Off 4H-SiC Buried Channel MOSFETs”, IEEE Elec. Dev. Lett., Vol. 22, No. 6, pp. 272-274, 2001

[118] S. Sridevan, B. J. Baliga, ”Inversion Layer Mobility in SiC MOSFETs”, Material Science Forum Vols. 264-268, pp. 997-1000, 1998.

80 REFERENCES

[119] D. Alok, E. Arnold, R.Egloff, J. Barone, J. Murphy, R. Conrad, J. Burke, “4H-SiC RF Power MOSFETs”, IEEE Elec.Dev. Lett., Vol. 22, No. 12, pp. 577-578, 2001.

[120] N. S. Saks, S. S. Mani, A. K. Agarwal, M. G. Ancona, ”A 475 V High-Voltage 6H-SiC Lateral MOSFET”, IEEE Elec. Dev. Lett., Vol. 20, No. 8, pp. 431-433, 1999.

[121] J. Spitz, M. R. Melloch, J. A. Cooper, G. Melnychuk Jr., S. E. Saddow, "2.7 kV epitaxial lateral power DMOSFETs in 4H-SiC", Device Research Conference Digest, 2000, 58th DRC pp. 127-128, 2000

[122] J. B. Casady, A. K. Agrawal, L. B. Rowland, S. Seshadri, R. R. Siergiej, D. C. Sheridan, S. Mani, P. A. Sanger, C. D. Brandt, “Silicon Carbide Power MOSFET Technology”, IEEE International Symposium on Compound Semiconductors, pp. 359-362, 1997

[123] H. Linewit, S. Dimitrijev, C. E. Weitzel, H. B. Harrison, “Novel SiC Accumulation-Mode Power MOSFET“, IEEE Trans. On Elec. Dev., Vol. 48, No. 8, pp. 1711-1717, 2001.

[124] Y. Sugawara, K. Asano, R. Singh, J. Palmour, D. Takayama, "4.5 kV High Voltage High Performance SiC-FET 'SIAFET'", ISPAD'2000, pp. 105-108, 2000.

[125] R. A. Reshanov, "Growth and high temperature performance of semi-insulating silicon carbide", Diamond and Related Materials, Volume 9, Issues 3-6, Pages 480-482, 2000

[126] St. G. Müller, D. Hoffmann, E. N. Mokhov, M. G. Ramm, A. D. Roenkov, Yu. A. Vodakov, A. Winnacker, “Electronic and Optical Properties of Vanadium Doped Silicon Carbide Crystals Grown by the Sublimation Sandwich Method”, Semiconducting and Semi-Insulating Materials Conf., 1996. IEEE , 1996, pp 219 -222

[127] Y. Watanabe, J. Nishizawa, Busseiron Kenkyu, vol. 41, p. 96, Aug 1951, Rep. 3:33 Joint Conf. IEEE, IECEJ and ILEJ, May 1951

[128] P. G. Neudeckm R. S. Okojie, L.-Y. Chen, "High temperature Electronics-A Role for Wide Bandgad Semiconductors?", Proc. of the IEEE, Vol. 90, No. 6, 2002, pp. 1065-1076.

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