Simple as Possible

8/11/2019 Simple as Possible

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Prepared By : Engr. Bhai Nhuraisha Ibrahim Delomo


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What is the meaning of SAP?


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SAP Simple-As-Possible (SAP) The main purpose of SAP is to introduce all the crucial

ideas behind computer operation


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What are the three different

generations of SAP?


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There are three different generations of SAP.(SAP-1 SAP-2 SAP-3)


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SAP - 1 Is the first stage in the evolutiontoward modern computers. Can only perform addition andsubtraction and no logical operation SAP1 has six T-states (three fetch andthree execute cycles) reserved for eachinstruction


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SAP-1 Architecture

Define archit

ect

ure


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Architecture Architecture is the conceptual design andfundamental operational structure of a computersystem.


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SAP-1 Architecture Has a 16 x 8 memory (16 mem orylocations with 8 bits in eachloca tion . S A P cannot store program havingmore than 16 loca tions.


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SAP-1 Architecture


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SAP 1 Architecture 1. Program Counter (PC) - Counts from 0000-1111 and it signals the memory

address of the next instruction to be fetched andexecuted.- used for proper execution of functions of

computer by providing address of next

instruction to microprocessor.


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3. RAM SAP-1 Architecture

- Program code to be executed and data for SAP-1 computer is stored.

- Receives 4-bit addresses from MAR and a readoperation is performed.


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SAP-1 Architecture 4. Instruction Register (IR) - contains the instruction, composed of

OPCODE + ADDRESS.- The contents of the IR is split into two nibbles;upper nibble that goes directly to the controller,sequencer and the lower nibble that is directed

into the WBUS.


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SAP-1 Architecture 5. Controller sequencer - Generates the signal for each block so th at

action occur in desired sequence. - Produces a 12- bit word that determines how the

register will react to the next positive CLK edge.


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SAP-1 Architecture 6. Accumulator - AN 8- bit buffer register that stores intermediate

results during a computer run. - one of the operands of ADD, SUB and OUT

instructions.


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SAP-1 Architecture 7. Adder / Subtractor - A 2s complement adder-subtractor.

- Its content can change as soon as the input wordchanges (asynchronous).


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SAP-1 Architecture 8. B Register (Buffer R egist er )

- 8-bit, primarily used to hol dthe other operand ofmathematical operat ion .


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SAP-1 Architecture 9. Output register - holds the output of the out instruction.

10.Binary display - Row of eight LED s to show the contents of the

output register.


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FETCH CYCLE ADDRESS STATE T1 INCREMENT STATE T2 MEMORY STATE

T3


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CON

Cp Ep m 1 1 A E A Su Eu B O Active

Address State 0 1 0 1 1 1 1 0 0 0 1 1 (T1) Ep m Increment 1 o 1 1 1 1 1 0 0 0 1 1 Cp State (T2)

Memory 0 0 1 0 0 1 1 0 0 0 1 1 1 State (T3)

FETCH CYCLE


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Example 1 If the system clock has a frequency of 2.5 MHz, how long is an instruction cycle?

The Period of the clock is T = 1/f = .5 MHz = 400ns Therefore, each T state last 400ns. Since it takes 13T states to fetch and execute the LDA instruction, the instruction cycle lasts for

13 x 400 ns =5,200 ns = 5.2s


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Counter-cp Ep-execute CE - Chip Enable


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EXECUTION CYCLE LDA ROUTINE ADD ROUTINE SUB ROUTINE OUT ROUTINE


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CON

LDA Cp Ep m 1 1 A E A Su Eu B O Active

LDA T4 m, 1

LDA T5 , A

LDA T6 NONE

EXECUTION CYCLE


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SAP-1 Architecture Summary SAP-1 control unit consists of

program counter (PC) Instruction Register (IR) Controller sequencer

SAP-1 ALU consists of Accumulator Adder-subracter B register

SAP-1Memory MAR 16x8 RAM

I/O unit Input programming switches Output port Binary Display


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SAP-1 INSTRUCTION LDA ADD SUB OUT

HLT


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PROGRAMING SAP-1


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SAP-1 Instruction LDA Load addressed memory contents into theaccumulator.

ADD content of the accumulator will be added to thecontent of the memory in the address placing the sumback to the accumulator.

SUB Subtract addressed memory contents from

accumulator. OUT Load accumulator data into the output register. HLT Stop Processing.


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SAP-1 OP CODE (Operation Code)

Mnemonics Opcode

LDA 0000

ADD 0001

SUB 0010

OUT 1110

HLT 1111


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What is the difference between the Assembly Language &

Machine Language?


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Assembly Language Involves working with mnemonics when writing a program Source program

Machine Language

Involves working with strings of 0s and 1s Object program


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EXAMPLE 1 Translate this program into SAP-1 machine language

Address Instruction

0H LDA 9H1H ADD AH2H ADD BH3H SUB CH4H OUT5H HLT


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0001 0001 1010 0010 0001 1011

0011 0010 1100

0100 1110xxxx

0101 1111xxxx

Address Instruction 0H LDA 9H1H ADD AH2H ADD BH3H SUB CH4H OUT5H HLT

Solution (OPCODE + ADDRESS) Address Instruction

0000 0000 1001

Mnemonics Opcode

LDA 0000 ADD 0001

SUB 0010 OUT 1110

HLT

1111


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Assignment How would you program SAP-1 to solve this Arithmeticproblem?

16 + 20 + 24-32 LDA A DD A DD SUB OUT HLT

Note : Table the Address and its Contents (9H is the address, thecontent of 9H is 10H ). Use addresses 9H to CH for the data

Address Contents 0H LDA 9H

How would you program SAP-1 to solve this Arithmetic problem?


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Address Contents

0000 0000 1001

0001 00011010 0010 00011011 0111 00101100 0100 1110 XXXX0101 1111 XXXX0110 XXXX XXXX0111 XXXX XXXX

1000 XXXX XXXX1001 0001 0000 1010 0001 0100 1011 0001 1000

y p g p

16 + 20 + 24 -32

Assembly Language

Machine Language

Address Contents oH LDA 9H1H ADD AH2H ADD BH

3H SUB CH4H OUT5H HLT6H XX7H XX8H XX9H 10H AH 14H BH 18H

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