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Silicon Photonics: Enabling technologies & products
Laurent FulbertManager for Strategic Programs in Integrated Photonics
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 2
Outline
Rationale for silicon photonics
Silicon photonics: main building blocks
From components to circuits
Perspectives and conclusion
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 3
Outline
Rationale for silicon photonics
Silicon photonics: main building blocks
From components to circuits
Perspectives and conclusion
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 4
The zettabyte era
In 2011, 1.8 zettabytes of information created and replicated (source: IDC)
In 2015 the annual run rate of global IP traffic will reach the zettabyte threshold (source: Cisco)
And it’s doubling every 2 years !50 zettabytes by 10 years
>1 yottabyte by 20 years
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 5
Power and bandwidth issues in electronic systemsData centers represent 3% of total U.S. Energy Consumption
Several bottlenecks: process‐to‐memory, backplane, switches, …
Source : Cisco Cloud Index 2011
80% of traffic staysin data center
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 6
The benefits of optical interconnects
Very high capacity: Tb/s links achievable
Scalability through Wavelength Division Multiplexing (WDM)
Lower power consumption
Electrical I/O Optical I/O
Courtesy of IBM
Courtesy of IBM
Optics is the only so
lution to meet bandw
idth density and
power consumption requ
irements
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 7
Silicon photonics at LETI
Our objectives: Build a complete technology platform (design, process, test, packaging) for photonics /electronics integration
Our approachPhotonics/electronics 3D integration
yield, performance, cost
Heterogeneous integration III‐V on silicon
wafer‐scale laser integration
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 8
Outline
Rationale for silicon photonics
Silicon photonics: main building blocks
From components to circuits
Perspectives and conclusion
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 9
I/O & waveguides
Edge coupling with inverted taper: <1dB losses
WaveguidesTransitionsSplittersMMIResonators AWGoNoCSlow wave structure
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 10
Germanium photodetectors
~ 90 GHz
15 GHz
40 GHz
AWG 400GHz
-45
-40
-35
-30
-25
-20
-151550 1555 1560 1565 1570 1575 1580 1585
Lambda (nm)
P (d
Bm
)
Voie 1Voie 2Voie 3Voie 4Voie 5Voie 6Voie 7Voie 8
Eye diagram @ 40Gbps
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 11
Carrier depletion modulators
40Gb/s operation demonstrated3.2dB ER, 4.5 dB losses, 1 mm
Demonstration of slow light devices at 40Gb/s
400 nm100 nm
660 nm
P+ N+
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 12
Laser integration process
1- Processed SOI substrate
2- PECVD silica deposition
3- CMP planarization
4- Surface Cleaning
Surface cleaning
Laser processing
III-V heterostructureSOI substrate
Low temperature bonding
0 50 100 150 200 250 300 350 4000
2
4
6
8
10
12
14
16
18
0
2
4
6
8
10
12
14
16
18
L out (
mW
)
I (mA)
15°C 20°C 25°C 30°C 35°C 40°C 45°C 50°C 55°C 60°C
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 13
Wafer level testing
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 14
Outline
Rationale for silicon photonics
Silicon photonics: main building blocks
From components to circuits
Perspectives and conclusion
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 15
Tunable lasers
20 mA threshold at room temperature
>45dB SMSR, tuning range 45nm
10Gb/s transmission with direct modulation
‐80
‐70
‐60
‐50
‐40
‐30
‐20
‐10
0
1520 1530 1540 1550 1560 1570 1580
Power (dBm)
Wavelength (nm)
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 16
Integrated transmitterHybrid III‐V/Si laser + silicon modulator
8 nm wavelength tunability at 1550 nmLaser Ring resonator
Mach-Zehnder ModulatorIII-V waveguideBack Bragg
reflectorSilicon MZ modulator Output
waveguideHybrid III-V/Si laser
Front Bragg reflector
154015411542154315441545154615471548154915501551
0 5 10 15 20 25 30
Heating power (mW)
Wavelen
gth (nm)
λ1λ2λ3λ4λ5
λ6λ7λ8
λ 5 λ 6
λ 7 λ 8
λ 1 λ 2
λ 3 λ 4
Eye diagram @ 10Gb/s
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 17
PhotonicsTransistors
How to integrate photonics with electronics ?
Monolithic integration
☺ Very low parasitics
Custom SOI, specific libraries
process co‐integration
Size and cost of photonics
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 18
PhotonicsTransistors
How to integrate photonics with electronics ?
Monolithic integration
☺ Very low parasitics
Custom SOI, specific libraries
process co‐integration
Size and cost of photonics
3D integration, chip‐to‐wafer
Higher (but reasonable) parasitics
☺ No change in CMOS Front‐End
☺ Separate processes
☺ Chip size doesn’t matter
Transistors
Photonics
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 19
Outline
Rationale for silicon photonics
Silicon photonics: main building blocks
From components to circuits
Perspectives and conclusion
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 20
Chip C
Chip A
Chip D
Chip B
Roadmap: from links to networks
Optical modulesActive Optical Cables
Board to boardRack to rack Board level In package
Chip B
Chip C
Chip A
Chip D
Optical I/O Optical networkin package
Electrical links in the packageHigh bandwidth optical I/O
Optical links in the packageHigh bandwidth optical I/O
Time
Backplane
Processor ProcessorMemory
Optics OpticsOptics
Optics
Tx optical chip
Optical Tx (red)
OpticsOptics
Optics
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 21
Conclusion
Photonic links will replace copper links, even for very short distances
Photonic Integration on silicon is key To reach competitive cost
To reduce size and power consumption while scaling up bandwidth
LETI has been developing an integration platform for silicon photonics
High performance building blocks demonstrated
Versatile photonics‐electronics integration process
L. Fulbert ‐ Leti Day in Nagoya, October 4th 2012| 22
Thank you for your attention
