Silicon Carbide Processing Technology: Issues and Challengescsmantech.pairserver.com/Workshops/0014_final-capano.pdf · Silicon Carbide Processing Technology: Issues and Challenges

Silicon Carbide Processing Technology: Issues and Challenges

Michael A. CapanoSchool of ECE, Purdue University

May, 2007

2 out of 83Michael A. CapanoMichael A. CapanoMichael A. CapanoMichael A. CapanoPurdue, ECEPurdue, ECEPurdue, ECEPurdue, ECE

Outline� Introduction

� Epitaxial growth of 4H-SiC by hot-wall CVD

(Si-face and C-face)

� 4H-SiC bipolar pin diodes

(Si-face 8o and Si-face 4o)

� Channel mobility in SiC MOSFETs

� Process-dependence of channel mobility


Potential Applications for SiC

Automobiles

Spacecraft

Aircraft

Power

Radar/Communications

MEMS


Polytypism: A Virtue and Curse of SiC

C

Si

A

BC


4H3C

AA A AB BB BC CCC

c-axis

C

Si

Stacking Sequence of 3C- and 4H-SiC


3.33.93.31.5Thermal conductivity (W/cmK)

9.79.79.711.8Dielectric constant

2 x 1072 x 1072 x 1071.0 x 107Saturation velocity (cm/s)

1 x 1063 x 1063 x 1063 x 105Breakdown field (V/cm)

?12095460Hole mobility (cm2/Vs)

1000800 (⊥ c)900 ( c)

400 (⊥ c)85 ( c)

1350Electron mobility (cm2/Vs)

1.5 x 1021.6 x 10-83 x 10-61.5 x 1010Intrinsic carrier concentration (cm-3)

2.323.263.031.12Bandgap (eV)

3C-SiC4H-SiC6H-SiCSi

Selected Properties of SiC


Doping of SiC

p-type (Al, B) n-type (N, P)

SiC P/N junction

Methods for doping� in-situ (CVD)

� ion implantationNote: diffusion to achieve selective doping is not an option in SiC

Methods for annealing � Argon ambient (severe

roughening)

� SiH4/Ar ambient (smooth surfaces, narrow process window)

� Graphite-capped anneal (best results)

Step bunching in implanted SiC

Step spacing ≈ 1 µm

Step bunching sensitive to anneal ambient and temperature


Horizontal cold-wall CVD reactor

Horizontal hot-wall CVD reactor

Vertical hot-wall CVD reactor

CVD

4H-SiC Material Growth

� Bulk growth: Seeded sublimation (Modified-Lely) methodDiameter: up to 100 mm; Boule length: 25~30mmOff-cut angle: 4o or 8o; Polarity: C-face or Si-face

� Epitaxial growth: chemical vapor deposition (CVD), Liquid-phase epitaxy (LPE), Sublimation epitaxy

� Good temperature uniformity

� Higher growth rate and good film quality

Horizontal hot-wall CVD reactor


4H-SiC Bipolar Power Devices

� Pin diodes, Bipolar Junction Transistor (BJT), Insulated-Gate Bipolar Transistor (IGBT), and thyristors.

� Advantages of bipolar power devices:� Low on-resistance due to conductivity modulation� High temperature operation (without critical oxide layer)

� Status of 4H-SiC bipolar power devices:� Pin diodes: VF<3.5V @ 100 A/cm2; VB = 19.2 kV� BJT: β=10~120; BVCEO≤9.2 kV

� IGBT: 20kV p-IGBT, 31 A/cm2 @ 300 W/cm2


Material Issues in 4H-SiC Bipolar Power Devices

Ni

N+ 4H-SiC substrate

N+ buffer layer

N- drift layerND ~ low 10 14 cm -3

AuTi/Al

P+ anode

4H-SiC pin diode

High Breakdown

VoltageLow Specific

On-resistance

High ReliabilityLow Forward Voltage Drift

Low Basal Plane

Dislocation Density

Thickness & Doping

Low defect densitiesHigh Minority

Carrier Lifetime


Horizontal Hot-wall SiC CVD Reactor

To pump

Quartz tubeRF coil

Gas outletPyrometer

SiC substrate

Thermal insulation

Graphite susceptor

Horizontal hot-wall SiC CVD system

Thermal insulation

� Temperature: ~1600oC

� Pressure: 50~150 mbar

� Precursor gases:

� SiH4 (5% in H2)

� pure C3H8

� Carrier gas: H2

� N-type doping: N2

� P-type doping:

TMA, B2H6

� Purge gas: Ar

C/Si ratio


4H-SiC CVD Growth Process

4H-SiC CVD growth processTime

H2 +C3H8

Etch

Buffer Layer

N+

Thick Epilayer N-

Heat up

Cool down

~1600oC

1100oC

Temperature

H2

Clean

H2

Etch

SiH4+C3H8+ H2H2 +C3H8

Clean

� Clean-Etch-Growth

� Clean to remove moisture

� H2/C3H8 etch to remove polishing damage

� Highly-doped buffer layer is used to separate active device region from substrate


Growth Modes – 3C Nucleation

� Low step density and long terrace length� Island nucleation of 3C-SiC� High temperature required for homoepitaxy

On-axis or low off-angle substrate


Growth Modes – Step-flow Growth

� high step density and short terrace length� Step-flow growth with stable polytype at lower temperature� Good film quality from “step-controlled epitaxy”

Substrate with larger off-cut angle


Doping Control

0.74N

1.10B-H

0.82B

1.26Al

1.10P

0.77C

1.17Si

Radius (Å)Species

� Site-competition epitaxy:Doping control by adjusting C/Si ratioIncrease C/Si ratio, N: ; Al:

� Other factors:growth pressure

growth temperaturegrowth rate

substrate polarity (C-face/Si-face)

off-cut angle

C

Si

Si

Si

CX

Covalent radii of dopants*

*Data from D. J. Darkin, et. al., Phys. Status Soli di B, 202 p305, 1997


Epitaxy

Substrate

Epitaxy

Substrate

A B C D

EF

Defect Reduction

� Defects propagated from substrate:� A/B : micropipes

� C: threading edge/screw dislocations (TED/TSD);

� D: carrot defects

� E/F: basal plane dislocations

� BPD conversion� Growth conditions: C/Si ratio;

growth rate, off-cut angle

� Pre-growth treatment: KOH etching

Lithographic patterningPropagation of defects from substrate into epilayer


Epilayer Characterization

� Thickness measurement:Fourier transform infrared spectroscopy (FTIR)

� Doping measurement:Mercury probe (C-V), MOSC (C-V)

� Surface morphology characterization:Nomarski microscopy, Atomic force microscopy (AFM)

� Defect etches: Molten KOH etching

(5~10 min at 520 oC)

BPD

TSD

TED

Nomarski micrograph of epilayer surface after 8 min KOH etching


Experimental Results on Epitaxial Growth of 4H-SiC

� Si-face:Effects of different off-cut anglesCarrier lifetimes of epilayers on Si-face

� C-face: Optimization of growth process to minimize defect densities


Growth rate

� Growth rate increases almost linearly with SiH4 flow

� The growth rate is constant for C/Si ratio >1.0, drops at C/Si ratio of 0.5

� The growth rates on 8o sample are larger than those on 4o sample

8o off-angle


Nitrogen Doping

� Nitrogen incorporation decreases with C/Si ratio (site-competition)

� Doping concentrations on 8o sample are slightly higher than those on 4o sample

� Nitrogen incorporation decreases with decreasing growth pressure

8o off-angle


Surface Morphology-Nomarski

� Epilayers on 4o substrate show extensive step-bunching, not on 8o substrates� Large surface defect densities are low on both substrates (less than 10 cm-2 )� Micropipes can be observed on epilayers grown under high C/Si ratio


Surface Morphology-AFM

� Macrosteps on 4o sample have height 10-15 nm, and spacings increase with decreasing C/Si ratio.

� Steps on 8o sample have height less than 0.5 nm and constant spacings

� Step crossover and hillocks on epilayers grown under high C/Si ratio.

10 micron

5 micron


Basal Plane Dislocations

� Molten KOH etch at 520oC for 10 minutes, BPDs are identified as oval-shaped etch pits and marked with white circles.

� BPD density on 4o sample is much lower than that on 8o sample under same C/Si ratio (1.5).

4o off-angle 8o off-angle


Basal Plane Dislocations

� BPD densities decrease with increasing C/Si ratio

� BPD densities are reduced by growing on 4o samples, the lowest BPD densities is 2.6 cm-2 at C/Si ratio of 2.0

� The image force on the BPD near the surface is believed to encourage BPD conversion to TED:


BPD Reduction by Pre-growth Treatments

� Pre-growth treatments: KOH etching; Lithographic patterning

� Disadvantages: more process steps; rough surface after growth (CMP is needed); generate new defects

KOH

etching

Litho

Patterning

7 µm100 µm

KOH 100 µm

30 µm

20 µm

10 µm

200µm

3min


BPD Reduction by Pre-growth Treatments

� BPD densities decrease with increasing KOH etching time up to 5 min.

� The lowest BPD densities with KOH etching technique is 40 cm-2.

� When excessive KOH etching is performed, BPD density increases dramatically.

� BPD densities achieved by patterning technique is around 50 cm-2

Very low BPD densities (< 10 cm-2) can be achieved using multiple KOH etching steps under optimized conditions.


Mechanism for Enhanced BPD conversion

� In the KOH etch pits, the BPD propagation is blocked and converted into TED If lateral growth dominates.

� During the normal growth, small etch pits may be produced during H2etching. Enhanced lateral growth under high C/Si ratio help to promote the BPD conversion under those conditions.

*Z. Zhang, et al., APL 89 , p081910, 2006


Minority Carrier Lifetime Control

� Deep level trap densities:DLTS (deep-level trap spectroscopy)Z1/Z2; EH6/EH7; D-center; Ti

� Lifetime characterization: Electron beam induced current (EBIC) Time-resolved photoluminescence (PL) Pulsed MOS capacitor (C-t) Reverse recovery (RR)

� Growth parameter correlations: C/Si ratio; growth temperature; susceptor purity……

EV+(0.58-0.63)D-center

EC-(0.11-0.17)Ti

EC-(1.60-1.65)EH6/EH7

EC-(0.63-0.68)Z1/Z2

Position in the band gap (eV)

Defect

*Data from J. Zhang, et al., JAP 93, p4708, 2003


Deep-level Traps Densities

� Three deep level traps are detected by DLTS from a Schottky structure

� Concentration of the traps are relatively low, which should correspond to a long minority carrier lifetime

EH6/EH7

DLTS spectrum Arrhenius plot


� DLTS is performed on several sets of samples grown under different C/Si ratios.

� Generally, Z1/Z2 and EH6/EH7 trap densities decrease with C/Si ratio. � Trap densities vary from set to set, indicating other lifetime-limiting factors.

Effects of C/Si Ratio on Deep-level Trap Densities


Lifetime Measurement on n-type epilayer

� Minority carrier diffusion length (Ld) is deduced of EBIC signal. The bulk minority carrier lifetime estimated from Ld is around 1.45 μsec.

� Minority carrier lifetimes of a 182-μm epilayer measured by time-resolved PL is around 1 μsec. This is sufficient for IGBT device applications.

λλλλ =391nm

W1W2

W3

Si Face

1.07µµµµsec

0.72µµµµsec


Experimental Results on Epitaxial Growth of 4H-SiC

� Si-face:Effects of different off-cut angles Carrier lifetimes of epilayers on Si-face

� C-face: Optimization of growth process to minimize defect densities


Why C-face 4H-SiC?

bettergoodStep bunching

difficulteasyP+ doping

difficulteasyn- doping

narrowwideGrowth window

easyhardLow off-angle growth

possibleNot possible

On-axis growth

lowhighBPD density

goodgoodSurface morphology

C-faceSi-facePARAMETERS

Comparison of Si-face and C-face

� Epilayers on C-face 4H-SiC show some good properties

� C-face is also suitable for low off-angle and on-axis growth

� Narrow growth window and difficulties in controlling doping limit C-face device applications

� N-type C-face epitaxial growth on 4o off-angle substrate will be discussed in this work


C-face Epilayers by Standard Growth Process

C/Si ratio=2.0, 1600oC 2 µm buffer + 10µm epilayer

VS

C-face Si-face

C/Si ratio=2.0, 1600oC 5 µm buffer + 40µm epilayer

Surface morphology of C-face epilayers is much worse than that of Si-face epilayers if the same standard growth process is used.

200µm


Surface Morphology under different N2 flow and C/Si ratios

� Under high N2 flow, surface starts to deteriorate at C/Si ratio of 2.0. Triangular pits are aligned perpendicular to the off-cut direction

� Under low N2 flow, triangular pits start to appear on surface at higher C/Si ratio with density of 10 cm-2 (C/Si=2.0) and 17 cm-2 (C/Si=3.0)

0

2.5 µm

100 µm

50

0

0

2.0 µm

100 µm

50

0

[1120]


Nitrogen-induced Step Bunching

All images are 3 µm× 3µm collected by AFM in tapping mode

-20

-10

0

10

20

0 0.4 0.8 1.2

nm

µm

-2

-1

0

1

2

0.0 0.2 0.4 0.6

µm

nm

� Macrostep bunching has been observed under high N2 flow conditions. No step bunching is found on samples grown under low N2 flow conditions

� Step-height is about 10~15 nm on samples under high N2 flow; while step-height is about 0.25~0.5nm (1~2 bilayers) on samples under low N2 flow.


Effects of C/Si Ratio on Surface Roughness and Doping Concentration

C/Si ratio

RM

S r

ough

ness

(nm

)

0.1

1.0

10.0

0 1 2 3 4

N2: 1800 sccmN2: 0.037 sccm

� Surface roughness is about one order of magnitude higher for high N2 flow condition. RMS increases with C/Si ratios for heavily-doped samples.

� “Site-competition” effect has been observed on the lightly-doped epilayers, but not on the heavily-doped epilayers.

0 1 2 3 4

N2: 1800 sccmN2: 0.037 sccm

1020

1018

1016

1014

1022

C/Si ratio

Dop

ing

Con

cent

ratio

n (c

m-3

)

SIMS

C-V


� Surface roughness decreases with N2 flow. Step-bunching can be significantly reduced with proper N2 flow setting.

� Doping concentration under high N2 flow condition decreases only slightly with N2 flow.

0.0

0.1

1.0

10.0

-500 0 500 1000 1500 2000

C/Si atio=1.0

Nitrogen Flow (sccm)

RM

S r

ough

ness

(nm

)

Effects of N2 flow on Surface Roughness and Doping Concentration

Nitrogen Flow (sccm)

Dop

ing

Con

cent

ratio

n (c

m-3

)

0 500 1000 1500 2000 2500

C/Si ratio=1.0

1019

1018

1020

SIMS


Effect of Growth Temperature on Defect Densities

Growth Pits

1600oC

1620oC

1640oC

Triangular defect

� Shallow growth pit densities increase with growth temperature, while the triangular pit densities decrease.

� The optimum growth temperature is around 1620oC.

C/Si ratio=2.0, N2: 0.037 sccm

200µm

1E-01

1E+00

1E+01

1E+02

1E+03

1E+04

1E+05

1600 1620 1640

Growth Pit

Triagular Pit

Def

ect D

ensi

ties

(cm

-2)

Growth Temperature

3017

580

50

10

0.7

0


Modified C-face Epitaxial growth process

� Grow buffer layer at lower C/Si ratio under proper N2 flow condition.

� Grow device layer at higher C/Si ratio to obtain low doping concentration.

� Grow at optimum growth temperature to minimize both the triangular defects and growth pits.

Buffer layer C/Si ratio=1.0; High N 2 flow (~500 sccm)

C-face 4H-SiC substrate

Device layer C/Si ratio>2.0; Low N 2 flow

Temperature=1620 oC


High-voltage Pin Diodes Fabrication

N+ 4H-SiC Substrate

N+ buffer layer


Ni

Ti/Al

P+

Ni

N+ 4H-SiC Substrate

N+ buffer layer


Ti/Al

P+

Au

Forward operation of the 4H-SiC pin diodes will be discussed with an emphasis on forward voltage degradation issue.


8o Pin Diodes – Forward Characteristics

� VF at 100 A/cm2 is 4.1 V for 100-micron diameter device, and VF increase with device size.

� The diodes exhibit an ideality factor of 2.0 in the low current region.


Forward Voltage Stressing on 8o

off-angle Substrates

� VF at 100 A/cm2 increases from 4.1 V to 5.8 V after 34 hours of stressing at 100 A/cm2.

� VF drifts for a period of time, and then stabilizes during the test.


Forward Voltage Drift on 8o

off-angle Substrate

� Larger devices (0.5mm2) are stressed at 100 A/cm2 for 2 hours cross the wafer.

� The averaged VF drifts over ten diodes is about 4 V.

� The largest drift measured is about

12 V.


Forward Voltage Instability

� Light emission microscopy (LEM) is used to monitor the motion ofstacking fault (SF).

� SF is nucleated at BDP and expand under the forward bias.

1mA, 2sec100mA, 4sec300mA, 4sec500mA, 5sec

Si (g)

Si (g)

C (g)

C (g)

Nucleation site

*M. Skowronski, et al., JAP 92 (8), p4699, 2002


4o Pin Diodes – Forward Characteristics

� PiN diodes are built on 50 µm thick 4o off-angle epilayer with doping of 6.0×1014 cm-3 grown under C/Si ratio of 2.0.

� VF at 100 A/cm2 is 3.3 V for 100-micron diameter device, and VF increase with device size.

� The diodes exhibit an ideality factor of 1.7 in the low current region.


Forward Voltage Stressing on 4o

off-angle Substrates

� VF at 100 A/cm2 drops from 3.49 V to 3.45 V after 22 hours of stressing at 100 A/cm2 due to the heating effect during the stress.

� After cooling, VF drifts is measured to be about 50 mV for this diode.


� Larger devices (0.5mm2) are stressed at 100 A/cm2 for 2 hours cross the wafer.

� The averaged VF drifts over ten diodes is less than 100mV.

� The largest drift measured is only

300 mV.

Forward Voltage Drift on 4o

off-angle Substrate


Conclusions: SiC Epitaxy� A thorough study of epilayers grown on substrates with different off-cut

angle is performed for the first time. High quality Si-face 4H-SiC epilayers with low defect densities : surface defect densities < 10 cm-2, BPD density ~2.6 cm-2 (4o substrate).

� A detailed investigation of epitaxial growth on 4o off-angle C-face 4H-SiC is performed for the first time. C-face epilayers with low surface defect densities are grown under optimized growth conditions.

� High purity Si-face 4H-SiC n-type thick epilayers with low deep level trap densities and long carrier lifetime (~1 μμμμsec). Correlation between deep level trap densities and C/Si ratio is established.

� Thick epilayer with thickness of 182 μμμμm, m, m, m, doping of 1x1014 cm -3 and high minority carrier lifetime is grown at Purdue and is being used for n-channel IGBT fabrication.

� Pin diode with VF of 3.3 V at 100 A/cm2 and minimal forward voltage drift (<100 mV) is demonstrated on low off-angle epilayers for the first time.


MOS Channel Mobility: Background

• MOS inversion layer mobility in 4H-SiC is low (typically ~10 - 20 cm2/Vs)

• 4H-SiC exhibits a high density of interface states in the upper half of the bandgap

• Post-oxidation annealing in nitric oxide (NO) can reduce DIT and increase µEFF


Interface State Density on SiC

10 11

10 12

10 13

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Inte

rfac

e S

tate

Den

sity

(eV

-1 c

m-2

)

E - Ev (eV)

EC

(4H)

Measured onP-Type SiC

Measured onN-Type SiC

6H-SiC

4H-SiC

6H-SiC

4H-SiC

EC

(6H)

(0001)Silicon Face


Interface States and MOS Mobility

EC

EFEV

EF

VG

Distribution ofinterface statesacross the bandgap

Oxide 4H-SiCMetal

Large negative chargetrapped in interface states

Few electrons inthe inversion layer


Effect of Interface States

EC

EF

EVVG

Oxide 4H-SiCMetal

EC

EF

EV

VG

Oxide 4H-SiCMetal

Room Temperature High Temperature

Ei - EF largeEi - EF large Ei - EF smallEi - EF small


Effect of Nitric Oxide POA on DIT

10 11

10 12

10 13

0.00.20.40.60.81.0

Inte

rfac

e S

tate

Den

sity

(eV

-1 c

m-2

)

EC

- E (eV)

Wet Ox

H2 Burn

LPCVD

Dry Ox

ONO

LPCVD

Wet Ox

H2 Burn

Sampleswithout POA

4H-SiC4H-SiC

NO

NH3

NO

NO

NH3

NO

Samples withNitric Oxide POA

Inte

rfac

e S

tate

Den

sity

(eV

-1cm

-2)

Michael A. CapanoMichael A. CapanoMichael A. CapanoMichael A. CapanoPurdue, ECEPurdue, ECEPurdue, ECEPurdue, ECE

Oxidation Schedule

150 m

30 m

15 m

120 m

30 m

Wet O2

(Pyrogenic)Ar Wet O2

(Pyrogenic)

30 m

1150 °C

950 °C

850 °C

H2:O2=6:5 H2O:O2=3:1

unload

(optional) NO Anneal, 1175 °C, 2 hr.(flow rate 0.5 L / min.)

(optional) NO Anneal, 1175 °C, 2 hr.(flow rate 0.5 L / min.)

load


Basic MOSFET Equations

))(1( 20

DSoxVVG

Dm V

LW

CVI

gTG

=∂∂=

−+θµ

)( DSTGoxD VVVL

WCI −=

EFFµµµµ

)(10

VV TG −−−−++++θθθθµµµµ

��

)(0 TGDSox

m

D VVVL

WC

g

I−= µ


Parameter Extraction

VT VG

ID/gm1/2

DSox VL

WC0µµµµ

)(0 TGDSox

m

D VVVL

WC

g

I−= µµµµ


Temperature Dependence of ID / gm

Without NO Anneal

0.0000

0.0005

0.0010

0.0015

0.0020

0.0025

2 4 6 8 10 12 14

Gate Voltage (V)

18 °C

352 °C

56 °C

102 °C

169 °C

Increasing T

I D / g m

1/2

EC

EF

EVVG

Ei - EF largeEi - EF large

EC

EF

EV

VG

Ei - EF smallEi - EF small


0.000

0.001

0.002

0.003

0.004

0.005

0.006

-2 0 2 4 6 8 10 12 14

With NO Anneal

I D / g m

1/2 19 C

344 C

Gate Voltage (V)

0.0000

0.0005

0.0010

0.0015

0.0020

0.0025

2 4 6 8 10 12 14

Without NO Anneal

I D / g m

1/2

18 C

352 C

Gate Voltage (V)

Effect of NO Anneal

)(0 TGDSox

m

D VVVL

WC

g

I−= µµµµ


Effective Mobility (µEFF)

0

10

20

30

40

50

60

70

80

-2 0 2 4 6 8 10 12 14

Gate Voltage (V)

Effe

ctiv

eM

obili

ty (

cm

2 /V

s)

With NO Anneal

19 C

344 C

0

5

10

15

20

25

30

4 6 8 10 12 14

Gate Voltage (V)

Effe

ctiv

e M

obili

ty (

cm 2

/Vs)

Without NO Anneal

18 C

56 C

352 C

211 C

µEFF = µµµµ0 / [1+θθθθ(VG - VT)]


Field-Effect Mobility (µFE)

010203040

50607080

-2 0 2 4 6 8 10 12 14

Gate Voltage (V)

Fie

ld-E

ffect

Mob

ility

(cm

2 /V

s) With NO Anneal

19 C

344 C

0

5

10

15

20

25

2 4 6 8 10 12 14

Gate Voltage (V)

Fie

ld-E

ffect

Mob

ility

(cm

2 /V

s) Without NO Anneal

18 C

344 C

169 C


Effe

ctiv

e M

obili

ty (

cm 2

/Vs)

0

10

20

30

40

50

60

70

-2 0 2 4 6 8 10 12 14

Measured

Gate Voltage (V)

µ0

VT


Parameters for Effective Mobility


Zero-Field Mobility (µ0)

35

40

45

50

55

60

65

0 100 200 300 400

Temperature (°C)Z

ero-

Fie

ld M

obili

ty (

cm2 /

Vs)

With NO Anneal

0

5

10

15

20

25

0 100 200 300 400

Temperature (°C)

Zer

o-F

ield

Mob

ility

(cm

2 /V

s)

Without NO Anneal



Threshold Voltage (VT)

Temperature (°C)T

hres

hold

Vol

tage

(V

)

With NO Anneal

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

0 100 200 300 400

Temperature (°C)

Thr

esho

ld V

olta

ge (

V)

Without NO Anneal

3

4

5

6

7

8

9

10

0 100 200 300 400



Mobility Parametersfor NO-Annealed Samples

µ0 = 48.5 + 0.191 T - 1.15x10-3T2 + 1.58x10-6T3

VT = 0.882 - 0.0148 T + 4.62x10-5T2 - 5.02x10-8T3

θθθθ = 0.0233 - 1.92x10-5T + 1.11x10-7T2 - 2.75x10-10T3

where T is temperature in Celsius and 20 < T < 350



Comparison for NO Annealed FETs

0

10

20

30

40

50

60

70

80

-2 0 2 4 6 8 10 12 14

Gate Voltage (V)

Effe

ctiv

eM

obili

ty (

cm 2 /

Vs)

Measured Mobility

19 C

344 C

0

10

20

30

40

50

60

70

80

-2 0 2 4 6 8 10 12 14

Gate Voltage (V)E

ffect

ive

Mob

ility

(cm

2 /V

s)

Mobility from Equations

19 C

344 C



Conclusions

• We have characterized the temperature dependence of MOSFET mobility in 4H-SiC

• Post-oxidation annealing in NO...- reduces interface state density- reduces threshold voltage

- reduces temperature dependence- increases mobility


Matrix of Experiments

A B

E F

C D

YPoly

Metal

1200 C, Ar

1400 CPillbox

Post-Ox Anneal

(none) NO

Gat

e M

ater

ial

Impl

ant A

nnea

l

AuburnPurdue

Oxidation Procedure

X

ZW

NO


Experimental Comparisons

• Effect of S/D implant activation anneal

• Effect of gate oxidation procedure (AU vs PU)

• Effect of post-oxidation anneal in NO

• Effect of gate material (poly vs metal)

• Effect of ohmic contact anneal

• Effect of E-beam metal evaporation


Measurement Techniques

• “Constant Voltage” Technique-- Hold VDS constant at ~ 50 mV-- Measure ID vs VG-- Mobility is erroneous if S/D are non-ohmic

• “Constant Current” Technique (NEW)-- Hold ID constant at 10, 50, or 90 nA-- Measure VDS vs VG -- Eliminates effect of non-ohmic S/D contacts


0

5

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25

30

35

40

0 5 10 15 20M

obili

ty (

cm2/V

s)

Gate Voltage (V)

Sample B: 4H-SiC N-MOSFETImplant Anneal :1200 C, ArOxide: Auburn Wet Ox + ReOxOxide Anneal: NOGate: PolyContact Anneal: 850 C

0

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0 5 10 15 20

Mob

ility

(cm

2/V

s)

Gate Voltage (V)

Sample B: 4H-SiC N-MOSFETImplant Anneal :1200 C, ArOxide: Auburn Wet Ox + ReOxOxide Anneal: NOGate: PolyContact Anneal: none

Comparison of Measurement Techniques

MOSFET sample B before ohmic contact anneal.The S/D contacts are non-ohmic, and the constantvoltage technique measures an artificially lowmobility.

MOSFET sample B after ohmic contact anneal.The S/D contacts are now ohmic, and the constantvoltage technique measures a much highermobility.

Before Contact AnnealBefore Contact Anneal After Contact AnnealAfter Contact Anneal


Notes on Subsequent Mobility Plots

• On all subsequent plots, mobility is measured by thenew “constant current” technique.

• In the constant current mobility plots, each data pointis derived from measurements on 5 - 8 MOSFETsat each of four channel lengths (80, 100, 120, and

140 µm), for a total of 20 - 32 MOSFETs.

• Each plot consists of two curves measured at draincurrents of 50 and 90 nA, respectively. The mobilitydetermined at 50 nA is plotted as solid symbols andthe mobility at 90 nA is plotted as open symbols.


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0 5 10 15 20M

obili

ty (

cm2/V

s)

Gate Voltage (V)

Samples E & F: 4H-SiC N-MOSFETImplant Anneal :1400 C, pillboxOxide: Auburn Wet Ox + ReOxGate: PolyContact Anneal: 850 C

E: w/o NO anneal

F: with NO anneal

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Mob

ility

(cm

2/V

s)

Gate Voltage (V)

Samples A & B: 4H-SiC N-MOSFETImplant Anneal :1200 C, ArOxide: Auburn Wet Ox + ReOxGate: PolyContact Anneal: 850 C

A: w/o NO anneal

B: with NO anneal

1: Effect of Post-Oxidation NO Annealing

MOSFET samples without NO annealing (A) andwith NO annealing (B). The implant is annealed at1200 C in Ar. Ohmic contacts are annealed at850 C. The improvement in mobility is obvious.

MOSFET samples without NO annealing (E) andwith NO annealing (F). The implant is annealed at1400 C in a SiC pillbox. Ohmic contacts are annealed at 850 C. The improvement in mobility is obvious.

1200 C Implant Anneal1200 C Implant Anneal 1400 C Implant Anneal1400 C Implant Anneal


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0 5 10 15 20M

obili

ty (

cm2/V

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Gate Voltage (V)

Samples B & F: 4H-SiC N-MOSFETOxide: Auburn Wet Ox + ReOxOxide Anneal: NOGate: PolyContact Anneal: 850 C

F: 1400 CSiC Pillbox

B: 1200 C, Ar

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0 5 10 15 20

Mob

ility

(cm

2/V

s)

Gate Voltage (V)

Samples B & F: 4H-SiC N-MOSFETOxide: Auburn Wet Ox + ReOxOxide Anneal: NOGate: PolyContact Anneal: none

F: 1400 CSiC Pillbox

B: 1200 C, Ar

2: Effect of Implant Anneal Conditions

MOSFET sample B (annealed at 1200 C in Ar) andF (annealed at 1400 C in a SiC pilbox) before contactannealing. The sample annealed at 1200 C hasslightly higher mobility.

MOSFET sample B (annealed at 1200 C in Ar) andF (annealed at 1400 C in a SiC pilbox) after contactannealing at 850 C. The mobility of the 1400 Csample is improved slightly by contact annealing butthe mobility of the 1200 C sample is unchanged.

Before Contact AnnealBefore Contact Anneal After Contact AnnealAfter Contact Anneal


0

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0 5 10 15 20M

obili

ty (

cm2/V

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Gate Voltage (V)

Sample F: 4H-SiC N-MOSFETImplant Anneal :1400 C, pillboxOxide: Auburn Wet Ox + ReOxOxide Anneal: NOGate: Poly

After Contact Anneal

BeforeContact Anneal

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Mob

ility

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Gate Voltage (V)

Sample B: 4H-SiC N-MOSFETImplant Anneal :1200 C, ArOxide: Auburn Wet Ox + ReOxOxide Anneal: NOGate: Poly

After Contact Anneal

Before Contact Anneal

3: Effect of Ohmic Contact Anneal

MOSFET sample B before contact anneal andafter contact anneal. The implant is annealed at1200 C in Ar and the oxide is annealed in NO.Very little change in mobility is observed.

MOSFET sample F before contact anneal andafter contact anneal. The implant is annealed at1400 C in a SiC pillbox and the oxide is annealedin NO. The mobility is improved slightly by the850 C contact anneal.

1200 C Implant Anneal1200 C Implant Anneal 1400 C Implant Anneal1400 C Implant Anneal


4: Effect of Gate Material

MOSFET samples D (Mo gate) and F (poly gate). The implant is annealed at1400 C in a SiC pillbox. Ohmic contacts are annealed at 850 C. Very littlechange in mobility is observed.

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Mob

ility

(cm

2/V

s)

Gate Voltage (V)

Samples D & F: 4H-SiC N-MOSFETImplant Anneal :1400 C, pillboxOxide: Auburn Wet Ox + ReOxOxide Anneal: NOContact Anneal: 850 C

Poly Gate

Metal (Mo) Gate


5: Effect of Gate Oxide Procedure

MOSFET samples A, B, E, and F are oxidized at Auburn and W, X, Y, and Z are oxidized at Purdue. SamplesA, B, E, and F are fabricated on the same wafer, and samples W, X,Y, and Z are fabricated on a different wafer.Samples A, B, X, and Y are implant annealed at 1200 C in Ar. Samples E and F are implant annealed at 1400 Cin a SiC pillbox, and samples W and Z are implant annealed at 1400 C in Ar. Samples B, F, W, and X are NOannealed at Auburn. All have poly gates fabricated at Purdue, and all received an 850 C ohmic contact anneal invacuum at Purdue. The samples oxidized at Purdue appear to have higher mobility, especially at low gate voltage.

0

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0 5 10 15 20M

obili

ty (

cm2/V

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Gate Voltage (V)

Samples W, X, Y, Z: 4H-SiC N-MOSFETImplant Anneal :1200 C & 1400 C, ArOxide: Purdue Wet Ox + ReOxGate: PolyContact Anneal: 850 C

W: 1400 C impl. ann.and NO anneal

X: 1200 C impl. ann.and NO anneal

Y: 1200 C impl. ann.

Z: 1400 C impl. ann.

Auburn OxidationAuburn Oxidation Purdue Oxidation Purdue Oxidation

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Mob

ility

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Gate Voltage (V)

Samples A, B, E, F: 4H-SiC N-MOSFETImplant Anneal :1200 C & 1400 C, ArOxide: Auburn Wet Ox + ReOxGate: PolyContact Anneal: 850 C

F: 1400 C impl. ann.and NO anneal

B: 1200 C impl. ann.and NO anneal

A: 1200 C impl. ann.E: 1400 C impl. ann.


6: Effect of E-Beam Evaporation

MOSFET sample F before and after E-beam evaporation of Ni. The original Ni ohmic contacts were deposited by sputtering. The implant is annealed at 1400 C in a SiC pillbox and the oxide is annealed in NO. The mobility is not affected by E-beam evaporation.

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ility

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Gate Voltage (V)

Sample F: 4H-SiC N-MOSFETImplant Anneal :1400 C, pillboxOxide: Auburn Wet Ox + ReOxOxide Anneal: NOGate: PolyContact Anneal: 850 C

Before E-beamNi Evap.

After E-beamNi evap.


Conclusions

Effect of post-oxidation anneals in NO

• NO annealing increases the mobility by about afactor of five (from ~ 5 to ~ 30 cm2/Vs) (c.f. plot 1).

Effect of gate oxidation procedure (AU vs PU)

• Purdue oxides have higher mobility than Auburnoxides at low gate fields. Both oxides are improvedsignificantly by post-oxidation NO annealing (c.f. plot 5).


Conclusions (Cont’d)

Effect of S/D implant anneal conditions

• The mobility of Auburn oxides is slightly higherwhen the implant is annealed at 1200 C in Ar,compared to 1400 C in a pillbox (c.f. plot 2).

• The mobility of Purdue oxides is slightly higherwhen the implant is annealed at 1400 C in Ar,compared to 1200 C in Ar (c.f. plot 5).


Effect of ohmic contact anneal

• On samples that are implant annealed at 1200 Cin Ar, the ohmic contact anneal has no effect onmobility (c.f. plot 3).

• On samples that are implant annealed at 1400 Cin a SiC pillbox, an ohmic contact anneal at 850 Cimproves the mobility slightly (c.f. plot 3).



Effect of gate material (metal vs poly)

• Gate material (Mo vs polysilicon) has no effect onMOSFET mobility (c.f. plot 4).

Effect of E-beam evaporation of ohmic contacts

• E-beam evaporation has no effect on MOSFET mobility(c.f. plot 6).



Acknowledgement

� James Cooper, Purdue University

� Dr. Robert Stahlbush, Naval Research Lab

� Prof. Marek Skowronski’s group, Carnegie Mellon University

� Wenzhou Chen, Micron Technologies

� Funding provided by DARPA, ONR and the Indiana 21st Century Fund

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