Silicon Carbide Electronic Device Processing for Power Devices and I.C.s Melissa Spencer, Dept of ECE EMRL Why SiC? SiC devices are needed by DoD and Industry High-temperature, power and frequency electronics Critical future technology to replace silicon microchips EMRL is a device fabrication research laboratory focusing on SiC technology Reactive Ion Etching (RIE) is one of the key manufacturing steps in semiconductor technology SiC 3 rd strongest material, only RIE can etch it to make devices Reactive Ion Etching RF energy strikes a plasma which etches the SiC material Plasma Chemistry Etch: SF 6 +He, H 2, O 2 Ash: O 2 RF Power W typicalPressure mT These SiC samples were etched using our RIE process Etched Devices* *G. E. Carter, J. B. Casady, M. Okhuysen, J. D. Scofield, and S. E. Saddow, ICSCRM99 Problem Changes in plasma dielectric constant, P, plasma impedance, Z P, variation This changes the RF power transfer to the plasma P in = P reflected + P plasma The etch rate is a sensitive function of P plasma Manual impedance matching makes the etching process highly operator dependent Therefore RIE process variations unavoidable RIE Etch Rate SEMICONDUCTOR DEVICE CROSS-SECTION Each one of these layers are very thin so etching is critical! RIE etch rate recipes are critical in forming devices Devices are fabricated by forming, patterning, and etching layers Each layer must be precisely etched for the device to function properly 2.5 m Each layer is patterned and etched Power Dependence* Etch rate is a sensitive function of plasma power 10 Percent power change 20% etch rate variation *J. Bonds, G. E. Carter, J.B. Casady and J.D. Scofield, Spring MRS Meeting, April 2000 SF 6 :O 2 (5:10 sccm) Pressure = 100 mT Electrode to sample spacing = 25.4 cm Power (W) vs Etch rate (A/min) Etch rate (Angstroms/minute) Power (W) Automated RF Tuner Detects load impedance, Z P, changes Automatically matches Z P, making the RIE process more repeatable Allows more precise RIE recipes to be performed Devices with finer features may be fabricated Impedance Matching The load impedance is matched to the source impedance by a T network: X1X2 X3 X1, X2 variable capacitors and X3 variable inductance Control algorithm to minimize P R vs. Z P P Forward P Reflected RF Source =ZS=ZS ZPZP Matching Algorithm Vary Impedance Vary Impedance ? Detect Reflected Power System Block Diagram Monitoring PC Micro- Controller Servo Motor/Driver Servo Motor/Driver Servo Motor/Driver Servo Motor/Driver Servo Motor/Driver Servo Motor/Driver Detection Circuitry for Forward and Reflected Power RF in RF out Goal: Maintain constant power transfer MFJ-962D LAM 9400 Etcher AIXTRON SiC Reactor Multi Wafer SiC Epi Sub-micron lithography Multi Wafer Plasma Etching Multi Wafer PECVD Multi Wafer Metal Deposition Prototyping Systems Production Northrop Grumman GE/Lockheed Martin Component Production Mississippi Small Business SBIRs EMRLEMRL SiC CVD Epi Research Materials Characterization Research Impact Device Design & Fab This project has been a collaborative effort by members of the Emerging Materials Research Laboratory at MSU and would not have been possible without the assistance of the EMRL researchers and staff. Dr. Mazzola and Dr. Casady for their support of this project Janna Bonds and Geoff Carter for their RIE assistance Dr. Donohoe for his help on RF concepts and impedance matching theory Dr. Saddow my project advisor Acknowledgements