[SiC-En-2013-1] Development of a SiC JFET-Based Six-Pack Power Module for a Fully Integrated Inverter

1464 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 3, MARCH 2013

Development of a SiC JFET-Based Six-Pack PowerModule for a Fully Integrated Inverter

Fan Xu, Student Member, IEEE, Timothy J. Han, Member, IEEE, Dong Jiang, Member, IEEE,Leon M. Tolbert, Senior Member, IEEE, Fei (Fred) Wang, Fellow, IEEE, Jim Nagashima, Member, IEEE,

Sung Joon Kim, Srikanth Kulkarni, and Fred Barlow, Senior Member, IEEE

AbstractIn this paper, a fully integrated silicon carbide (SiC)-based six-pack power module is designed and developed. With1200-V, 100-A module rating, each switching element is composedof four paralleled SiC junction gate field-effect transistors (JFETs)with two antiparallel SiC Schottky barrier diodes. The stabilityof the module assembly processes is confirmed with 1000 cycles of40 C to +200 C thermal shock tests with 1.3 C/s tempera-ture change. The static characteristics of the module are evaluatedand the results show 55 m on-state resistance of the phase legat 200 C junction temperature. For switching performances, theexperiments demonstrate that while utilizing a 650-V voltage and60-A current, the module switching loss decreases as the junctiontemperature increases up to 150 C. The test setup over a largetemperature range is also described. Meanwhile, the shoot-throughinfluenced by the SiC JFET internal capacitance as well as packageparasitic inductances are discussed. Additionally, a liquid cooledthree-phase inverter with 22.9 cm 22.4 cm 7.1 cm volume and3.53-kg weight, based on this power module, is designed and devel-oped for electric vehicle and hybrid electric vehicle applications.A conversion efficiency of 98.5% is achieved at 10 kHz switchingfrequency at 5 kW output power. The inverter is evaluated withcoolant temperature up to 95 C successfully.

Index TermsElectric vehicle and hybrid electric vehicle(EV/HEV), SiC junction gate field-effect transistor (JFET), sili-con carbide (SiC) inverter, six-pack power module.

I. INTRODUCTION

THE advent of electric vehicle and hybrid electric vehicle(EV/HEV) brings several challenges to power electronicManuscript received February 15, 2012; revised April 29, 2012; accepted

June 6, 2012. Date of current version October 12, 2012. This work was sup-ported by the Engineering Research Center Program of the National ScienceFoundation (NSF) and the Department of Energy under NSF Award NumberEEC-1041877 and the CURENT Industry Partnership Program. Recommendedfor publication by Associate Editor H.-P. Nee.

F. Xu, L. M. Tolbert, and F. (Fred) Wang are with the Department ofElectrical Engineering and Computer Science, The University of Tennessee atKnoxville, Knoxville, TN 37916 USA (e-mail: [email protected]; [email protected];[email protected]).

T. J. Han, J. Nagashima, and S. J. Kim are with the Global PowerElectronics, Inc., Irvine, CA 92618 USA (e-mail: [email protected];[email protected]; [email protected]).

D. Jiang is with the United Technologies Research Center, East Hartford, CT06118 USA (e-mail: [email protected]).

S. Kulkarni is with Micron Technology Inc., Boise, ID 83716 USA (e-mail:[email protected]).

F. Barlow is with the Department of Electrical and Computer Engineering,University of Idaho, Moscow, ID 83844 USA (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2012.2205946

modules on both power device and packaging technologies, tooperate in a high-temperature environment and minimize weightand volume as well [1], [2]. In the harsh operating conditions,electrical, thermal, and lifetime limitations reduce the reliabilityof traditional Si insulated gate bipolar transistor (IGBT) powerdevices and modules [1][4]. To meet these design challenges,several options are provided in [5], such as the improvement ofthermal management techniques, increasing the Si die area toincrease cooling area, and using soft switching to eliminate losswhich is realized in [6]. Another option is using wide bandgappower semiconductor materials such as silicon carbide (SiC),which shows characteristics superior to conventional Si semi-conductors for high temperature, high power density convertersin EV/HEV [7].

SiC power electronic semiconductors provide high break-down voltage, fast switching, low on-state resistance, and hightemperature tolerance. Meanwhile, SiC has high thermal con-ductivity, which leads to improved power dissipation and higherpower handling capability. Fast switching and low on-state re-sistance increase the efficiency of SiC-based power conver-sion systems, and reduce the requirement of the cooling sys-tem. High junction temperature capability helps SiC devicesto work in a high-temperature environment. High switchingfrequency leads to the reduction of the number and mass ofinductors [8], [9]. SiC diode is the first commercial SiC powersemiconductor and has been widely used with Si switching de-vices [10][12]. SiC bipolar junction transistor (BJT) has goodperformance for high-voltage and high-temperature application.However, a certain base current in steady state is necessary todrive BJT which causes high driving power [13], [14]. SiCMOSFET and SiC junction gate field-effect transistor (JFET)have been improved through the years and have been commer-cialized. Research on the application of SiC MOSFETs andSiC MOSFET-based power module are presented in [15][19].However, the modules cannot operate above 200 C, due tothe SiC MOSFET inherent oxide interface issues at high tem-peratures [20][22]. Even though some of the SiC MOSFETsoperating above 200 C have been demonstrated [23], [24], thedata concerning their reliability are not provided. SiC JFETsdo not have any interface issues and are considered good can-didates for SiC-controlled switches. Many publications havepresented SiC JFET-based power module and power conversionsystems [25][29] in recent years. In [25], the SiC JFET hasbeen pushed to extremely high ambient temperatures, 450 C.However, the JFET drain current Ids decreases significantlywith rising temperature [25], and thermal runaway is a potential

0885-8993/$31.00 2012 IEEE

XU et al.: DEVELOPMENT OF A SiC JFET-BASED SIX-PACK POWER MODULE FOR A FULLY INTEGRATED INVERTER 1465

Fig. 1. Six-pack SiC JFET-based power module.

threat when the power devices operation temperature is higherthan its allowable limit [7], [30], [31]. Most of the published SiCJFET power modules are single phase-leg modules [26], [27].The modules in [28] and [29] are three-phase modules, but thepower rating of them is 4 kW. Therefore, high-power, high-density SiC JFET-based three-phase power modules with highoperating temperature capabilities still need to be developed,for the tough operating conditions in EV/HEV applications. Inaddition, some issues of SiC JFET-based power module, suchas packaging technologies and phase-leg shoot-through duringfast switching [32], need to be solved.

In this paper, a fully integrated SiC-based three-phase powermodule is designed and developed. With 1200-V, 100-A rat-ing of the module, each switching element is composed offour paralleled SiC JFETs with two antiparallel SiC Schottkybarrier diodes (SBDs). The stability of the module assemblyprocesses is confirmed with the thermal shock test. The phase-leg shoot-through issue is analyzed by switching test with a650-V voltage and 60-A current. Additionally, a three-phase in-verter based on this power module is designed and developed forthe EV/HEV applications. This paper is organized as follows:Section II describes the six-pack SiC power module, with itsassembly processes and package parasitics; Section III showsthe static characteristics of the module; the switching test andphase-leg shoot-through discussion are presented in Section IV;in Section V, the three-phase inverter is developed and tested;and finally, Section VI provides conclusions.

II. SIX-PACK ALL-SIC POWER MODULE

A. Module Overview and Layout DesignFig. 1 shows the picture of SiC JFET-based power module

with 1200-V, 100-A power rating. The module size is 140 mm70 mm 12.7 mm. The module consists of a three-phase bridgeconfiguration with each switching element having four 4.17 mm 4.17 mm 1200 V normally-on SiC JFETs and two 2.7 mm 2.7 mm 1200 V SiC SBDs from SiCED in parallel.

Each phase leg is designed in a separate substrate, 38.5 mm 38.5 mm. Fig. 2(a) shows the phase-leg circuit. The basic

Fig. 2. Phase-leg structure of six-pack SiC power module. (a) Phase-leg cir-cuit. (b) Phase-leg layout. (c) Phase-leg picture.

switching cell theory proposed in [33] is used during the phase-leg layout design. As shown in Fig. 2(b), the devices in the com-mutation loop are placed at the same side. Thus, the physicallength of the commutation loop is specifically reduced com-pared with conventional module layout, in which the JFET andits antiparallel diode are seated at one side. This layout design


TABLE IPARASITIC INDUCTANCES OF THE THREE-PHASE SiC POWER MODULE

leads to the reduction of parasitic inductance in natural currentcommutation path. The gate loop layout, shown in Fig. 2(b),is composed of two control pins placed between the two closerJFETs to make the distance evenly distributed among four paral-leled JFETs. This step is necessary in order to balance gate loopparasitics in the module. Fig. 2(c) shows the phase-leg picture.

The package parasitics of the module are extracted byMaxwell Q3D parameter extractor [34], and the values of par-asitic inductances are listed in Table I, which come from theL matrix extracted by Q3D ac analysis at 100 MHz operatingfrequency, with a 1% margin of error. The common source in-ductance is the parasitic inductance shared by the JFET gate loopand the main loop, and the source inductance is the JFET source-side parasitic inductance only in the main loop. The gate loopinductance value of each JFET includes the inductance sharedby four paralleled JFETs, called common gate inductance, andthe inductance only in each JFET gate loop. The common gateinductance includes the mutual couplings of paralleled JFETsgate loops, which are important for paralleled devices switchingbehaviors [35].

B. Package DesignThe package of the module is designed to work at a junction

temperature of at least 200 C. The components and manufac-turing processes that have been used can be broken down intoseveral key pieces: die-attach, wire bonding, substrates, andhousing/encapsulation. The SiC JFETs and SBDs are bonded tothe active metal bonding Cu [36], [37] on Si3N4 substrates withlead-based solder that melts at a temperature of 310 C. The sol-der and substrate are selected since they have been demonstratedin prior work to be stable when used continuously at 200 C,and survive thousands of thermal shock cycles from 40 Cto + 200 C [38][40]. The die bonding is done in a fluxlessprocess with the aid of a vacuum soldering furnace. The sourceand gate connections for the JFETs and SBDs connections areformed using 99.99% pure 5-mil diameter Al wire bonds. Inorder to avoid very long gate wire bonds, the thin film Al onceramic or glass ceramic shunts are used. The metallization onthese substrates is designed, in that the trace width is narrowso as to minimize the parasitic capacitive coupling to the metal

trace below the low-temperature co-fired ceramic. To form thecomplete three-phase inverter, three substrates are bonded to aNi-plated Cu molybdenum alloy base plate and connected inparallel by connecting the substrates to common +dc and dcterminals. To sample the source voltages and control the gate-source voltages Vgs , Au over Ni-plated brass control pins isbonded to the metal traces on the direct bond copper substrates.The pins are bonded with the lead-based solder that is used fordie bonding. The housing is mounted on the baseplate that ismachined from a glass-filled polyimide material, torlon 5030.The housing is used to support the busbars, Ni-plated Cu, andcontain the encapsulation gel, Nusil Gel 8100, during the cur-ing process. Again, these materials are chosen since they arestable and reliable when used at these temperatures [41], [42].All switching components and interconnects are isolated fromthe heat sink baseplate. For simplifying system assembly andthermal management, the interconnection to the dc voltage inputterminals and the phase-leg output terminals are assigned as ascrew terminal type. The module also includes three thermistorsto monitor the substrate temperature.

Stresses in the die-attach interface during operation are simu-lated by thermal shock testing (TST) by cycling 54 samples be-tween40 C and 200 C, as shown in Fig. 3(a). This set of TSTconditions corresponds to a rate of temperature change (dT/dt)of 1.3 C/s. To evaluate potential metallurgical issues, another54 die-attach samples are subject to high temperature storage(HTS) test at 200 C. The TST on the samples is performed fora maximum of 1000 cycles and the HTS is performed for a max-imum of 1000 h. HTS and TST are chosen since the HTS testreveals direct temperature effects such as diffusion or decompo-sition of polymeric materials, while the TST reveals damage dueto effects such as expansion- and contraction-induced mechani-cal stresses. These test conditions are somewhat arbitrary sincethere is no published automotive specification for this temper-ature range when these tests begin. Therefore, the researchersadopt this standard based on reviewing a number of automo-tive and former mil-spec standards as representative of whatwould commonly be used in a variety of applications. Someapplication may require more cycles and some may requirefewer; however, these test conditions are a reasonable com-promise. From the tests, it is observed that high lead contentsolders show very reliable die-attach interfaces after the TSTand HTS. This observation is based on the fact that the shearstrength of the lead-based die-soldering material shows statisti-cally insignificant drop after TST or HTS, as shown in Fig. 3(b)and (c).

Fig. 4 shows the observed change in the pull strength ofthe wire bonds in both control and encapsulated samples. It isobserved from the control samples that the wire pull strengthdrops significantly with the increased number of temperaturecycles. From the encapsulated samples, the drop in the pullstrength of the wires is greater than that in the control sam-ples. This is likely due to the fact that the gel itself has a veryhigh coefficient of thermal expansion (CTE), and although ithas a low modulus, it exerts some small amount of force onthe wires. However, the pull strengths of the wire bonds in theencapsulated samples are still greater than the minimum preseal


Fig. 3. Thermal profile and shear test results for solder die-attach samples. (a)Thermal shock cycle profile. (b) Shear strength during 1000 cycles. (c) Shearstrength during 1000 h.

Fig. 4. Pull strength of wire bonds plotted versus number of shock cycles from40 C to 200 C.

wire pull strength at the end of the 1000 cycles, as specified inMIL-STD 883. This finding is relevant to module constructionsince it would potentially enable alternative methods for pro-viding isolation in the module that do not require encapsulatinggel.

III. STATIC CHARACTERISTICSThe static characteristics of the switching element in the mod-

ule are obtained with a curve tracer at various temperatures from25 C to 200 C, as shown in Fig. 5. In the test, the module isheated with a hot plate with a thermocouple as the temperaturemonitor. The forward characteristics of switching element areobtained at JFET gate-source voltage Vgs of 0 V, as shown inFig. 5(a). Fig. 5(b) shows the forward characteristics at differ-ent Vgs at 200 C. Fig. 5(c) illustrates the transfer characteristicat different temperatures. Since the JFETs are normally-on de-vices, the pinch-off voltage is negative. From Fig. 5(c), thepinch-off voltage is lower with increasing temperatures, from16 V at 25 C to 17 V at 200 C. Fig. 5(d) shows the re-verse characteristics of the switching element measured withthe JFETs blocked by Vgs of22 V, in which both the antiparal-lel diodes and JFET body diodes are considered. The thresholdvoltage Vth decreases with rising temperatures, and the slope ofthe linear region becomes shallower with rising temperatures,which means the series resistance RD of the diode increases.

The measurement of the on-state resistance of the JFET isbased on the slope of the forward characteristic in the linearregion. Fig. 6 shows that the four paralleled SiC JFETs on-stateresistance RJ increases with higher temperature, from 25 mat 25 C to 55 m at 200 C, at 60 A drainsource current Ids ,at Vgs = 0 V. The low on-state resistance and high temperaturetolerance determine the low conduction loss of SiC-based powermodule even at 200 C.

For JFET-based switching cell, when current flows throughdrainsource direction, only RJ conducts current, and the con-duction loss is given in (1). When current flows through sourcedrain direction, the current will flow in two conditions, andwhen current is smaller than a threshold value, only the JFETconducts. When the current exceeds this threshold value, boththe JFETs and the diodes will conduct current [43]. The switch-ing cell equivalent circuit in this mode is shown in Fig. 7, andconduction loss is given as

Pcon = I2RJ (1)

Pcon = I2RJ , I VthRJ

Pcon =VthRJ I + I2RJ RD

RJ + RD, I >

VthRJ

.(2)

From Fig. 5(a) and (d), the reverse diodes start to conductsourcedrain direction current at 36 and 12 A, at 25 C and200 C, respectively. The diodes currents include the currentsflowing through both antiparallel SBDs and JFETs body diodes.Fig. 8(a) and (b) shows the sourcedrain direction current shar-ing between JFETs and diodes at 25 C and 200 C at differentload current levels. Fig. 8(c) and (d) shows the current shar-ing at different temperatures at 20- and 60-A load currents,


Fig. 5. Static characteristics of the switching element in the module.(a) Paralleled SiC JFETs forward characteristic. (b) Paralleled SiC JFETs for-ward characteristic at 200 C. (c) Paralleled SiC JFETs transfer characteristic.(d) Paralleled diodes forward. characteristic.

Fig. 6. On-state resistance of four paralleled SiC JFETs in the module.

Fig. 7. Switching cell equivalent circuit when current flows through sourcedrain direction.

respectively. These figures demonstrate that as the temperatureincreases, the reverse diodes starting conduction current de-creases and the shared current increases. In this SiC JFET-basedpower module, the JFETs channel will conduct more currentthan the reverse diodes even at 200 C, 60 A.

IV. SWITCHING PERFORMANCE EVALUATIONIn this section, the module phase-leg switching behaviors

are evaluated by double pulse test (DPT). The Saber simulationcircuit is based on the phase-leg circuit in Fig. 2(a) with parasiticinductance shown in Table I. In the experiments, the module istested at a 650-V dc bus voltage, 60-A current, and 150 Cjunction temperature. The load is a 1-mH inductor with 7 pFequivalent parallel capacitance.

A. DPT Circuit and Gate DriveFig. 9 shows DPT circuit with gate drive schematic. Both

high-side and low-side switching elements are four paralleledSiC JFETs with two antiparallel SiC SBDs. In the test, the fourhigh-side JFETs are off, and the double pulse signal is appliedto the low-side JFETs gate terminal. As shown in Fig. 10, theload inductor is charged to rated current value at the end of thefirst pulse. When low-side JFETs are turned OFF, load currentcommutates to high-side SBDs. The load current commutatesback to low-side JFETs when they are turned ON during thesecond pulse. The self-heating of the devices is not consideredand the junction temperature is assumed the same as the casetemperature because of the slow thermal time constant comparedto the pulse duration.

Considering JFET pinch-off voltage measured previously,and the devices 25-V gate breakdown voltage, a value of0 V of Vgs is chosen for turn-on and 22 V of Vgs is used for


Fig. 8. Sourcedrain direction current sharing between JFETs and diodes.(a) Current sharing at 25 C at different load current levels. (b) Current sharingat 200 C at different load current levels. (c) Current sharing at different tem-peratures at 20-A load current. (d) Current sharing at different temperatures at60-A load current.

Fig. 9. DPT circuit with gate drive schematic.

Fig. 10. DPT waveforms. (Time: 20 s/div).

TABLE IIMEASUREMENT APPARATUS USED IN MODULE DPT

turn-off. The driver IC in DPT is IXDN409 from IXYS. In thetest, RCD network [44] is used between the gate driver andJFETs to adapt to the different gate characteristics in case ofJFETs paralleling. In Fig. 9, the turn-on resistor is Rg 1 //Rg 2 =4 , and the turn-off resistance is Rg 1 = 10 . The measure-ment apparatuses, which have high bandwidth for switchingmeasurement, are listed in Table II. The propagation delays ofprobes are compensated.

In the test, the shoot-through protection of the phase leg isrealized by an IGBT, which is connected in series with +dc busas shown in Fig. 9. Once the current exceeds the limit, the IGBTwill be turned OFF to separate the phase leg from dc powersupply and protect the module. Fig. 11 shows a photograph ofthe high-temperature testing setup. The module is heated byconnecting to the hot plate. The temperature is monitored by athermocouple, and a fan is used to cool the printed circuit boardand the shunt resistor.


Fig. 11. High temperature switching test setup.

Fig. 12. Switching waveforms at 650 V and 60 A. (a) Turn-on waveforms. (b)Turn-off waveforms.

B. Switching CharacteristicFig. 12(a) and (b) shows the turn-on and turn-off waveforms

of four paralleled SiC JFETs in the module, respectively. Thewaveforms are obtained with a 650-V voltage and 60-A current.

Fig. 13. Switching loss as a function of load current at 650-V dc voltage withdifferent temperatures. (a) Turn-on loss. (b) Turn-off loss.

The turn-on overshoot current is 18 A at 150 C due to thedischarging current of junction capacitance of high-side JFETsbody diodes and antiparallel SBDs. It is verified in [43] thatthe use of SiC SBD, which has no reverse recovery, helps toreduce the turn-on overshoot current. From the comparison ofthe switching waveforms at 25 C and 150 C in Fig. 12, itis observed that the SiC JFETs switch faster at 150 C thanat 25 C. In this paper, the turn-on time ton is defined as thetime from the current rising to 10% of its peak value until thevoltage falls to 10% of the dc voltage value. Similarly, the turn-off time to is defined from the time the current falls to 90%until the voltage rises to 90% of its dc value. At 150 C, tonis 140 ns and to is 170 ns. However, ton is 160 ns and to is220 ns at 25 C. Fast switching leads to low switching loss. Theswitching loss calculation covers the whole switching transient.From the tests, the turn-on loss Eon of four paralleled SiCJFETs in the modules switching element is 3.8 mJ at 25 Cand 3.4 mJ at 150 C. The turn-off loss Eo is 3.6 mJ at 25 Cand 2.9 mJ at 150 C. Fig. 13(a) and (b) shows the Eon andEo as a function of load current at different temperatures,under 650-V dc voltage. Both turn-on and turn-off losses ofSiC JFETs, with antiparallel SiC SBDs in the module, decreasewith the temperature increasing. The switching loss of the SiIGBT, IGW60T120 from Infineon which has the same rating asthis power module, is 9.5 mJ at 25 C and 15.8 mJ at 150 C, at


Fig. 14. JFET structure and package parasitic impact on phase-leg shoot-through. (a) SiC JFET structure. (b) Phase-leg circuit with JFET internal capac-itance and parasitic inductances in gate loop and dc bus, during low-side JFETsturning ON.

600-V voltage and 60-A current [45]. The comparison shows thelow switching loss of SiC JFET-based power module obviously.

C. Discussion on Phase-Leg Shoot-ThroughShoot-through is defined as both high-side and low-side

switches in a phase leg being turned ON at the same time. Itwill cause additional power dissipation in the switching devices,increase losses [46], or even damage devices. Shoot-through ismainly caused by high dv/dt during a switching transient. Thestructure of a SiC JFET, as shown in Fig. 14(a) [47], leads to theexistence of the intrinsic capacitance, as shown in the circuit inFig. 14(b), which is a crucial factor in determining the switch-ing speed. For a normally-on JFET, the capacitor Cgs is chargedduring turn-on transient, and the device will be turned ON afterVgs exceeds the pinch-off voltage. During turn-off transient, Cgswill discharge to reduce Vgs . Even though a JFET is not switch-ing, its drain and source terminal voltages still vary when otherswitches are turning ON and OFF, and the internal capacitanceof it will be charged or discharged due to dv/dt. Since the SiCpower module has a fast switching speed, and the normally-onJFET gate breakdown voltage is only a few volts away from thepinch-off voltage, 25 and 17 V, respectively, the issues ofphase-leg shoot-through need to be addressed.

The package parasitics play significant roles on module elec-trical performances. It is demonstrated in [48] that JFET drainside, source side, and gate loop inductances have significantrole on its switching performance. Furthermore, the existenceof the parasitic inductance may cause shoot-through during fastswitching transient. The key parasitics include gate loop induc-tances and dc bus inductances. The voltage of phase-leg outputterminal drops from 650 to 0 V during low-side JFETs turningON in the test. At this time, the gate loop current ig appears inhigh-side JFETs gate loops because of the existence of JFETinternal capacitance. When ig increases, there is a voltage VLacross parasitic inductance Lg , as shown in Fig. 14(b). Sinceexternal gate voltage VG and Vgs are negative values to turnOFF the normally-on JFET, it is possible that Vgs is larger thanpinch-off voltage if VL is large enough. Fig. 15(a) shows thesimulation results of high-side JFET Vgs and channel currentwith different values of Lg . It is obvious that large Lg in high-side JFET gate loop will cause Vgs of JFET to be larger than itspinch-off voltage. In addition, the JFET internal capacitance willhave a charge current ibus associated with it on the dc bus, andibus will cause a voltage drop Vbus across the dc bus parasiticinductance Lbus , as shown in Fig. 14(b). This effect may alsoresult in shoot-through since it leads to high-side JFETs drainvoltage being higher than dc voltage and therefore increases thedv/dt during switching. Fig. 15(b) shows the simulation resultsof high-side JFET Vgs and channel current with different valuesof Lbus . A large Lbus leads to Vgs being more than the pinch-offvoltage and causes shoot-through as shown in the figure.

In addition, temperature is another factor for phase-leg shoot-through. From Fig. 5(c), the JFET pinch-off voltage decreaseswith the temperature increasing. So, the shoot-through is moresevere at higher temperature because of the reduction of thedifference between JFET turn-off voltage and pinch-off voltage.

Based on the aforementioned analysis, shoot-through can beinfluenced by many factors including the internal capacitance,package parasitic inductances, and operation temperature. Thekey parasitics include parasitic inductances in JFET gate loopand module dc bus. Since the SiC JFET-based power modulesare often operated at higher temperatures, it is more importantto reduce the parasitic inductances in gate loops and dc buses.Due to the simulation results in Fig. 20, the gate loop and dc busparasitic inductance values of the module, listed in Table I, aresmall enough to avoid phase-leg shoot-through at the proposedtest condition.

V. SiC INVERTER DEVELOPMENTBased on the six-pack power module developed and char-

acterized previously, a three-phase inverter is developed forEV/HEV applications, shown in Fig. 16(a). This inverter hasa designed power rating of 30 kW continuous and 50-kW peak.The custom gate driver, shown in Fig. 16(b), contains circuitsfor inherently safe operation of the depletion mode JFETs un-der start-up and fault modes. The dc input consists of metalized94-F polypropylene film capacitors with segmented foilsto provide short-circuit protection. There is an integral in-put LC electromagnetic interference filter to reduce conducted


Fig. 15. Gate loop and dc bus parasitic inductances influence on phase-legshoot-through at 200 C. (a) High-side JFET Vgs and channel current withdifferent Lg . (b) High-side JFET Vgs and channel current with different Lbus .

line currents. The controller is a Texas Instruments PiccoloTMX320F28035 microcontroller-based control card. The inputand output power and signal connections are by keyed twist-lockconnectors for maximum safety and convenience. The inverterspecifications are summarized in Table III. This liquid cooledinverter is 22.9 cm 22.4 cm 7.1 cm in dimension with avolume of 3.6 L, and a weight of 3.53 kg.

A. Gate Driver Circuits With Shoot-Through ProtectionThe SiC JFETs used in the module have a normally-on charac-

teristic, and when they are in the phase-leg with dc-link voltage

Fig. 16. Three-phase SiC inverter prototype. (a) Integrated prototype inverter.(b) Gate driver board integrated on SiC power module.

TABLE IIISiC INVERTER SPECIFICATIONS

active, any failure of gate driver will cause the shoot-through.Thus, an inherently safe gate driver for normally-on JFETs isdeveloped with 12-V dc-link voltage and 60-mA current, asshown in Fig. 17. The circuit uses a linear regulator to developan internal operating voltage, which is positive compared tothe low-side SiC JFETs source, from any voltage applied tothe high voltage bus ranging from 6 to 650 Vdc . The negativegate voltage, which nominally is regulated at 22 V, is cre-ated using a high-speed switching buckboost converter. The


Fig. 17. Schematic diagram of the inherently safe gate bias circuit.

buckboost converter operates with a switching speed in thelow mega Hertz region from a discrete controller that has beendesigned to start up rapidly allowing the negative gate voltageto be generated in less than a couple hundred microseconds.The heart of the buckboost converter is a small inductor of6 mm3which is 2.5 H with a 1-A peak current at 2 MHz, builton a ferrite core. The control circuit regulates the voltage onJFET gate input using a simple start-stop algorithm to minimizecomplexity and component count. The Zener diodes preventvoltage overshoot due to the fast rise time of the negative biasvoltage. An external bias voltage can also be provided for theinherently safe circuit to reduce power dissipation in the linearregulator and to maintain the circuit in a standby mode.

For normal operation, a conventional gate drive IC, InfineonIED02I12-FA, is used, to provide gate voltage of 0/22 V. Theinherently safe bias voltage is presented to the gate of the SiCJFET using a noncontact solid-state switch which is a biased n-p-n transistor. This switch is opened when the conventional gatedrive circuit is operational, and turns off the safe bias controller,removing the load from the linear regulator to prevent unneces-sary power loss. The test results of the safety lockout circuit inthe converter are shown in Fig. 18(a) and (b). The first waveformis the output voltage of the linear regulator. The second and thethird waveforms are oscillator and buckboost output voltages,respectively. From the zoom in waveforms in Fig. 18(b), theoscillation frequency is 1.8 MHz. The last waveform is the gateinput voltage of the SiC JFET. From Fig. 18(a), the startup de-lay to get to pinch-off voltage of 17 V is about 120 s. FromFig. 19, the JFET energy dissipation is about 1 J at 120 s. Sincethe destructive energy of the JFET is 60 J/cm2 [49], 120 s isfast enough to prevent damage even if a very high voltage isinstantaneously applied across the SiC JFETs with no power forthe normal gate drive. The energy dissipated in JFETs is relatedto the value of inductance of the dc busbar and the packageparasitics. According to the inductance values of the module,

Fig. 18. Safety lockout circuit waveforms. (a) Response time of safety lock-out circuit (Time: 20 s/div). (b) Safety lockout circuit performance (Time:200 ns/div).


Fig. 19. Four paralleled SiC JFETs energy dissipation.

Fig. 20. SiC inverter test and efficiency measurement setup.

the JFET energy dissipation is estimated as 250 mJ, until it isturned OFF, because the safety lockout circuits provide negativebiasing to JFET gate input from 0 to 17 V gradually [50].

B. SiC Inverter Test and Efficiency MeasurementThe liquid-cooled SiC inverter is tested with an RL load. As

shown in Fig. 20, the inverter is connected to a dc power supplyand feeds ac power to a three-phase RL load with Y-connection,where R = 10 and L = 1.2 mH. The switches in the inverterare controlled by space vector pulsewidth modulation signalsgenerated by the TMX320F28035 microcontroller board. Thechiller changes the coolant temperature from 25 C to 95 C. Thecoolant flow rate is set at 6.8 L/min with 50% ethylene glycol,50% water at the output of the chiller. The input dc voltage, theinput dc current, the three-phase line-to-line voltage, and theline current are monitored and measured by the oscilloscope,Tektronix DPO7104. The power conversion efficiency and thequality of the inverted ac power are monitored and measuredusing Yokogawa WT3000 Precision Power Analyzer with anaccuracy of 0.02%. For ac side, three-phase three-wire powermeasurement method is used, and dc-side power is obtained bymultiplying dc voltage and current.

Some of the experimental waveforms of line-to-line outputvoltage (Vab and Vbc) and output current (ia and ib ) at coolant

Fig. 21. Experimental waveforms of the SiC inverter at 650 Vdc , f = 60 Hz,M = 0.85 with the RL load, R = 10 and L = 1.2 mH. (Time: 5 ms/div, Vaband Vb c : 700 V/div, ia and ib : 30 A/div). (a) fsw = 10 kHz. (b) fsw = 40 kHz.

temperature of 25 C are shown in Fig. 21. The input voltagein the figure is 650 Vdc . The frequency of the output currentis 60 Hz, and its magnitude is set by a modulation index of0.85. Fig. 21(a) shows the waveforms with 10-kHz switchingfrequency. When the switching frequency is increased to 40 kHz,as Fig. 21(b) shows, the line current is distorted at zero crossingbecause the fixed dead time of 2 s between high-side andlow-side switches is relatively large compared to the switchingperiod 25 s.

The measured temperature difference between the coolantand the thermistor on the substrate inside the module is shownin Fig. 22. The maximum coolant temperature is limited by theoperation temperature of the dc link. The difference betweenthe coolant temperature and the substrate temperature is about4 C and 13 C at 5-kW output power, at fsw = 10 kHz and fsw= 40 kHz, respectively.

As Fig. 23 shows, the inverter efficiencies are measured atup to 11.4-kW output power with different switching frequen-cies from 10 to 40 kHz, at 60-Hz fundamental output frequency,25 C coolant temperature, and 0.85 modulation index. Thepower loss at the gate driver board, which is 5 to 8.5 W depend-ing on the switching frequency, is included in the efficiencymeasurement. The efficiency curves are measured by chang-ing the dc input voltage with the fixed RL load. The maximum


Fig. 22. Measured substrate temperatures at different coolant temperatures at5-kW output power.

Fig. 23. Efficiency of the SiC inverter at 25 C coolant temperature, differentoutput power levels, and switching frequencies.

Fig. 24. Efficiency of the SiC inverter at 10-kHz switching frequency, differentoutput power levels, and coolant temperatures.

98.5% efficiency including the 5-W gate driver power loss isachieved at a switching frequency of 10 kHz at 5-kW outputpower, 450-V dc voltage, with the power factor 0.73.

The inverter conversion efficiencies with different coolanttemperatures at 10-kHz switching frequency are shown in

Fig. 25. Efficiency variation with coolant temperature changes at 5-kW outputpower and different switching frequencies.

Fig. 24. The conversion efficiency degradation at coolant tem-perature of 95 C is less than 0.2% compared to the measureddata at 25 C. Considering the thermal resistance from JFETjunction to inlet coolant of 2.62 C/W, the estimated JFET junc-tion temperature is 113.6 C at 10-kW output power, 10-kHzswitching frequency, and 95 C coolant temperature.

The conversion efficiencies are measured with the differ-ent switching frequencies at fixed 5-kW output power overcoolant temperatures, as shown in Fig. 25. No significant ef-ficiency degradation is observed. When the coolant temperatureincreases at 40-kHz switching frequency, the conversion effi-ciency is improved because the switching loss, which is abouttwo times of the conduction loss [43], reduces at higher junc-tion temperature. The degradation of the efficiency is expectedat higher temperature over 150 C and low switching frequencyrange, because the conduction loss will dominate the switchingloss of SiC JFETs in this operation regime.

VI. CONCLUSIONA SiC JFET-based three-phase inverter power module with

200 C packaging is designed and demonstrated. Each switchingelement consists of four paralleled normally-on SiC JFETs withtwo antiparallel SiC SBDs. Basic switching cell theory is used toreduce package parasitics. The stability of the module assemblyprocesses is confirmed.

The module static characteristics are tested up to 200 C,and the switching performance is evaluated by the DPT up to150 C, at 650-V voltage and 60-A current. In addition, theinfluences of phase-leg shoot-through, including JFET internalcapacitance, package parasitic inductance, and junction temper-ature, are analyzed. The key parasitics are parasitic inductancesin JFET gate loop and module dc bus. The results show the lowloss of SiC JFET-based three-phase power module even at hightemperature, and the increase of conduction loss and decreaseof switching loss with temperature increasing. Meanwhile, thesignificance of shoot-through protection and package parasiticsreduction for the SiC JFET module is pointed out.

A liquid-cooled inverter based on this power module is de-veloped and demonstrated for EV/HEV applications. The safetylockout circuits successfully protects the normally-on JFETsfrom shoot-through by providing a negative bias from dc-link


voltage within the safe power dissipation range. The efficiencyof the inverter is 98.5% at 10-kHz switching frequency at 5-kWoutput power. The inverter was successfully demonstrated at upto 95 C coolant temperature. These show the benefits by usingthe SiC JFET-based power module in EV/HEV applications.

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Fan Xu (S09) received the B.S. and M.S. degreesin electrical engineering from Tsinghua University,Beijing, China, in 2007 and 2009, respectively. Heis currently working toward the Ph.D. degree at theUniversity of Tennessee, Knoxville.

His research interests include SiC power deviceapplication, three-phase current source converters,three-phase converter design, and analysis for highefficiency applications.

Timothy Junghee Han (M11) received the B.S.and M.S. degrees in electrical engineering from Bu-san National University, Busan, South Korea, andthe Ph.D. degree in electrical engineering from Ko-rea Advanced Institute of Science and Technology(KAIST), South Korea.

He is a Senior Manager of Global Power Elec-tronics, Inc. (GPE). He has 20 years experience insemiconductor devices, SiC power devices and pack-aging, optical components and packaging, and sim-ulation of the power electronics systems. Currently,

he leads the design and development of the advanced power electronics subsys-tems using SiC devices for the next generation hybrid electric vehicles (HEV)and alternative energy industry at GPE, and collaborates with university pro-fessors and leading R&D institutions. He was a visiting scholar at the PowerElectronics Lab at the University of Tennessee at Knoxville and National Trans-portation Research Center of Oak Ridge National Laboratory. He has authored22 technical journal papers, 12 patents, and made 11 presentations at prestigiousinternational conferences.

Dong Jiang (S05M12) received the B.S and M.Sdegrees in electrical engineering from Tsinghua Uni-versity, Beijing, China, in 2005 and 2007, respec-tively. He began his Ph.D. study in the Center forPower Electronics (CPES) in Virginia Tech in 2007,and in 2010 he was transferred to the University ofTennessee, Knoxville to continue his research and re-ceived the Ph.D. degree there in 2011.

He has been with United Technologies ResearchCenter (UTRC) since Jan. 2012 as a Senior Re-search Scientist/Engineer. His research interests in-

clude high performance motor control, multi-phase PWM converter design andcontrol, EMI, power electronics devices, and magnetic bearings.

Leon M. Tolbert (S88M91SM98) received theBachelors, M.S., and Ph.D. degrees in electrical en-gineering from the Georgia Institute of Technology,Atlanta, in 1989, 1991, and 1999, respectively.

He worked at Oak Ridge National Laboratory,Oak Ridge, TN, from 1991 until 1999. He was ap-pointed as an Assistant Professor with the Depart-ment of Electrical and Computer Engineering, TheUniversity of Tennessee, Knoxville, in 1999. He iscurrently the Min Kao Professor in the Departmentof Electrical Engineering and Computer Science, The

University of Tennessee. He is the UTK Campus Director for the National Sci-ence Foundation/Department of Energy Research Center, CURENT (Center forUltra-wide-area Resilient Electric Energy Transmission Networks). He is alsoa Senior Research Engineer with the Power Electronics and Electric MachineryResearch Center, Oak Ridge National Laboratory. In 2010, he was a VisitingProfessor at Zhejiang University, Hangzhou, China.

Dr. Tolbert is a Registered Professional Engineer in the state of Tennessee.He received an NSF CAREER Award in 2001, the 2001 IEEE Industry Ap-plications Society Outstanding Young Member, and three prize paper awardsfrom the IEEE Industry Applications Society and the IEEE Power ElectronicsSociety. From 2003 to 2006, he was the Chairman of the Education ActivitiesCommittee of the IEEE Power Electronics Society and an Associate Editor forthe IEEE POWER ELECTRONICS LETTERS. He was an Associate Editor of theIEEE TRANSACTIONS ON POWER ELECTRONICS from 2007 to 2012. He waselected to serve as a Member-At-Large to the IEEE Power Electronics SocietyAdvisory Committee for 20102012 and is presently the Chair of the Member-ship Committee for the society.

Fei (Fred) Wang (S85M91SM99F10) re-ceived the B.S. degree from Xian Jiaotong Uni-versity, Xian, China, and the M.S. and Ph.D. de-grees from the University of Southern California, LosAngeles, in 1982, 1985, and 1990, respectively, all inelectrical engineering.

He was a Research Scientist in the Electric PowerLab, University of Southern California, from 1990to 1992. In 1992, he joined the GE Power SystemsEngineering Department, Schenectady, NY, as an Ap-plication Engineer. From 1994 to 2000, he was a Se-

nior Product Development Engineer with GE Industrial Systems, Salem, VA.During 2000 to 2001, he was the Manager of Electronic and Photonic SystemsTechnology Lab, GE Global Research Center, Schenectady, NY and Shanghai,China. In 2001, he joined the Center for Power Electronics Systems (CPES)at Virginia Tech, Blacksburg, VA as a Research Associate Professor and be-came an Associate Professor in 2004. From 2003, he also served as the CPESTechnical Director. Since 2009, he has been with The University of Tennesseeand Oak Ridge National Lab, Knoxville, TN as a Professor and Condra Chairof Excellence in Power Electronics. He is a founding member and TechnicalDirector of the multi-university NSF/DOE Engineering Research Center forUltra-wide-area Resilient Electric Energy Transmission Networks (CURENT)led by The University of Tennessee. His research interests include power elec-tronics, power systems, controls, electric machines, and motor drives.


James Nagashima (M98) received the B.S. degreein electrical engineering from California University,Long Beach, in 1969 and the Masters degree in busi-ness administration, in 1983.

He has over 30 years of experience in the field ofpower electronics. He retired from General Motorsin June 2009. During his career at General Motorshe was a GM Technical Fellow and Manager of Ad-vanced Engineering for General Motors PowertrainAdvanced Technology Center in Torrance, CA. Heis currently the Director of Technology Strategy for

Global Power Electronics, Inc., and is responsible for developing SiC basedpower electronics and related technologies.

He was responsible for developing advanced concepts in power electron-ics, motor drives, and controls for GMs electric, hybrid and fuel cell vehicleprograms. His past research projects included wide bandgap power modules,advanced thermal methods for power electronics such as phase change coolingand double-sided cooling, die attachment processes, inverter and converter de-velopment from 30 kW to 250 kW. He holds 55 patents in the field of powerelectronics, controls, and electric machines. He has published many journal andconference papers on advanced motor drives and electronics. He is currently areviewer for the Department of Energy Vehicle Technologies Program annualmerit review in the areas of power electronics and motors.

Sung Joon Kim received the B.S., M.S., and Ph.D.degrees in electrical engineering from the CaliforniaInstitute of Technology, and the MBA degree fromPurdue University, West Lafayette, IN.

He is experienced in bringing out new ideasand technologies from R&D labs, productizing themand building successful businesses from them. Hewas a Founder and General Manager of TransponderBusiness Group, while at Lucent Technologies, andbrought out a new optical subsystem products fromR&D ideas in Bell Labs into commercial market. Af-

ter leaving Lucent Technologies, he co-founded CENIX creating business fromhigh tech ideas in telecom industry. He is also a Founder and Managing Partnerof Global Opportunities Fund, a Venture Capital company, that incubates andfunds early stage companies. He is Founder, President, and CEO of GlobalPower Electronics, Inc. He is especially interested in creating values and start-up companies in power electronics industry based on novel and game changingtechnologies and ideas, such as SiC based power electronics products.

Srikanth Kulkarni graduated with an M.S. degreein electrical and computer engineering from the Uni-versity of Idaho, with a major in the field of Micro-electronic Packaging.

He worked in Idaho Microelectronics Laboratoryat the University of Idaho from 2006 to 2011 and iscurrently working at Micron Technology Inc., Idaho.

Fred Barlow (M96SM10) received the B.S. de-gree in physics and applied physics from Emory Uni-versity, Georgia, and the M.S. and Ph.D. degrees inelectrical engineering from Virginia Tech.

He is currently serving as a Professor and theDepartment Chair for Electrical and Computer En-gineering at the University of Idaho. He worked forseveral universities including Virginia Tech and theUniversity of Arkansas, where he held the position ofAssociate Department Head. He has served as the ma-jor Professor for thirty graduate students, and served

as PI or Co-PI on more than $5 million of funded research. He has authored overone hundred and twenty publications, and is coeditor of the Handbook of ThinFilm Technology (McGraw Hill, 1998), as well as the Handbook of CeramicInterconnect Technology (CRC Press, 2007).

Dr. Barlow is a Fellow Member of the International Microelectronics andPackaging Society (IMAPS).

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[SiC-En-2013-1] Development of a SiC JFET-Based Six-Pack Power Module for a Fully Integrated Inverter