Si Solar Cells

Crystalline Si Baseline Solar Cell Development

Students: Sandeep S. S., Gaudhaman Jeevanandam, Karthick Murukesan, Meenakshi Bhaisare, Amrita Joshi,Sunil Kumar Singh and Ketan Warikoo.

Faculty members: Anil Kottantharayil, B. M. Arora and Chetan Singh Solanki.

Solar cells were fabricated and characterized using the existing facilities. Development of various unit processes forhigh efficiency cells are also being developed with the existing facilities. The timeline as targeted in the proposal isgiven below:

Fig. 1.1: Roadmap for achieving 20% efficiency for c-Si solar cells.

The first Si cell efficiency target is 15% in 18 months (by the end of March 2012) and this process would be used asthe baseline process to investigate various methods for improving the efficiency. Presently achieved efficiency is11% with the facilities available in the CEN. The team has used the existing facilities to develop and understand unitprocesses and critical characterization techniques. However several of the silicon PV specific process equipmentsare yet to be installed, as there is a delay in receiving the equipment from the vendors. We are also experiencingdelays in procurement of some of the critical consumables. We expect to complete the installation and start up of thetools by the end of December 2011. So the timeline for the baseline process is expected to be delayed by 6 months,i.e. postponed to end of June 2012.

Cell fabrication and results:

The solar cells were fabricated on p-type mono crystalline CZ Si wafer, of <100> orientation and resistivity of 0.1-1ohm-cm. Cells were designed with area of 1cm x 1cm, with a spacing between cells of 100 um. The cells wereisolated using a 300 nm thick SiO2 layer. The contact design had 3 fingers, 140 um wide, and one bus bar, 1000 umwide. The fingers were spaced at 2.75 mm from each other.

The junction was formed using a solid source diffusion process. After diffusion the sheet resistance was measured tobe 20 ohm/sq. A 70nm thick SiNx, with a refractive index of 2.0, was deposited as an anti- reflective coating usingICP-CVD process. Electron beam evaporated Ti/Pd/Ag (50nm/50nm/100nm) was used as top contact, and a

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thermally evaporated Aluminum (140 nm) was used as back contact. The samples were then annealed in forming gasat 420oC.

Fig. 1.1: Structure of the fabricated device with SiO2

between cells used for isolation. Fig. 1.2: Charactersitcs of one of the fabricateddevices.

Device structure and cell characteristics are shown in Fig. 1.1 and 1.2. The solar cell exhibited a VOC = 578 mV, JSC =27.17 mA/cm2, FF = 50.9%, and efficiency = 8%. The shunt conductance was measured to be 0.015 S. I-Vcharacteristic of the cell indicated that shunt resistance needs to be increased further while the series resistance needsto be lowered. In order to lower the shunt resistance, an RIE based cell isolation process was tried in place of anoxide based cell isolation. The cell structure and the characteristics are shown in Fig. 1.3 and 1.4.

Fig. 1.3: Structure of the fabricated device RIE etchedtrenches between cells used for isolation.

Fig. 1.4: Charactersitcs of one of the fabricated deviceswith structure shown on the left.

In the reactive ion etch (RIE) based cell isolation process, the spacing between the cells was increased from 100 umto 2 mm. Here the full wafer was diffused, an ARC layer was deposited and the cells were then isolated using aplasma etching process. The rest of the processes remained same as with the oxide based cell isolation process. Thedevice exhibited a VOC = 579 mV, JSC = 25.5 mA/cm2, efficiency = 7.67%, and a FF = 51.8%. The shunt conductancewas measured as 0.0002 S. There was a slight decrease in the efficiency and the open circuit voltages which couldpossibly be caused by a increase in the surface recombination velocity at the etched sidewalls of the cell, broughtabout by the plasma based etching process. Lifetime studies needs to be carried out to assess the impact of theplasma based process on the bulk lifetime of the carriers.

An improvement in efficiency was achieved by assessing the doping profile using SIMS and including a backetching step in the cell processing to remove very highly doped dead layer at the top of the emitter diffusion. The

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cells have antireflection coating, but have no texturing. We have fabricated solar cells from p type crystalline silicon,with efficiency of 10% with area of 1cm2 and efficiency more than 11% with area 0.25 cm2 without correcting forthe contact area coverage. The process is now being improved to achieve higher efficiency.

Unit Process Development:

1) Texturing Process:a) Inverted Pyramid Texturing:

A process for the inverted pyramidal texturing was developed for p type <100> Si wafers using tetra methylammonium hydroxide (TMAH) as the etchant. The process development included the development of amask and subsequent lithography processes, and finally the etching optimization. The mask was designedto include 20 um squares with a spacing of 10 um between the squares. The sample was etched in a 2.5%TMAH solution, at 90oC for 25 min. The oxide was removed and the sample was taken for SEM imaging.SEM image of a Si wafer surface subjected to the process is shown in Fig. 1.6.

b) Random Pyramidal Texturing:

The process doesn’t include any lithographic steps. The etchant used was 2.5% TMAH at 90oC. The etchingwas carried out on 2 inch, polished, p type <100> Si wafers. The process was done for 40 min. The processwas also tried out for As-cut Si wafers. However, As-cut wafers required the development of a saw damageremoval step. The saw damage removal was done using a HNA solution. The As-cut wafers were dipped inHNA for 20 min, before they were subjected to etching in 2.5% TMAH solution. Fig. 1.7 shows the crosssectional SEM image of a randomly textured sample, and also the reflectance measurements done on as-cutand polished Si wafers for two different concentrations of TMAH (2.5% and 15%), see Fig. 1.8. Significantreduction in reflectance was achieved. Experiments were done to assess the impact of addition of IPA to theetchant solution, and was observed that it lead to smaller pyramid sizes but with higher density.

The texturization process was integrated to the cell process described above and efficiency was found to belower. It was noticed that the series resistance of the cells had increased. We have concluded that the cellwith texturization requires thick metallization for proper probing. This would be possible with screen-printing or electroplating processes which are being developed.

Fig. 1.6: SEM image of an inverted pyramid texturizedSi (100) surface.

Fig. 1.7: SEM image of an random texturized Si (100)surface.

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Bare Si Ascut Si(2.5% TMAH) Ascut Si(15% TMAH) Polished Si(2% TMAH) Polished Si(15% TMAH

200 400 600 800 1000 12000

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20

30

40

50

60

70

80

% R

efecta

nce

Wavelength

Fig. 1.8: Comparison of reflectance obtained with and without texturization. Both as-cut and polished wafers arecompared. UV-Vis spectrometer available in the CEN was used. This spectrometer does not have an integratingsphere and hence the results are qualitative in nature.

2) Anti-reflective coating development:

In the base line process a 70 nm thick SiNx layer, with a refractive index (RI) = 2.0, was used as the ARC layer.On subjecting the sample to FGA at 420oC for 10 min, it was seen that the nitride films blistered off due torelease of hydrogen. This was identified as a major hurdle in the development of high efficiency Si solar cells,where in the screen printed contacts are fired at temperatures in the order of 800oC. The films were depositedusing various recipes and subjected to FTIR studies to check for the H 2 content, before and after anneal tounderstand the phenomenon. Based on the FTIR studies new SiNx layers were developed by varying the processparameters, which could withstand the high temperature anneal process at 800oC. The Fig. 1.9 shows themicroscope image and FTIR spectra of a blistered SiNx layer and also microscope image and FTIR spectra of aSiNx film stable at 800oC.

The FTIR data reveals that the film that blistered during annealing showed FTIR signals corresponding to N-Hbending modes and Si-H stretching modes. These disappeared after anneal. These were not present in the recipethat did not lead to blistering in the SiNX film. On the other hand the N-H stretching mode is seen in the filmthat did not blister and this was still retained after anneal. This signal was not seen in the film that blistered. Wehad also seen that some of the recipes resulted in no N-H bending modes and Si-H stretching modes but stillblistered (results not shown). We conclude that the hydrogen incorporated in the film is either not bonded orbonded in N-H bending modes and Si-H stretching modes in films that blistered. These bonds are likely to bebroken during high temperature anneal used for BSF or contact firing processes. Cells incorporating theimproved SiNX film are currently being processed.

Further investigations are on-going to assess the surface passivation on n-type diffused layers and alsocompatibility with textured surfaces.

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Fig. 1.9: SiNX films deposited using ICP-CVD system. The top images are optical micrograms of films

deposited using different recipes and annealed at 800C. The FTIR spectrograms of the films are shown

below the images.

3) Optimization of Phosphorous Diffusion and Dead Layer Removal:

A solid source phosphorus diffusion process was developed to obtain a sheet resistance of 70 ohm/sq. SIMSmeasurements on the sample indicated the presence of a dead layer of ~70 nm. In order to remove the deadlayer and to attain the targeted sheet resistance, the diffusion process was modified to include the impact of thedead layer removal process. Fig. 1.10. shows the SIMS profile for a sample diffused at 890 oC, for 25 min. Fig.1.11. shows the sheet resistance measured after the dead layer removal for three different diffusion conditions.The process done at 900oC, for 25 min yielded the targeted sheet resistance (60 – 80 ohm/sq.). However, theSIMS profile of the same is awaited. The dead layer removal was carried out using an HF: HNO 3: Acetic acid(1:60:6) solution. Fig. 1.12. shows the life time measured for processes including diffusion and deadlayer removal. The minoritycarrier lifetime increases after phosphorous diffusion due to impurity getting. However the lifetime is seen todecrease when the surface is passivated using iodine – methanol (IM) solution after diffusion. It is known thatthe IM solution passivates p-type silicon surfaces (We have obtained ~ 1 msec minority carrier life time on p-type FZ wafers with IM passivation) and does not passivate n-type silicon to the same extent. The wafer afterdeadlayer removal shows a lower minority carrier lifetime. When a heavily doped surface layer is present, thisis likely to result in a surface field, which would repel holes, and hence surface recombination would be smallerin such a case. This would result in a better overall carrier lifetime. However, when the surface layer is etched,the surface field would be less and hence the surface recombination velocity would increase resulting in anoverall reduction in minority carrier lifetime. In this scenario, it can be concluded that the bulk minority carrierlifetime after diffusion has increased.

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Fig. 1.10: SIMS data of diffused junctions. A highconcentration layer of ~ 70nm thick is seen at thesurface.

Fig. 1.11: Solid source diffusion optimization withdeadlayer removal.

Fig. 1.12: Life measured using QSSPC technique at a minority carrier density of 1015 cm-3 after various processingsteps. The vertical axis shows the lifetime in microseconds. RCA: RCA clean, Pyro: pyrogenic oxidation, PSG:phosphosilicate glass, IM: iodine methanol solution.

4) Optimization of Boron Diffusion for n-type solar cells:

We have initiated some trials of fabricating solar cells starting with n type silicon wafers. This requires diffusionof boron into n type silicon base to form the emitter region. It is known that a layer of silicon boride is formednear the surface region of the diffused silicon wafer , which is quite impervious. We have investigated the thinboride layer by Transmission electron microscopy (TEM) and x ray diffraction measurements. TEMmeasurements reveal that the layer formed under typical diffusion condition(975C, 45 min) has islandmorphology. This is unexpected and has not been reported earlier. Grazing incidence x-ray diffractionmeasurements produce some broad features and some sharp lines. This leads us to believe that silicon boridelayer is a mixture of amorphous tissue and nanocrystalline Si-B structures. The island nature of the surfacemorphology seems to be the result of precipitation of boron rich phase at high level of boron concentration (>1020/cm3) in the surface region.

5) Edge Isolation Using RIE:

The edge isolation process was developed using the RIE tool available at the CEN, IIT Bombay which can onlyetch the top surface of Silicon wafer. In a solar cell process the edge isolation process electrically isolates thefront and rear of the cell by etching away the junction formed on the edges of the wafer. The aim of the exerciseis to learn about the process which can guide the development of processes in edge isolation tool being boughtas part of NCPRE. The process made use of Sulphur Hexaflouride (SF6) as the etch gas. The targeted etch depth

Sh

eet

Resis

tan

ce (

Oh

m/s

q)

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was approximately 3 um. An etch rate of 2.4 um/min was obtained using the RIE process. The recipe used forthe same was: SF6: 25 sccm, Pressure = 80 mT, RF Power = 100 W.

Fig. 1.13: Si etch process developed using the RIE tool available at the CEN. An etch rate of 2.4 um per minute wasachieved and the step shown is 4.4 um.

6) Al2O3 deposited by reactive sputtering for passivation:

Objective: Optimization of pulse-DC reactive sputtered Al2O3 dielectric for surface passivation of p-type siliconsurface for c-Si solar cell applications.

Introduction: The Al2O3 dielectric has been widely studied for the surface passivation of p-type silicon surfacebecause of its property of containing negative fixed oxide charges. Various techniques have been studied for Al 2O3

dielectric deposition to achieve a high quality passivation of the rear surface for p-type silicon solar cell and emitterfor n-type silicon solar cell. The most popular technique is chemical vapor deposition (CVD) which has shown mostefficient passivation, but the disadvantage is higher cost for processing, because of expensive precursors andrequirement for various safety arrangements. Atomic layer deposited (ALD) Al2O3 dielectric has shown excellentsurface passivation. Due to its very low deposition rate there are challenges to adoption for manufacturing. On theother hand the physical vapor deposition (PVD) technique gained considerable interest due to higher deposition rateand simpler process. Here we present the reactive sputtering technique for Al2O3 deposition using pulsed- DC powersupply and initial results on the surface passivation of p-type Silicon wafer surface using this Al 2O3. The reactivesputtering of pure Al target (99.9995% purity) is carried out in high purity oxygen ambient with argon as sputteringgas. The Al2O3 film is deposited on p-type silicon wafer to perform various material characterization and opticalcharacterization like life-time measurement (quasi-steady state photo-conductance (QSSPC) technique). To measureoxide charges a high -frequency C-V measurement (HFCV) is done on Metal-Insulator- Semiconductor (MIS)structure.

Results & Discussions: As shown in Fig. 1.14, a higher deposition rate of 6-8 nm / min is observed for high power processes measured byX-ray reflectivity (XRR), it also shows an increase in surface roughness with power. Although the value shown isstill very low as ~6 Å for 1000 W deposition power which is also acceptable. These films are deposited with Ar; O 2

flow of 15; 60 sccm for 300 sec.

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Fig. 1.14: Surface roughness and thickness of the filmby X-ray reflectivity measurement. These films aredeposited with Ar; O2 flow of 15; 60 sccm for 300 sec.

Fig. 1.15: High frequency normalized C/C max versus gate voltage plot of AlxOy MOS capacitor with AlxOy

deposited at 500 W and 1000 W.

HFCV measurements performed on MIS structure for films deposited at 500 W and 1000 W. Film deposited at500 W with Ar; O2 flow of 10; 25 sccm for 300 sec is the optimized recipe to obtain stoichiometric high qualityAl2O3 dielectric film. Film deposited at 1000 W with Ar; O2 flow of 15; 55 sccm for 300 sec. Fig. 1.15 shows thenormalized C/Cmax curve and Table 1.1 shows the extracted results.

Table 1.1: Parameters extracted from the HFCV for different deposition power.

Power (W) EOT (nm) k VFB (V) Qox (cm-2)

500 8.59 8.15 -0.7 -3.5×1011

1000 12.44 8.93 0.8 -2.88×1012

The HFCV curve shows a positive shift in VFB value for high power deposition. The negative fixed oxide charges(Qox) of 2.88×1012 cm-2 is obtained for deposition at 1000 W power which is higher by one order of magnitude ascompared to film deposited at 500 W ( Qox of 3.5×1011 cm-2). Thus we can use this property of high negative chargedensity in Al2O3 for the passivation of p-type surface for c-Si solar cell.

The surface passivation quality of Al2O3 film can be assessed by extracting surface recombination velocity (SRV)from measured effective minority carrier life-time by QSSPC technique. For this measurement, low resistivity (1-10Ω cm) p-type FZ Si wafers are used and Al2O3 film is deposited at both front and back surfaces of the wafer. Al2O3 isdeposited at 1000W for 300 sec with Ar:O2 flow of 15sccm:55sccm and forming gas annealing (FGA) is done at420oC for 20 min. The thickness ~ 25.5 nm and refractive index ~ 1.62 of Al2O3 is obtained for this film as measuredby spectroscopic ellipsometry. The effective life-time measurements are performed at various steps to see the impactof the particular step on the life-time and the results are summarized in Table 1.2. To measure the bulk life-time τ bulk,Iodine- Methanol (IM) solution was prepared, and measurement is performed after 15 minutes dip of wafer in thesolution.

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Table 1.2: Effective life-time measurement to evaluate passivation quality of Al 2O3, here double polished lowresistivity p-type FZ wafers used.Step Measurements τ eff (μ sec) at

∆n=10 14 cm-3

Seff (cm/s) at ∆n=10 14 cm-3

τ eff (μ sec) at ∆n =10 15 cm-3

Seff (cm/s) at ∆n=10 15 cm-3

1 Bare Si wafer before RCA clean

11.77 1265 10.8 1329

2 Bare Si wafer after RCA 12.74 1168 11.97 11933 Bare Si wafer after RCA

clean in IM solution 1609.3 252.46

4 As- deposited (Al2O3/Si/Al2O3)

1.58 9484

5 After FGA (Al2O3/Si/ Al2O3) 13.76 1080 15.56 904

The effective surface recombination velocity Seff (cm/s) for both surface passivated by Al2O3 is calculated using the

following formula:

where, W is sample thickness. bulk is the minority carrier lifetime in the bulk of Si and the value of effective lifetime

obtained in step 3 in table 2 is used as bulk.

It is observed that as- deposited SRV for Al2O3 is as high as 9.4× 10 3 cm/s, while the improvement in SRV observedafter FGA was 1.08 × 10 3 cm/s, calculated at ∆n = 1014 cm-3. The SRV values obtained for after FGA is 904 cm/s at∆n = 1015 cm-3. J. Benick et al. (Proc. 35th IEEE PVSC in 2010, pp. 891), had investigated Al2O3 deposited by PE-ALD technique for surface passivation and the samples were annealed in atmosphere for 25 min. A SRV value of ~ 6cm/s was reported at ∆n = 1015 cm-3. The authors have attributed the passivation to growth of an interfacial SiO2

layer. Our process requires further optimization and analysis to improve the passivation and also to assess thephysics behind it. Note that our process used FGA for anneal in which case an interfacial oxide is unlikely to grow.

7) Heterojunction with Intrinsic Thin layer (HIT) solar cells:

Apart from these, we have done preliminary work on solar cell with half HIT structure. Solar cell fabricatedfrom p a-Si:H/n-c-Si heterostructure using hot wire CVD technique shows anomalous behavior. The shortcurrent density is small ( 2-4 mA/cm2), but with application of reverse bias (1V) , the current density increasessubstantially ( 30 mA/cm2). Additionally, the spectral response of short circuit current is mainly in the blue,while the response in the red region is negligible. Simulations suggest this behavior is caused by low doping ofthe p a-Si:H layer. Experiments to improve the p type conducting a-Si:H layer are continuing.

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Fabrication of a novel solar cell with 3-D junction

Students: Som Mondal

Faculty member: Chetan Singh Solanki

Introduction: In this work, a new structure for crystalline silicon solar cell has been proposed. The basic motivationbehind this structure of the cell is to reduce the optical losses and to increase charge collection probability. Threemajor improvements, as compared to the conventional solar cell, have been focused while developing the celldesign:

1. Shifting the front contact (finger-busbar) to the rear side of the cell to remove the shadow loss (6 - 9%) dueto the presence of front contact in conventional solar cell.

2. Create 3-D junction in the bulk to enhance photo-generated charge separation and collection probability(especially important for poor bulk carrier lifetime).

3. Provide good surface passivation to front and rear side to reduce recombination loss.

Considering these objectives, a solar cell structure with emitter on both top and bottom side connected by 3-D dopedtrenches/channels has been proposed. The proposed solar cell structure is shown schematically in Fig. 2.1. Theproposed novel diffusion based trenches will create lower mechanical stresses in the bulk material as compared toexisting cell structures like MWT or EWT wherein a hole is drilled in the substrate using laser.

Fig. 2.1: Schematic of the novel solar cell with 3-D junction

Temperature evolution of the substrate under laser irradiation: The n-type trenches that connect the frontemitter with rear one is proposed to be fabricated by laser assisted diffusion. The temperature in the substrate underabsorption of laser radiation should reach near melting point of Si to enable high diffusion co-efficient of the dopantatoms. Hence the temperature profile and its evolution with time are being simulated using Matlab.

Transient heat conduction equation has been solved using numerical equation with laser radiation as heat source inthe bulk region. Different models for parameters like thermal conductivity, heat capacity, absorption coefficient etcas a function of temperature have been taken into the simulation as the temperature rise is very high. The radial andthe depth-profile and the time evolution of temperature under absorption of laser radiation of two different pulse-

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6 µm

7 µm

8 µm

6 µm

5 µm

durations; 1 µs and 3.3 µs (laser power - 150W, wavelength - 1070 nm and beam width - 20 µm) are shown in Fig.2.2.

(a) (b) (c)Fig. 2.2: (a) Radial profile, (b) depth profile and (c) time evolution of temperature due to laser irradiation.

The time evolution curve shows avalanche type behaviour after a certain time. This behaviour is not well understoodat this point. It is speculated that the temperature sensitive parameters are providing positive feedback and hence thetemperature shoots up. Further inspection on the simulation algorithm is being carried out to understand thebehaviour. Fig. 2.3 shows the time evolution curve for 25 W, 1070 nm wavelength and different beam width of laserand the avalanche behaviour is again observed below certain beam-width. Simulation is also carried out to evaluatethe effect of wavelength of laser beam. Fig. 2.4 depicts the spatial temperature distribution for two wavelengths 532nm and 1070 nm. As expected the 532 nm laser get absorbed in shallow depths while the 1070 nm laser absorbsnearly uniformly.

(a) (b)Fig. 2.3: Effect of beam-width on temperature in irradiated column; (a) no avalanche observed for beam widthhigher than 6µm (b) avalanche is observed for beam width below 6µm.

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(a) (b)

Fig. 2.4: Spatial temperature distribution for (a) 532 nm and (b) 1070 nm

Simulation of novel solar cell: The proposed novel solar cell structure (device) has been simulated in SentaurusTCAD software without any front surface texture. Instead of 3-D columnar trenches, however, 2-D 'box-like'trenches have been made as the solar cell could be made on 2-D platform. Several parameters of interest like trenchwidth, trench separation, trench doping concentration, minority carrier lifetime and front SRV have been varied andtheir effects on the cell performance have been studied. The results are compared with simulation results of aconventional solar cell, whenever possible. As an example, the results for trench separation have been comparedwith the front contact separation in case of conventional cell. Shadowing effect of front contact grid is taken intoconsideration. Fig. 2.5 and Fig. 2.6 depicts the effect of trench width and trench doping concentration respectively,for two different bulk minority carrier lifetime.

0 10 20 30 40 50 60 7029.5

30

30.5

31

31.5

32

10 us 0.1 us

Trench width (us)

Jsc (mA/cm2)

1.00E+016 1.00E+018 1.00E+0209

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0.1 us 10 us

Fig. 2.5: Effect of trench width Fig. 2.6: Effect of trench doping

Fig. 2.7 demonstrates the effect of trench separation on the efficiency of novel solar cell for different electronlifetime in base. For a comparison the contact separation in conventional solar cell has been varied and the resultsare compared in the same figure. It is seen that for very poor minority carrier lifetime in base, the relativeimprovement is very high for very closely separated trenches. While for moderate and good lifetime, the maximumrelative improvement occurs when trenches are moderately separated.

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20 70 120 170 220 270 320 370 420 470 520101112131415161718

Chart Title

10 1 0.1 10 1

0.1

trench/contact separation (um)

Efficiency (%)

Fig. 2.7: Effect of trench separation (solid lines - novel cell, dashed lines - conventional cell) for10, 1 and 0.1 µs.

Fig. 2.8 shows the effect of minority carrier lifetime in n-type emitter and p-type base region. The drop in efficiencyfor very low τp in case of novel cell happens due to low diffusion length in wide trenches that is not present inconventional solar cell. The effect of SRV, substrate doping concentration, junction depth etc is also studied.

0 0.01 0.1 1 10 1007

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15

17

19

conventional novel

Tau-n (us)

Efficiency (%)

0 0.01 1 100.113

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novel conventional Linear (conventional)

Tau-p (us)

Efficiency (%)

(a) (b)Fig. 2.8: Effect of minority carrier lifetime in (a) p-type base and (b) n-type emitter

Conclusion: From the thermal simulation, the radial and the depth distribution appears to be as of expected. Thespatial profile for different wavelengths also shows significantly expected behaviour. But the time evolution oftemperature shows an unexpected avalanche behaviour which becomes very prominent for very high fluence value.This behaviour is not well understood at this point and it is being tried to understand it.

From the device simulation, it is seen that the device performs in most of the condition better than the conventionalsolar cell. If the τn is very high (~100 µs or so) or τp is too poor (~ 0.05 µs or less), then only the novel cell efficiencyis worse than the conventional cell. For other condition, the novel cell performs better. It is also observed that poorerthe material bulk lifetime, better the relative improvement (>15% for 1 µs). Hence this structure might be very goodfor solar cell fabrication on solar grade silicon.

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Future plan: The current device simulation will be extended for other parameters like back surface passivationcontact pattern, BSF optimization etc. Real time phenomenon like Gettering will be incorporated in devicesimulation. Surface texturing will also be applied.

The unwanted avalanche behaviour of the time evolution curve is being studied in detail. The thermal simulationwill be tried to be associated with the Sentaurus device simulation using Sprocess.

The 1070 nm CW fiber laser, bought as part of NCPRE will be used to fabricate doped trenches in silicon. Theresults from the thermal simulation may be used to predict the junction depth after laser assisted diffusion.

An alternative technique to measure junction depth is being studied for application in deep junction characterization.The results from these experiments will be verified with SIMS/other technique.

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Silicon Concentrator Cells

Students: Mehul Raval and Vishnu Kant Bajpai.

Faculty members: Chetan Singh Solanki.

Introduction: Concentrator solar PV systems offers possibility of cost reduction but offers challenges of suntracking, heat removal from solar cells, and special design of solar cells. In this work fabrication of Si solar cells forconcentrator applications is proposed. One of the main features of concentrator solar cells is to have low seriesresistance. The low series resistance can be obtained by lower metal-semiconductor contact resistance and lowermetal resistance itself. For this Ni/Cu plated contact for solar cell application is being developed. In our earlier work,we have demonstrated the use of Ni/Cu plated contact to obtain low metal-semiconductor contact resistance of 8-11mΩ-cm2 under optimized conditions and operation of solar cell till 4 suns without drop in efficiency.

The Ni/Cu front-contact metallization scheme for c-Si solar cells is a low cost and potentially useful for highefficiency solar cells manufacturing. But in spite of being an ancient technique, due to some inherent problems (likeweak adhesion of contacts with the solar cell, effect of chemical processing environment, batch process etc.), thistechnique is not industrially accepted till now. The plated Ni/Cu contacts are obtained by metal plating at the patternSiNx layers on solar cells. In this process two major problems have been indentified; (a) poor adhesion of Ni/Culayer with Si which results in delamination of the metal contacts, and (b) background plating in non-patterned SiNxarea, which causes decrease in cell performance. These issues are being researched in this work.

Initial studies on background plating: Background plating studies were carried out under the optimized bathconditions at temperatures from 70°C-90°C. Surface morphology, EDAX and carrier lifetime studies have been doneto assess the extent of impact and recommend modifications in the process steps. It was observed that depositionconsisting of Na and Cl (miscellaneous ions) was present in the valley regions between the pyramids. No Ni or Pdeposits were observed except for a couple of sample points on a particular cell. In addition, no deposition wasobserved on the pyramid surfaces. Fig. 3.1 shows the optical and close-up front surface morphology withbackground plating for bath temperature of 70°C. The distribution of deposits was random and hence difficult toquantify. It was inferred that the miscellaneous ions were deposited due to bath decomposition at high bathtemperatures. Many thorough rinses were needed to remove the deposits from the ARC of the cells, and it isrecommended that an ultrasonic cleaning step can be tried to ensure complete removal of the unwanted deposits.Also the deposition was more pronounced for aged bath. This is due to the fact that more decomposition componentswill be present in an aged solution. Using a fresh bath for each run would alleviate the problem of excessivemiscellaneous ions being present in the bath. From the carrier lifetime studies it was observed that, on an average thecells recovered to the original lifetime values after the annealing step which probably ensured that minimumunwanted deposits remained on the front side of the solar cells.

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(a) (b)

Fig. 3.1 Background plating of Ni (a) Optical image (50 x) (b) corresponding SEM Image (plating temperature was70°C)

Adhesion of Ni/Cu contacts with Si: The aforementioned adhesion problem is not well addressed in the literature.Only some prescriptive ideas have been given and accepted as challenge by some working groups. It isexperimentally observed that the adhesion is a very sensitive property varying with plating conditions like: platingtemperature, bath composition, sensitizing & activating steps of samples. For adhesion problem, it seems that thereare mainly two possibilities. One is that the existing process needs to be optimized with respect to adhesion. Otherpossibility is that there is a need of major changes in the existing process like: major modification in the process,new chemical exchange/introduction in the process etc. In each of the possible directions for adhesion improvement,adhesion is to to be quantified. No accurate and universal method is found till now to quantify adhesion of Ni-Cusystem with silicon. So quantification of adhesion is another obstruction present in the path towards adhesionimprovement and needs to be cleared.

Experimental work done and future plan of study: Experimentally, Ni- Cu metallization process is successfullyapplied for solar cells patterned either by laser or by lithography. Even though having better electrical charcteristicsof solar cells using nickel-copper two step metallization, the whole front side metal assembly peels off while dealingwith it due to small mechanical stresses. The adhesion between Ni-Cu is found to be good, but due to loweradhesion between Ni-Si, the complete system suffers with this introduced unreliability. Generally, for the higher Ni-layer thickness(beyond ~300 nm) adhesion reduces drastically and it automatically peel off, even during the plating.

Scotch tape test have been done for qualitative study of adhesion but this rather simple adhesion test method couldnot provide meaningful data. Scratch tests (Fig. 3.2) and nanoindentation tests are also performed on the samples butcouldn’t give any satisfactory results. So appropriate testing methodology is required which is also the part of futurework.

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Fig. 3.2: AFM images of samples surface after performing scratch tests @50 mN, 80micron scratch.

It is found that the nickel deposited on textured front side surface of the solar cell is quite porous (Fig. 3.3) due towhich subsequently deposited copper may get easily diffused during thermal treatment for contact formation. Alsothis porosity causes higher contact resistance. But the nickel deposition done on the non-textured n-type siliconwafer is densely packed and in semicrystalline state, which provides a better barrier against copper diffusion causingthe junction shunting. There is need to find reasons behind this discrimination and to get the dense packed nickeldepositions for solar cells are the parts of future study.

Fig 3.3: SEM images of (a) nickel deposited on textured front side emitter (n-type) of a solar cell, (b) nickeldeposited on n-type polished silicon wafer.

Natural oxide formation on the silicon substrate (before Ni/Cu plating) may be an important cause of loweradhesion and poor performance of the solar cells. So it is planed to do some substrate-surface characterization forbetter understanding of the substrate surface upon which we are going to deposit nickel.

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Novel technologies for contact formation using temperature sensitive paste

Students: Akella Sastry, Mehul RavelFaculty members: Chetan Singh Solanki.

Introduction: Photovoltaic solar cell uses solar radiation and converts it into electricity. Even though the convertingefficiencies are reached to 25% for a crystalline silicon solar cell, the commercially available cells are at 16-17%efficiency level. In order to bridge this gap innovating ways are required to manufacture high efficiency cellswithout increasing the cost of production. Metallization schemes, alternative to screen printing, can be useful inenhancing the cell efficiency.

Commercially available solar cells are patterned using screen-printing technique to make contacts at front side withsilver containing metal paste. Screen printed solar cells have average finger widths of 100-125 µm and fill factors0.70 to 0.75, which are the limiting factors for optimum performance of solar cell. High finger widths leading toshading losses and less fill factors reduces the efficiency of the solar cell. In screen-printed solar cells, heavy dopingof emitter required in order to achieve the good contact with silver.

Improved metallization techniques are required to optimize the solar cell performance. The main objectives are:

Reduce the finger widths (< 100 µm) to avoid shading losses. Metal contact should have good mechanical and electrical contact with silicon surface (specific contact

resistivity 0.003-0.03 mΩ cm2). Achieve higher fill factors ( > 0.75) by lowering line resistance

The alternative metallization technique, which can provide the above features, could be various types of platingtechniques. The plating techniques require patterning of dielectric layer (mostly SiXNY). Patterning of ARC enablesfor the front side metallization.

Experimental: The objective is to create finger bus bar patterns on the solar cell. A structure is made by micromachining in the finger bus bar structure with stainless steel which can be placed on the solar cell to get the pattern.Size of the solar cell is 4 X 4 cm2 and accordingly the structure with 14 fingers and 1 bus bar. Grooves inside themechanical structure (Fig. 4.1) are used to keep the electric heaters and sensors to provide heating of the cell oncepasted. The concept of the technique is shown in Fig. 4.2.

Bus-bar

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Heat the solar cell to 390 0CFor 90 sec

Solar cell is cleaned by Ultrasonic bathClean the solar cell with DI water

Apply paste on the mechanical structureSolar cell is made in contact with the structureStart the sample

Fig. 4.1: Metal structure with finger – bus bar pattern

Fig. 4.2: Schematic process of patterning of ARC

The structure is applied with paste (commercially available etching pastes containing phosphoric acid) and kept incontact with the solar cell. The paste gets transferred to the solar cell in the same pattern. At the same time, the solarcell is heated with the help of electric heaters in the structure with the optimized temperature conditions (390°C – 90s). The solar cell is removed after the heating process and is subjected to cleaning. Process flow of patterningdielectric layers of solar cells using above motioned technique is shown in Fig. 4.3.

Fig 4.3: Process flow of patterning dielectric layers of solar cells.

Cleaning is done with DI water and ultrasonic bath so that to remove the residues of chemical paste. After dryingthe solar cell, the etched portion is observed with microscope. An average finger width of 150 μm is achieved withthe structure (see Fig. 4.4). The further reduction in finger width is targeted. The problem with the present

mechanical structure is that when heated at 390C, due to convection the air within the groove also gets heated and

as a result the etching of dielectric layer occurs at the undesirable locations, between the fingers. In order to confirmthis, structure with only two metal fingers (far apart) is designed. This has the provision of inserting temperaturecontroller as well as heaters to heat the solar cell to desired temperatures. The thickness of the finger at the tip isaround 50 µm.

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Fig. 4.4: Etched portion of a finger (≈150µm)

In order to obtain less than 100 µm another method for patterning is also proposed. In this proposed technique, auniform surface with thickness of 2 mm (for example, acrylic sheet) is taken and the etching paste is uniformlysprayed on it by ultra sonic bath. A thin wire of radius less than 50 µm (generally these wires used for wide EDMmachining) is kept in contact with the uniformly sprayed paste. The same wire is kept on the solar cell so that thepaste is transferred as thin finger. Thermal sensitivity of the etching paste will be activated at elevated temperatures.The solar cell with applied paste will be heated to optimum temperature condition of corresponding etching paste(390°C – 90 s) for the etching process. After heating the sample, it will be subjected to ultra sonic bath to remove thechemical residues of etching paste. This technique is demonstrated in Fig. 4.5.

Once the required finger width is achieved (which is less than 100 μm), the number of wires can be increased to thenumber of fingers for a 4 cm X 4 cm solar cell (with 14 no. of fingers and 1 bus bar). This alternative method issimultaneously tested with the mechanical structure. Both the methods are to be compared in terms of processfeasibility, number of steps and minimum finger widths. Patterned dielectric layers, obtained from these techniqueswill be processed for metallization to complete the solar cell fabrication.

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Fig. 4.5: New approach of using thin wire for patterning.

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Plasmonics for Photovoltaic Applications

Students: Hemant Kumar Singh (experimental), and Mopurysetty Sundara Murthy (simulation and modelling)

Faculty members: Anil Kottantharayil and C. S. Solanki (experimental), and Swaroop Ganguly (simulation and modelling)

Acknowledgements: Dr. Meril Mathew (experimental)

The relatively new field of plasmonics seeks to control light at the nanoscale by coupling it to charge densityoscillations at the interface between a metal and a dielectric. Implementing plasmonics (i.e enhanced scattering ofincident light in photoactive absorbing material using metal nano particles) we can make photovoltaic absorbers“optically thick” which enable us nearly complete light absorption even in thin films and apparently complete photocarrier current collection. As increased scattering at longer wavelengths using metal nano particles would enablegood light trapping, it can offer the possibility of reducing the physical thickness of the photovoltaic absorber layerswhile keeping their ‘optical thickness’ constant. Clearly, plasmonics-enhancement could be applied to all kinds ofsolar cell technology as an add-on. However Si solar cells would be used as an initial test vehicle to study theeffectiveness of the technology.

This report is divided into two parts: 1. Experimental investigation of plasmonic effects2. Simulation and modeling of plasmonic effects

Experimental Investigation of Plasmonic Effect: Our work in this report presents the results on tuning the plasmonic resonance by varying size and shape of

silver nanoparticles and the thickness of dielectric spacer layer in spectral region which is most suitable forphotovoltaic (PV) application and also the effect of Ag nanoparticles sandwiched between silicon nitride and siliconoxide layers to find optimized device architecture for implementing and optimizing the plasmonics based conceptfor Si based solar cell. Silver nanoparticles of different sizes are fabricated on glass substrate and on different devicearchitecture (as shown in next section) on Si based substrates by RF sputtering of silver film of different massthicknesses followed by annealing at 200 0C in Ar gas atmosphere and in some cases by RTP at 400 0C for 1 minutesfor Si based substrates. Scanning electron microscope (SEM) analysis for glass based substrates showed thatdifferent thicknesses of silver film resulted on nanoparticle formation of different sizes, shapes and particledistribution on the glass substrate. Also for Si based substrates silver nanoparticles of 100nm - 200 nm sizes arefabricated by RF sputtering of silver film having 15 nm mass thicknesses followed by RTP at 400 0C in Ar gasatmosphere for 60 seconds for preparing different samples for comparative study of different device architecture andeffect of Ag nanoparticles sandwiched between SiO2 and Si3N4 layers. Si3N4 and SiO2 deposition were done byinductively coupled plasma chemical vapour deposition (ICP-CVD). Si3N4 deposition was done with optimizeddeposition rate of 12 nm/min at 250 0C with refractive index ~ 2.08 and 18 nm/min at room temperature withrefractive index ~ 2.04. SiO2 deposition was done with optimized deposition rate of 24 nm /min at room temperaturewith refractive index ~ 1.58 and 21 nm/min at 250 0C with refractive index ~ 1.52.

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Fig. 5.2: Different device architecture used for study (a). Ag nanoparticles above anti reflection coating, (b). Ag nanoparticles just above SiO2 spacer layer, (c). SiO2 film deposited above Ag film for surface passivation, (d). Si3N4 anti reflection coating above Ag nanopaticles.

(a)

(c)

Different Device Geometry of Samples:

Geometry for Glass based samples (a). (b).

(c) (d).

Fig. 5.1: Schematic of the architecture followed for silver nanoparticles (NP’s) fabrication on glass substrate and onsilicon nitride coated (Si3N4) glass substrate (a). Ag thin film on glass substrate (b). Ag NP’s formed on glasssubstrate after annealing.(c). Ag thin film on silicon nitride coated (Si3N4) glass substrate (d). Ag NP’s formed onsilicon nitride coated (Si3N4) glass substrate after annealing.

Geometry for Si substrate based samples:

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Table 5.1: Different sample Ids for Si based substrate and their architecture:

Sample ID. Sample Architecture

Sample 1A Si/ Si3N4(80nm)Sample 1B Si/ Si3N4(80nm)/AgRTP

Sample 1C Si/Si3N4(80nm)/AgRTP/SiO2(20nm)Sample 1D Si/ Si3N4(80nm)/Ag/SiO2

RTP(20nm)Sample 1E Si/Si3N4(80nm)/SiO2(20nm)

Sample 2A Si/ SiO2(12nm)Sample 3A Si/ SiO2 (28nm) Sample 2B Si/SiO2(12nm)/AgRTP

Sample 3B Si/SiO2(28nm)/AgRTP

Sample 2C Si/SiO2(12nm)/AgRTP/Si3N4(80nm)sample 3C Si/SiO2(28nm)/AgRTP/Si3N4(80nm) Sample 2D Si/SiO2(12nm)/Si3N4(80nm)

Sample 3D Si/SiO2(28nm)/Si3N4(80nm)

sample 4A Si/ Si3N4(70nm)

sample 4B Si/Si3N4(70nm)/AgRTP

Results:Plasmonic Resonance tuning:

Fig. 5.3: SEM images of silver nanoparticles fabricated on glass substrate for different deposition times.

Fig. 5.4: UV –Visible spectra (Transmittance vs incident wavelength plot) for (a). silver (Ag) nanoparticlesfabricated on glass substrate (b). Silver (Ag) nano particles fabricated on silicon nitride coated (Si3N4) glasssubstrate.

Plasmonic effect of Ag nanoparicles on Si active absorber substrate based sample geometry:

Fig. 5.5: Plasmonic effect as seen on Si wafer based substrates.

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525 nm585 nm

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Fig. 5.6: UV –Visible spectra (a). Reflectance vs incident wavelength plot for Si, sample 1A, sample 1B, sample1C, sample 1D and sample 1E (b). Reflectance vs incident wavelength comparative plot for Si, sample 1A,sample 1B, sample 1C.

Fig. 5.7: UV –Visible spectra (a). Reflectance vs incident wavelength plot for for Si, sample 2A, sample 3A,sample 2B, sample 3B, sample 2C, sample 3C sample 2D, and sample 3D. (b). Reflectance vs incidentwavelength comparative plot for Si, sample 2C, sample 3C, sample 2D and sample 3D.

Conclusion:The results shown above shows that plasmonic resonance can be tuned which enables us to enhance light

absorption in photoactive absorbing material i.e. Silicon (Si) due to enhanced light trapping in a spectral regionwhich is most suitable for photovoltaic solar cells and also gives us the possibility to boost the efficiency of solarcells by implementing this emerging technology of plasmonics by optimization and well research for differentdevice architectures of Si based solar cells. Up to now we studied the effect of Ag film mass thickness on particleshape, size and distribution and their optical effect together with effect of spacer layer thickness on optical behaviorof Ag NP’s. Also effect on optical behavior for sandwiched Ag NP’s for two different device architecture. Weoptimized device architecture for Si based solar cell for using ARC and plasmonics both together. For bettercombined plasmonic and ARC effect we come to a conclusion that we should follow architecture asSi/Si3N4/AgRTP/SiO2 (as in Fig. 5.2(c)). It is seen that the reflectance can be reduced to zero for certain wavelengths.Further experiments are on-going to optimize the thickness of Si3N4, SiO2 and Ag nano particle properties (size,distribution and surface coverage). These would be subsequently integrated on solar cells.

Simulation and modelling of Plasmonic Effect: This section describes the first-year progress on the simulation of plasmonic solar cells.

Bench-marking simulations of standard solar cell structures were done and compared to data from theliterature to verify the semiconductor device simulator for PV applications – an example is shown in Fig.5.8.

Bench-marking electromagnetics simulations were done for light absorption and scattering by metallicnanoparticles and compared to experimental data. The light, i.e. electric field concentration effect isillustrated in Fig. 5.9.

Combined electromagnetics and semiconductor device simulations were set-up successfully to estimate theeffect of plasmonic structures (metallic nanoparticles) added to the standard solar cell; note that there is asyet very little in the literature on such combined simulations.

Initial results were obtained that indicate enhancement in efficiency over standard solar cells with metallicnanoparticles – this is shown in Fig. 5.10.

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Fig. 5.8: Simulation results for open-circuit voltage & short-circuit current (left) and efficiency (right) ofstandard silicon solar cell structure.

Fig. 5.9: Color-coded electric field values illustrate light concentration effect around a metallicnanoparticles.

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Fig. 5.10: (Left) Solar cell structure with one metallic nanoparticle (MNP) embedded in the SiN coating on thedevice. (Right) Plasmonic enhancement of carrier generation rate.

Work Planned for Next Year

The following activities are planned for next year

Parallelization of the electromagnetics part of the simulation will be explored to reduce the extremely largerun-times encountered at present.

Joint optimization of plasmonic structures and the rest of the solar cell will be carried out for achievingmaximal efficiency.

We will work with the experimentalists working on plasmonic solar cells as part of the “New Materials andDevices” research direction; experimental data will be used to refine the simulations and produce better-optimized device designs.

Conclusions

We have made a promising start in the direction of novel device structures with light-absorption engineering. Thesimulation set-up now available is capable of getting cell efficiency for these structures. Preliminary results showplasmonic enhancement, which will be optimized, in collaboration with experimentalists, over the course of theproject.

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Slicing of silicon wafers for PV applications using Wire Electric Discharge Machining (WEDM)

Students: Dongre G. G. and Cyrus Vesvikar

Faculty members: Suhas S. Joshi and Ramesh Singh

Introduction and Deliverables

Conventional methods used for silicon slicing that are inner diameter (ID) saws and wire saws. These methodscreate large mechanical contact forces while slicing the ingots that easily results in harmful surface micro-cracks orother damages to the wafer due to mechanical abrasive nature. However smaller wafer thickness is profitablebecause of the high material cost of mono-crystalline silicon. This also makes the slicing process an important topicto be re-examined and re-investigated.

The wire electrical discharge machining (WEDM) technology is adopted as a new candidate for silicon slicing to becompared with the existing procedures and testified if it can inevitably substitute for the ID saw or even competewith wire saws in some manufacturing orders. Thin and little geometrical error wafers are produced with thisprocess. High contact resistance on the ingot surface is solved by nickel-plating. The surface roughness, cuttingefficiency and micro-structures under different energy intensities are observed. However, the various parametriccorrelations and mechanism of cutting are not very well understood so far.

Project work has focus on the following deliverables:

Prototype of a wafer slicing machine based on WEDM technology Processes for slicing of 100 µm to 500 µm Silicon wafers from ingot

Wire-EDM process

The scheme of the wire-EDM process is as shown in Fig. 6.1. In this process a thin single-strand metal wire, usuallybrass, is fed through the work piece which is either submerged in a tank of dielectric fluid or dielectric is suppliedthrough nozzle.

Fig. 6.1: Schematic diagram of wire-EDM process.

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The wire is constantly fed from a spool and is held between upper and lower diamond guides. Due to the inherentproperties of the process, wire-EDM can easily machine complex parts and precision components out of hardconductive materials. The phenomenon of erosion is same in wire-EDM process however; the tool electrode takesthe form of a wire of generally Φ100 to 300 μm.

1. Timelinesmonths => 6 12 18 24 30 36

1 Facilities for crystalline Si cell fabrication

2 Cell fabrication process development

3Lab teaching module on cell fabrication and documentation for copy-exact model

4 Report writing

2. Progress made

Feasibility experiments and their analysis

Initial experimentation conducted at IIT Bombay, Machine Tool Lab, by using available micro wire-EDM setup (asshown in Fig. 6.2 below) for cutting silicon wafers to understand feasibility of the process, to measure the kerf lossand removal rates, and to observe the quality of cut surfaces as a function of process invariables voltage, capacitancewire feed rate, wire tension, polarity and dielectric fluid.

Fig. 6.2: Photograph of micro wire-EDM setup used for silicon cutting.

This experimental analysis has shown that wire-EDM is promising process for silicon cutting. In this process, thematerials removal rate increase with increasing capacitance. The dicing silicon produces minimum kerf loss of 27%if EDM oil is used as working fluid. However, if water is used as a working fluid, the kerf loss is more than 40%,see Fig. 6.3 a-b.

Tank

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1.010.0100.0400.00.01

0.01

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MRR in mm^3/sec

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Fig. 6.3. a. MRR Vs Capacitance Fig. 6.3. b. Kerf loss Vs Working fluid

Experimentation to analyse the parametric effects in dicing of 3” square polycrystalline silicon ingot using metallicwire-EDM process: Screening experiments were conducted on conventional wire-EDM. These experiments weresuccessful in slicing 3” square polycrystalline silicon ingot with the slicing rate of 1mm/min, it means it will take 75minutes to slice 3” silicon ingot. Fig. 6.4 shows the photograph of sliced wafer from silicon ingot.

Fig. 6.4: Silicon wafers cut by wire-EDM process

Parametric evaluation of process parameters in silicon slicing by wire-EDM process:

A CNC wire cut machine with distilled water as dielectric with submerged condition of cutting was used forconducting experiments. A 100µm diameter zinc coated brass wire as a tool electrode (cathode) and three inchsquare polycrystalline silicon ingot with resistivity 0.5 ohm-cm is used as a work piece. The scheme of cutting isshown in Fig. 6.6(b). Three inch silicon square polycrystalline silicon ingot is cut for a length of 5 mm with thethickness of wafer is 500 µm.

Silicon wafers cut from ingot by wire-

EDM

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Fig. 6.5: Theme of the experiment.

Table 1 Different control factors used with their level values

Variable CodingLevel

1 2 3

Pulse on time (µs) Ton 1 1.5 2

Pulse off time (µs) Toff 26.2 41.2 69

Voltage (V) V 10 23 35

Water Pressure (Kg/cm2) WP 4 5 6

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Fig. 6.6: (a) Experimental set up (b) Scheme of cutting

Analysis of cutting speed

The optimization experiments indicate that for higher slicing speed, higher levels of pulse on time (2.5 µs), lowerlevels of pulse off time (19.2 µs), voltage(40V) and water pressure (6 Kg/cm2) must be used. Fig. 6.7 illustrates thecomparison of time required to slice 3” silicon ingot by conventional methods and the proposed method.

Fig. 6.7: Comparison of time to slice 3” silicon ingot. Fig: 6.8. Comparison of kerf loss.

Analysis of kerf loss

It is evident from optimization analysis for kerf loss that in order to achieve smaller kerf area pulse on-time mustbe set at the minimum level that is at 0.5 µs, whereas the pulse off-time must be at maximum level that is at 104 µsand the values for the voltage is 5 V. Fig. 6.8 illustrates comparative assessment of kerf loss for existing andproposed method.

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Analysis of surface finish

Surfaces sliced by linear saw and wire saw show saw marks, marks of abrasives and micro-cracks due to mechanicalabrasion involved in the process (Fig. 6.9 a-b). Since, wire-EDM process does not involve mechanical abrasion; theresulting surfaces are free from saw marks.

Fig. 6.9: (a). Surface machined by wire saw, Ra: 3-4um.

Fig. 6.9: (b). Surface machined by WEDM, Ra: 2-3um.

Fig. 6.10 describes the comparative assessment of the surface roughness for the existing and proposed method ofsilicon ingot slicing. It shows the surface roughness is 30-40% lower than the conventional methods.

Fig. 6.10: Comparison of surface roughness on silicon wafers sliced by various techniques.

Experimental results for minimum wafer thickness of Si wafer sliced by wire-EDM process

Wire-EDM is a kind of non-contact slicing scheme, theoretically thinner wafer thickness can be achieved. In thepresent experimental setup wafer thickness can be reduced to less than 360μm with lower discharge energy.Experiments were also conducted at CMTI, Bangalore using 70 µm diameter wire. It was possible to get the waferthickness as minimum as 150 µm

Work planned for next year

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Various activities of the project planned for future work are as follows:

Development of experimental setup for minimisation of wafer thickness: This work involves developmentof experimental setup in order to accommodate various wire sizes preferably less than 100 μm in order toget minimum wafer thickness.

Detail study of process mechanics: Study of Voltage –Current characteristics, analysis of debris and effectof thermal spalling during cutting in order study process mechanism.

FEA based and Mathematical Modelling of silicon ingot slicing process: This work involves modelling ofeffect thermal spalling during slicing ingot slicing by wire-EDM process. Development of model forfracture mechanics of the process and validation of the same.

Advanced experiment in silicon ingot slicing: Analyse practicability for interfacing of ultrasonic vibrations,magnetic field application and hybrid machining capability in silicon ingot slicing process for better results.

Development of table top wire-EDM set up and detailed experimentation to understand the mechanism:Efforts are on with the Korean company Hybrid Precision, to develop dedicated wire-EDM machine whichwill have the facility of multi wire slicing.

3. Conclusions

Based on the two sets of experiment one on silicon wafer cutting by micro wire-EDM and slicing of 3” squarepolycrystalline silicon ingot by wire-EDM process following observations are made

Slicing process of silicon ingot have been optimized to provide maximum of slicing speed at the same timeminimizing the kerf loss and surface roughness of machined surface of silicon wafer.

In this experimentation minimum thickness of wafer achieved was 350 µm. The work has help to achieve the slicing rate of 1mm/min. At this rate slicing of one 3” square silicon wafer

requires 75 minutes. This slicing rate 50 % less than the conventional methods of silicon ingot slicing. Dimensional variation in the wafer thickness cut by wire-EDM process is about + 10 µm. This accuracy is 40-

50% higher than the conventional silicon ingot slicing methods.

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