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SEMI Press Conference Highlights Market Forecast, Economic ConditionsBY JEFF DORSCH
When Gordon Moore of Fairchild Semicon-
ductor published his famous article on chip
scaling and costs in 1965, gasoline in the U.S.
was 31 cents per gallon, the Dow Jones Indus-
trial Average was under 1,000, and a house
could be purchased for $13,000 or so, noted
Denny McGuirk, president and CEO of SEMI,
at Tuesday morning’s press conference open-
ing the SEMICON West 2015 conference and
exhibition.
It’s the 45th anniversary of SEMI itself and
the annual SEMICON show in Northern Cali-
fornia during 2015, he added.
Karen Savala, president of SEMI Americas,
reviewed SEMICON West events for this week
and new aspects of the show, such as the Career
Exploration Forum.
Dan Tracy, SEMI’s
senior director of in-
dustry research and
statistics, presented
the market forecast
for semiconductor
equipment and mate-
JULY 15, 2015
MOSCONE CENTER | SAN FRANCISCO, CALIFORNIA
WEDNESDAYSHOW DAILYSHOW DAILYSHOW DAILY9:00 am – 10:00 amKEYNOTE: The Internet of Things and the Next Fifty Years of Moore’s LawSPEAKER: Doug Davis, Senior Vice President, General Manager, Internet of Things Group, IntelMoscone North, Hall E, Room 135
10:30 am – 12:30 pmSubsystem and Component Suppliers at Critical Crossroads to Deliver on Yield and ProductivityTechXPOT South, South HallSESSION SPONSOR: Advanced Energy
1:30 pm – 3:30 pmPACKAGING: Auto Utopia: Gearing up Semiconductor to Turn Dreams to RealityTechXPOT North, North HallSESSION PARTNER: Meptec
2:00 pm – 4:30 pmSCALING TRANSISTORS: HVM Solutions Below 14nm; Getting to 5nmMoscone North, Hall E, Room 133SESSION SPONSOR: Lam Research
3:30 pm – 4:30 pmSILICON INNOVATION FORUM:INNOVATE KeynoteSPEAKER: Stephen Forrest, Ph.D., Professor, Dept. of Engineering, University of MichiganMoscone North, Hall E, Room 135
4:30 pm – 6:00 pmSilicon Innovation ReceptionInnovation Villagecontinued on p 3Denny McGuirk Karen Savala Dan Tracy
DON’T MISS
Keynote Panel: Challenges Abound for Sub-14nmBY PETE SINGER
Semicon West 2015 kicked off Tuesday morn-
ing with a keynote panel session that addressed
the challenges of “Scaling the Walls of Sub-
14nm Manufacturing.” The general consensus
was that future progress is dependent on better
coordination and collaboration between de-
sign, manufacturing and packaging companies
and people.
The panel consisted of Jo de Boeck, Se-
nior Vice President, Corporate Technology
at imec, who acted as the moderator; Gary
Patton, Chief Technology Officer and Head
of Worldwide Research and Development at
GLOBALFOUNDRIES; Michael Campbell,
Senior VP Engineering at Qualcomm; Calvin
Cheung, Vice President, Business Develop-
ment and Engineering at ASE and Subhasish
Mitra, Associate Professor, Dept. of EE and
CD at Stanford University.
Patton said the end of scaling was nowhere in
sight. “People have talked about the end of scal-continued on p 3
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SHOW DAILY
WEDNESDAY | JULY 15, 2015
3SHOW DAILY
rials. Foundry and memory chip manufacturers
will primarily drive this year’s growth for wafer
fabrication equipment, he said.
SEMI is forecasting capital equipment rev-
enue will reach about $40 billion worldwide this
year, with 8% growth for all equipment and 10%
growth for wafer fab equipment.
SEMI forecasts the market to expand an-
other 4% in 2016 to reach $41.8 billion.
The global materials market is predicted
to increase 4% in revenue this year, according
to Tracy, to $46 billion for all packaging and
semiconductor materials.
The SEMI executive focused on fan-out
wafer-level packaging, which will increase dra-
matically over the next four years, according to
TechSearch International. WLFO is primar-
ily meant for mobile applications, “driven by
consumer demand,” Tracy noted. Such con-
sumer products will
bring “a lot of pricing
pressure,” he added.
However, SEMI
forecast test equip-
ment, assembly and packaging equipment to
contract this year, falling to $3.5 billion (-3%)
and $2.8 billion (-9%), respectively.
Tracy also highlighted the currency situ-
ation presented by a strong dollar, which is
having adverse effects on the euro and the yen.
The Semiconductor Equipment Association
of Japan estimates 2014 billings grew by 37%
when measure in yen, and only 26% measured
in U.S. dollars.
Taiwan is forecast to continue as the world’s
largest spender with $10.9 billion estimated
for 2015 and $10.0 billion for 2016. In 2015,
South Korea is second at $8.6 billion, followed
by North America at $6.5 billion. For 2016,
these three regions are expected to maintain
their relative rankings.
In 2015, year-over-year increases are ex-
pected to be largest for South Korea (25%),
Taiwan (16%), Europe (14%), and Japan (13%).
Projected year-over-year percentage increases
for 2016 are largest for Europe (26% increase),
China (19%), South Korea (8%), and Rest of
World (7%).
ing. Scaling is not going to end. I am not worried
about solving the physics challenges,” he said.
“We have run into many barriers over the years
and we always find a way to get around it.
Patton said what worries him is doing it in
a way “that can deliver to our customers a real
value proposition for going to that next tech-
nology node. The cost of doing design in these
nodes is increasing at a pretty rapid rate and we
have to provide them with a return on invest-
ment. It’s becoming more challenging,” he said.
He noted that in the past most break-
throughs, such as high-k metal gates, took over
10 years in the research stage before they were
ready for manufacturing. That was one reason
behind the merger between IBM and GLO-
BALFOUNDRIES: access to 16,000 some
IBM patents. Pat-
ton also mentioned
IBM’s expertise in
a ASICs business,
differentiated IP, RF
technology – both
silicon germanium
as well as RFSOI – as
well as 3D and 2.5D
technologies.
Q u a l c o m m ’ s
Mike Campbell said
the biggest threat to
Moore’s Law is yield.
“Yield is now an end-
to-end question,” he
said. “That doesn’t just mean semiconductor
yield today. It’s the package yield on top of that
and then the systems yield.”
Campbell said he’d like to see that end-to-
end yield contained in a productivity model.
“If you have a 10nm or 7nm silicon piece and it
works to the spec at the silicon level, but then
we change the stress characteristics because we
have to saw and dice it up into a package. Then
we put it into a 2.5D or 3D package and change
the stress levels again. The yields change at ev-
ery level,” he said.
Campbell believes that the whole system
has to be interactive. “Until 28nm, you didn’t
need to have that interactivity. But as we go
deeper and deeper into submicron technol-
ogy, the interactivity between the package, the
system and the silicon itself—and the basic
R&D for the silicon – all have to start to play
together or else at the end we’ll end up with
gaps in the system which will then add cost
to the deliverables that we have to bring to the
marketplace,” he said.
ASE’s Calvin Cheung said the company’s
biggest concern was CPI (chip package inter-
action). “We are really pushing assembly and
test technology capabilities,” he said. “In the
case of 2.5D, we have connect a couple hun-
dred thousand interconnects and put them
on a very, very small space. With the scaling,
the die is getting smaller but your I/O density
continues to increase.”
Keynote continued from p. 1
SEMI Press Conference continued from p. 1
Show Daily StaffPublished by Solid State Technology,
an Extension Media company.
EXTENSION MEDIAVince [email protected]
Pete [email protected]
Jeff DorschContributing [email protected]
Ed KorczynskiContributing [email protected]
Shannon DavisContributing [email protected]
Kerry HoffmanAdvertising [email protected]
TRADESHOW MEDIA PARTNERSMark LarsonProduction and [email protected]
Kevin ClarkeLayout and [email protected]
The Keynote panel discussion focused on sub-14nm challenges.
SEMI is forecasting capital equipment revenue will reach about $40 billion worldwide this year
MOSCONE CENTER | SF, CA
4
Technologies for Advanced Systems Shown at imec Tech ForumBY ED KORCZYNSKI
Luc Van den hove, president and CEO, imec
opened the Imec Technology Forum - USA in
San Francisco on July 13 by reminding us of
the grand vision and motivation behind the
work of our industry to empower individu-
als with micro- and nano-technologies in his
talk, “From the happy few to the happy many.”
While the imec consortium continues to lead
the world in pure materials engineering and
device exploration, they now work on systems-
integration complexities with over 100 appli-
cations partners from agriculture, energy,
healthcare, and transportation industries.
We are now living in an era where new
chip technologies require trade-offs between
power, performance, and band-
width, and such trade-offs must
be carefully explored for differ-
ent applications spaces such as
cloud clusters or sensor nodes.
An Steegen, senior vice presi-
dent process technology, imec,
discussed the details of new
CMOS chip extensions as well as
post-CMOS device possibilities
for different applications spaces
in her presentation on “Technol-
ogy innovation: an IoT era.” EUV
lithography technology continues
to be developed, targeting a sin-
gle-exposure using 0.33 Numeri-
cal Aperture (NA) reflective lenses to pattern
features as small as 18nm half-pitch, which
would meet the Metal1 density specifications
for the industry’s so-called “7nm node.” Pat-
terning below 12nm half-pitch would seem
to need higher-NA which is not an automatic
extension of current EUV technology.
So while there is now some clarity regard-
ing the pre-competitive process-technologies
that will be needed to fabricate next-gener-
ation device, there is less clarity regarding
which new device structures will best serve
the needs of different electronics applications.
CMOS finFETs using strained silicon-doped-
with-Germanium Si(Ge) will eventually be
replaced by gate-all-around (GAA) nano-
wires (NW) using alternate-channel mate-
rials (ACM) with higher mobilities such as
Ge and indium-gallium-arsenide (InGaAs).
While many measures of CMOS performance
improve with scaling to smaller dimensions,
eventually leakage current and parasitic ca-
pacitances will impede further progress.
Figure 1 shows a summary of energy-vs.-
delay analyses by imec for all manner of devices
which could be used as switches in logic arrays.
Spin-wave devices such as spin-transfer-torque
RAM (STT-RAM) can run at low power con-
sumption but are inherently slower than CMOS
devices. Tunnel-FET (TFET) devices can be as
fast or faster than CMOS while running at lower
operating power due to reduced electrostatics,
leading to promising R&D work.
In an exclusive interview, Steegen explained
how the consortium balances the needs of all
partners in R&D, “When you try to predict
future roadmaps you prefer to start from the
mainstream. Trying to find the mainstream,
so that customers can build derivatives from
that, is what imec does. We’re getting closer
to systems, and systems are reaching down to
technology,” said Steegen. “We reach out to
each other, while we continue to be experts in
our own domains. If I’m inserting future mem-
ory into servers, the system architecture needs
to change so we need to talk to the systems
people. It’s a natural trend that has evolved.”
Network effects from “the cloud” and from
future smart IoT nets require high-bandwidth
and so improved electrical and optical connec-
tions at multiple levels are being explored at
imec. Joris Van Campenhout, program direc-
tor optical I/O, imec, discussed “Scaling the
cloud using silicon photonics.” The challenge
is how to build a 100Gb/s bandwidth in the
near term, and then scale to 400G and then
1.6T though parallelism of wavelength divi-
sion multiplexing; the best results to date for
a transmitter and receiver reach 50Gb/s. By
leveraging the existing CMOS manufacturing
and 3-D assembly infrastructure, the hybrid
CMOS silicon photonics platform enables high
integration density and reduced
power consumption, as well as
high yield and low manufac-
turing cost. Supported by EDA
tools including those from Men-
tor Graphics, there have been 7
tape-outs of devices in the last
year using a Process Design Kit
(PDK). When combined with
laser sources and a 40nm node
foundry CMOS chip, a complete
integrated solution exists. Arrays
of 50Gb/s structures can allow for
400Gb/s solutions by next year,
and optical backplanes for server
farms in another few years. How-
ever, to bring photonics closer to the chip in an
optical interposer will require radical new new
approaches to reduce costs, including integra-
tion of more efficient laser arrays.
Alexander Mityashin, project manager thin
film electronics, imec, explained why we need,
“thin film electronics for smart applications.”
There are billions of items in our world that
could be made smarter with electronics, pro-
vided we can use additive thin-film processes
to make ultra-low-cost thin-film transistors
(TFT) that fit different market demands. Us-
ing amorphous indium-gallium-zinc-oxide
(a-IGZO) deposited at low-temperature as the
Fig.1. Energy vs. delay for various logic switches. (Source: imec)
continued on p 6
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6
active layer on a plastic substrate, imec has
been able to produce >10k TFTs/cm2 using
just 4-5 lithography masks. Figure 2 shows
these TFT integrated into a near-field com-
munications (NFC) chip as first disclosed at
ISSCC earlier this year in the paper, “IGZO
thin-film transistor based flexible NFC tags
powered by commercial USB reader device
at 13.56MHz.” Working with Panasonic in
2013, imec showed a flexible organic light-
emitting diode (OLED) display of just 0.15mm
thickness that can be processed at 180°C. In
collaboration with the Holst Center, they have
worked on disposable flexible sensors that can
adhere to human skin.
Jim O’Neill, Chief Technology Officer of En-
tegris, expanded on the systems-level theme of
the forum in his presentation on “Putting the
pieces together - Materials innovation in a dis-
ruptive environment.” With so many additional
materials being in-
tegrated into new
device structures,
there are inherently
new yield-limiting
defect mechanisms
that will have to be
controlled. With de-
mand for chips now
being driven primar-
ily by high-volume
consumer applica-
tions, the time be-
tween first commer-
cial sample and HVM has compressed such
that greater coordination is needed between
device, equipment, and materials companies.
For example, instead of developing a wet chemi-
cal formulation on a tool and then optimizing
it with the right filter or dispense technology,
the Process Engineer can start envisioning a
“bottle-to-nozzle wetted surface solution.” By
considering not just the intended reactions on
the wafer but the unintended reactions that can
occur up-steam and down-stream of the pro-
cess chamber, full solutions to the semiconduc-
tor industry’s most challenging yield problems
can be more quickly found.
Fig.2. Thin-Film Transistors (TFT) fabricated on plastic using Flat Panel Display (FPD) manufacturing tools. (Source: imec/Holst Center)
Advanced Systems continued from p. 4
Results of Board Elections and Leadership Appointments
Announced by SEMISEMI announced yesterday that Stephen S. Schwartz, CEO of Brooks Automation, and Toshikazu Umatate, senior vice presi-dent and general manager of the Semiconductor Lithography Business at Nikon Corporation, were elected as new directors to the SEMI International Board of Directors in accordance with the association’s by-laws.
Four current board members were re-elected for a two-year term: Bertrand Loy, president and CEO of Entegris; Dave Miller, president of DuPont Electronics & Communications; Kyu Dong Sung, CEO of EO Technics; and Xinchao Wang, chairman and CEO of JCET.
Additionally, the SEMI Executive Committee confirmed Yong Han Lee, chairman of Wonik as SEMI Executive Commit-tee chairman, and Tetsuo Tsuneishi, chairman of the Board of Tokyo Electron, Ltd. as SEMI vice-chairman.
The leadership appointments and the elected board mem-bers’ tenure become effective at the annual SEMI member-ship meeting on July 15, during SEMICON West 2015 in San Francisco, California.
“These two distinguished industry leaders will be tremen-dous assets to the SEMI Board of Directors,” said Denny Mc-Guirk, president and CEO of SEMI. “We also appreciate the continued service of those re-elected to the Board — their counsel and wisdom is valued as SEMI responds to new indus-try challenges, inflections, and opportunities.”
SEMI’s 19 voting directors and 11 emeritus directors rep-resent companies from Europe, China, Japan, Korea, North America, and Taiwan, reflecting the global scope of the asso-ciation’s activities. SEMI directors are elected by the general membership as voting members of the board and can serve a total of five two-year terms.
SEMICON Daily Ad Layout-Plasma-Therm.indd 1 7/1/2015 11:36:14 AM
semi_show_2.indd 1 22/06/2015 15:46:54
MOSCONE CENTER | SF, CA
8
Fan-out Wafer Level Packaging Set to ExpandBY PETE SINGER
The expansion of fan-out is finally coming,
says Rich Rogoff, Vice President and General
Manager, Lithography Systems Group at Ru-
dolph Technologies.
Wafer level packaging (WLP) using fan-out
technology is an attractive platform for achiev-
ing low-cost low-profile package solutions for
smart-phones and tablets, which require cost-
effective, high-density interconnects in small
form-factor packaging.
It was originally introduced by Infineon
in the fall of 2007. Called eWLB, or embed-
ded wafer-level ball grid array technology, it
enables all operations to be performed highly
parallel at wafer level. In August of 2008, ST-
Microelectronics, STATS ChipPAC, and Infi-
neon signed an agreement to jointly develop
the next-generation eWLB, based on Infine-
on’s first-generation technology.
Assembled directly on a silicon wafer, the
approach is unconstrained by die size, provid-
ing the design flexibility to accommodate an
unlimited number of interconnects between
the package and the application board for max-
imum connection density, finer line/spacing,
improved electrical and thermal performance
and small package dimensions to meet the re-
lentless form factor requirements and perfor-
mance demands of the mobile market.
STATS ChipPAC’s eWLB high volume
manufacturing process, for example, today
includes automated wafer reconstitution (in-
cluding wafer-level molding), redistribution
using thin film technology, solder ball mount,
package singulation and testing. Incoming wa-
fers in both 200mm and 300mm diameters can
be supported.
According to a recent report from Yole
Développement, the fan-out WLP (FOWLP)
market will reach almost $200M in 2015, with
30% CAGR in the coming years. Yole analysts
say FOWLP started volume commercializa-
tion in 2009/2010 and started promisingly,
with an initial push by Intel Mobile. However,
it was limited to a narrow range of applications,
essentially single die packages for cell phone
baseband chips. In 2012 big fabless wireless/
mobile players started slowly volume produc-
tion after qualifying the technology.
It faced strong competition from other
packaging technologies, such as wafer-level
chip scale packaging (WLCSP) in 2013/2014.
Intel Mobile also backed off from the technol-
ogy, and the main manufacturers reduced their
prices in 2014, creating a transition phase with
low market growth.
Strong growth is now expected, hoped in
part by the arrival of 2nd generation FOWLP.
“Benefiting from the delay in introducing
3D through-silicon via (TSV) architectures,
FOWLP is currently seen as the best fit for the
highly demanding mobile/wireless market and
is attractive for other markets focusing on high
performance and small size”, explains Jérôme
Azemar, Technology & Market Analyst, Ad-
vanced Packaging & Manufacturing, Yole
Développement.
Rudolph’s Rogoff believes it will be imple-
mented in a wafer form for the next year or two,
but will ultimately transition to a panel-based
approach. “The big question for the industry is
are they going to move to panels?” Rogoff asked.
“From a lithography perspective, the tools are
ready today. As the demand goes up, there will
be a push also for a switch,” he said. “Develop-
ment of panels has already started and will con-
tinue to increase in activity over the next year.”
In an article in Solid State Technology pub-
lished in 2014, titled “A square peg in a round
hole: The economics of panel-based lithogra-
phy for advanced packaging,” Rogoff said mov-
ing from round wafers to rectangular panels
(“panel-ization”) saves corner space, delivering
a roughly 10% improvement in surface utiliza-
tion. The larger size of the substrate and the
improved fit between the mask and substrate
reduce the transfer overhead by a factor of 5.
The potential reduction in throughput resulting
from an increase in the number of alignment
points is more than offset by the improvements
in throughput. Compared to a 1X stepper on
wafers, panel-based processes can reduce li-
thography cost per die by as much as 40%.
One of the advantage of Rudolph Technolo-
gies’ JetStep Panel System (JetStep S3500)
is that it can handle such rectangular panels.
Both the panel and wafer 2X reduction step-
pers offer many advantages — based in part on
Azores’ 6700 platform which was developed
for LCDs — including the largest printable
field-of-view, programmable aperture blades
and large on-tool reticle library, large depth-
of-focus along with autofocus to accommodate
3D structures in advanced packaging, very
large working distance, and warped substrate
handling (+/- 6mm). The wafer system (JetStep
W2300) features programmable wafer edge
protection, enabling a variable edge exclusion
zone of 0.5-5 mm. The systems also feature a
large (17mm) working distance between the
lens and the substrate, which helps avoid a
common maintenance issue on 1X systems.
Rogoff said the ability to handle warped wa-
fers is increasingly important. “We’ll always
be putting the best focus point in the middle of
our depth of focus range. If there’s any varia-
tion due to substrate warp, we can go up a little
and down a little and we’re still going to be in
focus,” he said.
The large working distance helps eliminate
problems with thick resists, which can outgas
and potentially contaminate the lens. “We’re
so far away — and we also have some purging
in the area — we don’t have that issue. The less
you have to take the machine down to clean it,
the better,” he said.
When it comes to fan-out, the challenge is
being able to manage the overlay performance
over a large field area. “Our competitors like to
say it can’t be done, yet we prove it can,” Rogoff
said. “The larger the field is, the more die you
get in it, so the more variations you’re likely to
see. With our ability to correct for intrafield
parameters, we can extract out that variation
so what’s left is just random noise.”
If the random noise gets too high, another
solution Rudolph can provide is a combination
of stepper modeling capability with inspection.
“You can measure the die placement on a high
speed inspection tool, throw that data into the
modeling software and spit out the stepping
model for the stepper,” Rogoff explained. “This
is something we’re continuing to develop. The
first round is available and as the fan-out tech-
nology gets more complex, we’re continuing to
expand on that.”
SHOW DAILY
WEDNESDAY | JULY 15, 2015
9SHOW DAILY
Caption
CEA-Leti and EV Group launched a new pro-
gram in nano-imprint lithography (NIL) called
INSPIRE to demonstrate the benefits of the
nano-patterning technology and spread its use
for applications beyond semiconductors.
In addition to creating an industrial part-
nership to develop NIL process solutions, the
INSPIRE program is designed to demonstrate
the technology’s cost-of-ownership benefits for
a wide range of application domains, such as
photonics, plasmonics, lighting, photovoltaics,
wafer-level optics and bio-technology.
Leti and EVG will jointly support the
development of new applications from the
feasibility-study stage to supporting the first
manufacturing steps on EVG platforms and
transferring integrated process solutions to
their industrial partners, thus significantly
lowering the entry barrier for adoption of NIL
for manufacturing novel products.
In its effort to support high-volume manu-
facturing applications, EVG recently launched
the HERCULES® NIL equipment platform,
and the INSPIRE program’s activities will
complement the company’s efforts within the
framework of its NILPhotonics™ competence
center that was launched in December 2014.
“EVG is excited about the value that the
partnership with Leti in the INSPIRE pro-
gram will provide to industry,” said Markus
Wimplinger, corporate technology develop-
ment and IP director at EV Group. “After more
than a decade of research and development
activities, EVG has propelled NIL technology
to a level of maturity that enables significant
advantages for certain applications compared
to traditional optical lithography.”
After launching its NIL technology-devel-
opment program more than 10 years ago, Leti
oriented the use of this technology mainly for
photonics applications. In early 2014, the pro-
gram was integrated in the Silicon Technolo-
gies Division to establish a NIL collaborative
program.
“Leti and EVG have a long history of col-
laborating on ways to bring new technologies
to market at reasonable costs for the benefits
of our customers,” said Laurent Pain, pat-
terning program manager in Leti’s Silicon
Technologies Division. “Through INSPIRE,
we will develop new ways for them to use this
flexible, powerful nano-patterning technol-
ogy to create new products for a wide range
of applications.”
Leti and EVG Launch INSPIRE
EVG’s nanoimprint lithography system
■ Scanning Probe Microscopy■ Selective Deposition as an Enabler of Self-Alignment■ Spectroscopic Ellipsometry■ Surface Modification of Materials by Plasmas for Medical Purposes■■ Tribology
FOCUS TOPICS & OTHER SESSIONS■ 2D Materials■ Accelerating Materials Discovery for Global Competitiveness■ Actinides & Rare Earths■ Additive Manufacturing/3D Printing■■ Atom Probe Tomography■ Energy Frontiers■ Exhibitor Technology Spotlight■ Helium Ion Microscopy■ In-Situ Spectroscopy & Microscopy■ IPF on Mesoscale Science and Technology of Materials and Metamaterials■■ Materials Characterization in the Semiconductor Industry■ Novel Trends in Synchrotron & FEL-Based Analysis
DIVISION/GROUP PROGRAMS■ Advanced Surface Engineering■ Applied Surface Science■ Biomaterial Interfaces & Biomaterials Plenary■ Electronic Materials & Processing■ Magnetic Interfaces & Nanostructures■■ Manufacturing Science & Technology■ MEMS and NEMS■ Nanometer-scale Science & Technology■ Plasma Science & Technology■ Surface Science■ Thin Films■ Vacuum Technology
Details available at www.avs.org
Housing Deadline: September 25, 2015Early Registration Deadline: September 28, 2015
Addressing cutting-edge issues associated with materials, processing, and interfaces in both the research and manufacturing communities. The weeklong Symposium fosters an environment that cuts across traditional boundaries between disciplines and features:
October 18-23, 2015 | San Jose Convention Center | San Jose, CA
AVS 62ND INTERNATIONALSYMPOSIUM & EXHIBITION
10
Gases: Completely Necessary to Semiconductor ManufacturingBY JEFF DORSCH
Silicon wafers. Semiconductor packaging. These
are commonly known products in materials for
manufacturing and assembling microchips.
Process gases? Not as familiar a commod-
ity, yet they are just as critical to semiconductor
manufacturing.
Some of the biggest gas suppliers have re-
ported greater profits this year, while revenues
have declined for certain companies, largely
due to the strength of the U.S. dollar against
other currencies.
Air Liquide reported revenue in its Gas &
Services segment was up by 6.3 percent in the
first quarter, while its Electronics grew rev-
enue 14.4 percent compared with a year ago.
“Sales were particularly vigorous in China, in
Taiwan, in Japan, and in the United States,”
the company said in a statement.
For its fiscal second quarter ended March
31, Air Products & Chemicals reported net
income was up 19 percent from a year earlier
to $336 million, while sales declined 6 percent
to $2.415 billion. “Volumes increased four per-
cent, primarily in Industrial Gases-Asia and
Materials Technologies, and pricing was up
one percent,” the company stated. Industrial
Gases-Asia had a 7 percent increase in sales
during the quarter, to $393 million. “Elec-
tronics Materials sales were up 16 percent on
strong volume growth in all business units and
positive price,” Air Products said.
Praxair reported first-quarter net income
of $416 million. Sales were $2.757 billion,
down 9 percent from a year earlier, due to the
impact of negative currency translation. The
company is forecasting 2015 revenue of $11.4
billion to $11.7 billion.
Financial results from the quarter ended
June 30 will be reported later this month.
“The quantity and number of gases are in-
creasing quite dramatically,” says Anish Tolia,
head of global marketing for Linde Electron-
ics, part of the Linde Group. “Fabs are getting
larger, clustered in one location. The amount
of gas per wafer is increasing.”
Some of the increases in gas usage are due
to double patterning and multiple patterning
in lithography steps, according to Tolia. “More
tools, more gas,” he observes.
Nitrogen is the most-used gas, typically
employed for purging of pumps and vacuum
chambers, Tolia notes. “It is also used as a pro-
cess gas,” he says. Wafer fabrication facilities
making chips with 28-nanometer or 20nm fea-
tures can go through 20,000 to 30,000 cubic
meters in an hour.
Hydrogen is another significant commodity
gas, Tolia says. “Extreme-ultraviolet lithogra-
phy will boost its use,” he adds.
continued on p 15
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SHOW DAILY 11SHOW DAILY
Is Silicon’s Heyday Over? New Materials Challenge the Industry WorkhorseBY JEFF DORSCH
The short answer to that headline’s question
is “no.” Longer term, in going beyond the
5-nanometer process node, silicon may finally
reach the end of its usefulness to the semicon-
ductor industry.
SEMI estimates the worldwide semicon-
ductor materials market grew 3 percent in
2014 to $44.3 billion, compared with 2013’s
$43.05 billion. The 2014 total was composed
of $24.0 billion in wafer fabrication materials
and $20.4 billion in packaging materials. Tai-
wan last year remained the world’s largest con-
sumer of semiconductor materials, accounting
for $9.58 billion in sales, an 8 percent increase
from the prior year’s $8.91 billion.
SEMI’s Silicon Manufacturers Group re-
ports silicon wafer area shipments increased
11 percent in 2014 to 10,098 million square
inches, as against 9,067 MSI in 2013. Rev-
enues, however, grew only 1 percent year-to-
year, to $7.6 billion from $7.5 billion, still far
below the 2007 peak of $12.1 billion.
Researchers around the world are constantly
investigating materials that could be the suc-
cessor to silicon. Molybdenum disulfide shows
promise. Graphene, the “wonder material” with
many exciting attributes, is difficult to employ
as a semiconductor material due to its lack of
a bandgap, although bandgaps can be found
in bilayer graphene or graphene nanoribbons.
Closer at hand are silicon carbide and the
III-V materials, such as gallium arsenide and
gallium nitride.
Scott Balaguer, Edwards’ president of the
U.S. & Europe Semiconductor Business Unit,
observes, “Chemistries, gas flows and materi-
als are constantly changing across numerous
applications and design nodes. We see these
innovations in both silicon and compound
semiconductor technologies. A great example
is the new prototype SiC line at SUNY Poly-
technic Institute that General Electric is driv-
ing in Albany, New York.
“The rate and pace of 10nm development is
picking up and 14nm HVM fabs continue to im-
prove and efficiencies and achieve higher yields.
“Clearly the rate of EUV adoption has
Researchers around the world are constantly investigating materials
that could be the successor to silicon.
continued on p 14
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Buying Used Equipment? Be Careful; Know Your SellerBY JEFF DORSCH
The used and refurbished semiconductor
equipment market can be a hazardous business
for buyers. The watchword always is: Caveat
emptor — let the buyer beware.
There are many reputable companies in
the used equipment business, of course. Intel,
Texas Instruments, and other big chipmakers
put their surplus production equipment on the
market, typically on an “as-is” basis.
Some used-equipment vendors and bro-
kers also offer their wares as they are, with-
out any guarantees or warranties. The chip-
making gear may be faulty; it could lack a
software license from the original equipment
manufacturer, which has occasionally been a
legal issue.
Many purveyors of used equipment are
also involved in refurbishing pre-owned
equipment, and some even develop their own
equipment, given their experience in buying,
maintaining, updating, and selling equipment.
“It’s an interesting year. The industry has
been very busy,” says Byron Exarcos, CEO of
ClassOne Equipment, which is based in At-
lanta and has operations around the world in
key markets. “There definitely is a lack of sup-
ply, versus demand. It has driven pricing up.
”It’s become very difficult to find equip-
ment, especially 200-millimeter equipment,”
he adds. “There’s a very tight supply and high
demand, which invariably increases prices.”
Dave Pawlak, ClassOne’s vice president of
purchasing, says the supply-and-demand situ-
ation has lately improved. The market is seeing
“a slowdown” after a torrid period of activity,
he adds. “Tools are becoming available. We’re
starting to see a turn. The prices are coming
down,” Pawlak observes.
Driving the demand for 200mm tools are
manufacturers of microelectromechanical sys-
tem devices and sensors, according to Exarcos.
Light-emitting diodes are typically manufac-
tured on 150mm wafer fabrication lines.
“They may have been using 3-inch, 4-inch
tools,” he says of these manufacturers. “Eight-
inch tools — they’re the leading edge.”
While Intel and Samsung Electronics are
fabricating their most advanced chips on
300mm fab lines, those integrated device
manufacturers (both of who are in the foundry
business) are “keeping their 200mm tools,” Ex-
arcos says. “They’re getting busy with them.”
In February, ClassOne Technology an-
nounced the acquisition of two product lines, a
spin-rinse-dryer and a spray solvent tool, from
Microprocess Technologies. Those products
became the company’s Trident SRD and Tri-
dent SST lines.
Exarcos concludes, “It is critical to work
with the right company.”
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SHOW DAILY 13SHOW DAILY
Deposition Equipment Market Witnesses a Year of Significant ChangesBY JEFF DORSCH
There are four main segments in the thin-
layer deposition equipment market — atomic
layer deposition, chemical vapor deposition,
epitaxy, and physical vapor deposition, also
known as sputtering.
As the semiconductor industry powers
through the 14nm process generation, interest
is keen on how researchers and suppliers will
improve the current crop of deposition equip-
ment to meet the requirements of the 10nm
and 7 nm nodes.
The long-pending merger of Applied Mate-
rials and Tokyo Electron into a company to be
called Eteris, called off in April due to regula-
tory issues, would have created a mighty depo-
sition vendor, holding nearly 60% of the world-
wide market. Applied still holds a commanding
share of the deposition market, yet will have to
contend with Lam Research
(which acquired Novellus
Systems in 2012), AIX-
TRON, ASM International,
and other competitors.
Global Industry Analysts
(GIA) forecasts the global
deposition equipment mar-
ket will hit $13.6 billion by
2020. Atomic layer deposi-
tion (ALD) will be the fastest
growing segment, with a com-
pound annual growth rate of
19.9 percent, the market research firm estimates.
Chemical vapor deposition (CVD) will be
the second largest deposition segment through
the end of this decade, followed by physical va-
por deposition (PVD) and epitaxy, according to
GIA. Japanese vendors, namely Hitachi Koku-
sai Electric/Kokusai Semi-
conductor Equipment and
Tokyo Electron, dominate
the worldwide CVD mar-
ket, with significant market
shares held by Applied Mate-
rials, ASM International, and
Lam Research, the market re-
search firm states.
Taiwan is the world’s larg-
est market for deposition
equipment, Global Industry
Analysts says. That’s not
surprising, since SEMI estimates that Tai-
wanese semiconductor manufacturers will
spend about $10.5 billion on wafer fabrication
equipment this year, representing nearly 30
percent of worldwide spending on fab equip-
continued on p. 14
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ment in 2015. GIA sees China being among
the fastest-growing markets for deposition,
with a CAGR of 15.1 percent.
In May, Applied Materials introduced the
Applied Endura Cirrus HTX PVD system
for making titanium nitride hardmask films,
targeting applications in fabricating semi-
conductors with 10nm and 7nm features.
A year ago at SEMICON West, the com-
pany debuted the Applied Producer XP Pre-
cision CVD system and Monday of this week
saw the launch of the Applied Olympia™
ALD system featuring a unique, modular
architecture that delivers high-performance
ALD technology.
July of 2014 also saw Lam Research unveil
its VECTOR ALD Oxide system to produce
conformal dielectric films defining critical
pattern dimensions in multiple patterning.
SEMICON West 2015 is expected to
see announcements on new products and
research in the deposition equipment field.
gained momentum as source performance
and throughput has improved. It is not a ques-
tion of if, it is just when,” Balaguer says.
Thomas Piliszczuk, senior vice president
of marketing, business development, and
global sales for Soitec, says radio-frequency
silicon-on-insulator technology is becoming
mainstream and has seen “huge growth over
the past several years.” He adds, “SOI is today
in 99 percent of smartphones.”
On the fully-depleted silicon-on-insulator
front, the industry today is at a tipping point
with strong industry support and a growing
ecosystem. The low-power, significant per-
formance, and cost benefit attributes of FD-
SOI are making the technology attractive for
mobile, wearable devices, and the Internet of
Things, as well as automotive and networking
applications, according to Piliszczuk. “FD-
SOI is a cheaper solution, overall,” he says.
The executive looks for it to soon become “a
very high-volume market.”
“The ecosystem now sees SOI not as a
niche any more, but as a robust technology
for many consumer applications,” Piliszczuk
concludes. Shin-Etsu Handotai and SunEdi-
son Semiconductor have joined Soitec as SOI
wafer suppliers.
EUV and immersion lithography are ex-
pected to usher in the 7nm and 5nm process
nodes. What happens past N7 and N5?
An Steegen, senior vice president of pro-
cess technology for imec, looks ahead to
nanowires and high-mobility channels in
semiconductors of the future. Those nanow-
ires will be made of silicon or silicon germani-
um, she says, with germanium in the channel.
That technology will have its drawbacks, she
acknowledges. “One nanowire will never beat
the performance of one FinFET,” Steegen says.
IBM Research has touted the future use of
carbon nanotubes in transistors.
So, don’t write off silicon for now. The old
reliable material may have years of useful-
ness ahead.
Deposition Equipment continued from p. 13Silicon’s Heyday continued from p. 11
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SHOW DAILY 15SHOW DAILY
CoorsTek Increases its Business with Covalent Acquisition, Organic GrowthBY JEFF DORSCH
CoorsTek made one of the biggest acquisitions
of its century-long history late last year in pur-
chasing Covalent Materials, formerly known
as Toshiba Ceramics.
Jonathan Coors, CEO of the company’s
Semiconductor and Medical Group, said Tues-
day the Covalent acquisition was “really strate-
gic for us. It enhanced the company as a whole.”
CoorsTek’s Japan market share in engineered
ceramics was “relatively small prior to Cova-
lent,” Coors noted. Covalent broadened Coor-
sTek’s product portfolio in carbons, quartz, and
silicon products, according to Coors.
CoorsTek plans to pursue both organic
growth in its business and acquisition opportu-
nities as they present themselves, the CoorsTek
executive said.
Asked whether privately held CoorsTek may
pursue a public offering, Coors said, “We enjoy
being private.” That status offers some “regu-
latory ease,” he noted.
As a private company, CoorsTek is able to
engage in a “long-term thought process, while
maintaining focus on quarterly performance,”
Coors added.
CoorsTek also provides orthopedic implants,
such as hip and knee replacements. Medical
products present “a demand on quality that
is as high (as semiconductor products), if not
higher,” Coors noted. There is a “similar sup-
ply chain” in the two product lines, he stated.
Coors and other CoorsTek executives are
meeting this week with customers to learn
“where the market is heading,” Coors said.
Such information gleaned at SEMICON West
2015 can point to “the next generation of
growth,” he said.
Process gases are in demand for etch-
ing and deposition, particularly in chemi-
cal vapor deposition, and less so in physi-
cal vapor deposition, according to Tolia.
The semiconductor industry is a
“strong consumer” of helium, a cooling
gas, Tolia says. “Supply has improved,” he
notes, with the U.S. Bureau of Land Man-
agement maintaining a helium reserve. “A
few new sources have been developed; the
pressure is off,” he adds.
Helium, which comes with natural gas,
is not a renewable resource, Tolia notes.
“It’s not a gas from air,” he says.
With on-site supply, “as close to their
fabs as possible,” Linde Electronics is bet-
ter able to serve its customers, Tolia says,
with “minimized leadtimes, quick trouble-
shooting, quick response to disasters.”
Gases are essential to the semiconduc-
tor industry. Have you thanked a gas sup-
plier lately?
Gases continued from p. 10
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16
New Materials Require New ApproachesBY PETE SINGER
Continued advances in the semiconductor will
increasingly be enabled by materials technol-
ogy, versus the scaling that has been com-
monplace over the last 50 years as defined by
Moore’s Law. Yet new materials technology will
itself create new challenges, not only in terms
of deposition, etching, cleaning, planarization
and cleaning, but in terms of handling. “I like
to at materials within the context of what a lot
of people are describing as the inflection points
in the industry,” said Jim O’Neill, Chief Tech-
nology Officer at Entegris. “Most materials
innovations and new material introductions
have been associated with those.”
O’Neill joined Entegris in 2014 as part of
the ATMI acquisition. Prior to that, he was
director of 14nm technology development at
IBM where he led process development activi-
ties at both Albany Nanotech and East Fishkill
facilities.
“Historically, Moore’s Law has really been
about miniaturization, but we’ve run into pat-
terning limitations with wavelengths,” O’Neill
said. “We’ve run into mobility
problems with the channel ma-
terials we now have. In order to
maintain the spirit of Moore’s
Law, materials have really been
front and center.”
Today, materials are being driv-
en most aggressively by multi-pat-
terning: “There’s been a class of
materials that have been increas-
ingly emphasized in terms of low
temperature silicon for the whole
patterning stack,” O’Neill said.
Another key area is the device architecture
and the transition from planar to 3D struc-
tures, such as finFETs on the transistor side,
and 3D NAND on the memory side. “This has
put an increased emphasis on deposition and a
transition from CVD to ALD type precursors,”
O’Neill said. “Also, very specific materials such
as fluorine-free tungsten, for example, for 3D
NAND.”
New high mobility chan-
nel materials are also needed
in the frontend. In the back
end, there’s whole class of
new materials being intro-
duced for interconnects and
metallurgies to try to im-
prove RC delay performance
and reliability, including co-
balt and ruthenium.
One of the biggest chal-
lenges with introducing
these new materials is that the infrastructure
that surrounds them needs need approaches.
“What you end up having to do — and what’s
so disruptive to our customers — is change
the whole integration scheme,” O’Neill said.
Jim O’Neill, CTO of Entegris
SHOW DAILYSHOW DAILY
In the case of cobalt, for example, clean processes and post-polish pro-
cess have need to be cobalt-compatible. “You’re not just putting in a
new CVD material. You’re putting in that material and changing the
enabling infrastructure that surrounds it. That’s a real challenge for our
customer, the process integrators and the fab folks. But for us it creates
a great opportunity,” O’Neill added.
O’Neill said Entegris’ deposition business is growing, driven to some
degree by the increased need for ALD materials for 3D structures, which
is the ATMI part of the business. But there are also new challenges in
handling those materials. “Many of the precursors that we’re dealing
with are solids. The whole challenge of handling solid materials and
deriving a gas from a solid that ends up delivering a film on a wafer goes
beyond the material itself and deals with the container: Its filtration,
its handling. Those are really expertises of the traditional Entegris,”
O’Neill said.
Entegris is now working on capabilities that would take the solid
precursor in a delivery vessel with the appropriate filtration to remove
any entrained particulates in the delivery stream, then sensor monitor
capabilities to ensure that there is feed gas flow. “That’s really an entire
materials delivery solution focused on enablement and no defectivity,”
O’Neill said.
Yesterday, at SEMICON West, Entegris announced the release of
Torrento X Series 7 nm filters with FlowPlane linear filtration technology
(photo). FlowPlane is the semiconductor industry’s first scalable, linear,
high-flow filtration platform enabling advanced wet cleaning applica-
tions for the 10 nm node and beyond. The first in a series of filters based
on the linear filtration technology, the FlowPlane S model is designed
for point of dispense (POD) applications, enabling improvements in
both on-wafer defectivity and yield for critical wet cleaning applications.
“We’ve reached an inflection point where filter design must evolve
to meet the needs of the most complex semiconductor manufacturing
processes,” said Entegris Vice-President of the Liquid Microcontami-
nation Control business unit, Clint Haris. “A filter is the last line of de-
fense to prevent defect-causing
contaminants from reaching
the wafer. Our smaller, more
powerful filtration solution
will enable our customers to
effectively implement their 10
and 7 nm technology nodes.”
Torrento X series 7 nm fil-
ters with FlowPlane linear fil-
tration technology improve re-
tention and increase flow rate
performance by 100% com-
pared to similarly sized radial
filters. Moreover, FlowPlane
users will benefit from the for-
mat’s smaller device footprint
as well as improved wafer de-
fectivity performance.Torrento® X Series 7 nm Filtration with FlowPlane Linear Technology
WEDNESDAY | JULY 15, 2015
17
MOSCONE CENTER | SF, CA
18
Managing Hazardous Process Exhaust in High Volume ManufacturingBY PETE SINGER
“Let no element on the periodic table go un-
used!” That may well be the rallying cry of the
semiconductor industry moving forward. One
problem is that many of the new materials be-
ing considered are flammable, corrosive, toxic,
pyrophoric, carcinogenic and/or hazardous
in general.
“We’re all familiar with silane and hydrogen
as flammable materials, but there are many
other materials finding their way into manufac-
turing,” said Andrew Chambers, a Technical
Manager at Edwards Ltd. “Disilane springs
to mind, which is extremely hazardous and
flammable.”
In various manufacturing process such as
CVD and etch, materials are introduced into
the tool as gases, liquids and solids. They react
with each other and what’s on the wafer, and
byproducts are pumped out of the chamber
and into exhaust pipes. They are often diluted
and treated by a gas abatement system, and
ultimately vented to the atmosphere.
One of the biggest concerns in the fab is
with flammable gas and the catastrophic dam-
age that a fire could cause in the fab or sub-fab
to equipment and, of course, to personnel.
“If you have an exhaust pipe with flammable
materials in it, it’s routine to dilute them with
nitrogen to keep the concentrations below their
lower flammable limit,” explained Chambers.
“So even if there’s an escape to the environ-
ment, it can’t be ignited.”
A pending problem is that as process gas
flows increase, more flammable materials
such as hydrogen, silane and disilane are be-
ing used. “The amount of nitrogen you need to
put into the exhaust pipe to dilute it to a safe
level becomes extremely large,” Chambers
said. “That has a number of consequences.
The consumption rate increases significantly.
While nitrogen in itself is not that expensive
of a commodity, as you start to approach the
nitrogen generation limit of your plant, it sud-
denly gets a lot more expensive if you have to
get into extending the nitrogen supply infra-
structure in your fab.”
In addition, the point of use abatement sys-
tem on the end of your exhaust pipe has to be
correspondingly large to deal with the very large
volume of nitrogen that goes into the front of it.
“The abatement of process gases in high dilu-
tion flows is very inefficient. The consequence
of that is not only are you using a lot of nitro-
gen, but you’re having to buy very much more
gas abatement capacity than you need. With
that goes the additional expense of installing
the equipment, providing it with water, natural
gas, electrical power and so on,” Chambers said.
Edwards is presently exploring alterna-
tives to using a gas dilution strategy to ensure
safety. “We have imaginative ways of keeping
the operation of the exhaust pipe safe, while
reducing the cost of doing that. This includes
treating the gas pipe as part of an entire inte-
grated sub-fab system that is comprised of the
vacuum pumps, the exhaust pipe, the
end-of-pipe abatement system and
the support infrastructure that goes
with that. We would put in place mea-
sures so that the flammable gas is not
diluted to the same level that they are
accustomed to, but the safety of that
gas is assured by doing a number of things. It
might be that the concentration in the exhaust
pipe is higher than its lower flammable limit,
but that in itself is not a problem providing you
keep air or oxygen or other oxidants out of the
pipe at the same time,” Chambers explained.
Chambers said those kinds of ideas are start-
ing to get some traction, because it allows the
end user to regulate nitrogen consumption, re-
duce the amount of abatement capacity needed
and generally provide a lower cost of ownership.
Clearly, properly assembled exhaust pipes
with conventional joint seals will exclude air
from exhausts containing flammable gases, but
the operational risk is assurance of exhaust pipe
integrity through years of continuous operation
and numerous invasive service interventions.
He said that a unified process exhaust design,
with a clearly identified owner responsible for
safe operation and servicing and appropriate
integrated safety features, provides assurance
of exhaust system integrity during prolonged
operation, including routine servicing.
The same argument applies to process
gases which may not be flammable but which
are corrosive or toxic and could easily condense
into the exhaust pipe during normal process
operation. Ammonium chloride (NH4Cl), for
example, is a common concern during metal
etch. Ammonium hexafluorosilicate ((NH4)
2
SiF6) is a nasty byproduct of nitride CVD.
“Over a period of time, they’re going to
block the exhaust. Once the exhaust become
blocked, you’re into areas where you need to
take the tool out of manufacturing, pull the ex-
haust pipe to pieces, clean it all out, leak check
it and get it back into service again,” Chambers
said. “There’s strong motivation for end users
to provide ways of avoiding condensation in
exhaust pipes.”
Interestingly, Chambers said what is per-
ceived as a common solution to the problem —
heater jackets — is not effective. “What we’ve
found through a lot of experience is that, in many
instances, the heater jackets and the heating sys-
tems for exhaust pipes are really badly applied.
Heating the exhaust pipe and its maintenance at
the required temperature is patchy at best and
completely ineffective at worst.”
The best way to address all of this, accord-
ing to Chambers, is to consider the sub-fab
system as a complete integrated package.
“We’ve been selling integrated systems
comprising pumps and abatement systems
for many years. If you join that whole thing
together as an integrated system, it enables
you to get data out of your system that can be
used to provide diagnostic routines. It’s going
to tell you about impending problems with
your vacuum pumps, abatement system and
exhaust pipe,” he said.
“The abatement of process gases in high dilution flows is very inefficient.”ANDREW CHAMBERS, EDWARDS LTD.
It’s how we add value.
Reducing Defects andImproving Yield in Advanced
Manufacturing Processes
As one of the industry’s largest and leading providers of advanced materials, materials handling and contamination control solutions, we provide the broadest range of technologies covering the entire integrated stack. From ultrapure process components to integrated materials and component solutions, we add value by ensuring productivity gains through yield-enhancing solutions.
Contact us and learn how Entegris can help reduce defects and increase yield in your manufacturing processes.
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