SHIRDI SAI ENGG COLLEGE - · PDF fileWrite a behavioral description of JKFF with ... Differentiate between the functions and procedures. Write a VHDL code to ... Briefly explain the

SHIRDI SAI ENGG COLLEGE











06EC667.5

\Sixth Semester B.E. Degree Examination, May/June 2010Digital System Design Using VHDL

Note: Answer any FIVE full questions, selectingat least TWO questions from each parle

PART-A1 a. Briefly explain the VHDL operators.

b. Differentiate between signals and variables.c. Write a VHDL description for n-bit binary adder, using structural modeling.

(07 Marks)(05 Marks)(08 Marks)

2 a. Write a behavioral description of JKFF with active low preset and clear inputs. (06 Marks)b. Differentiate between the functions and procedures. Write a VHDL code to add two 8-bits of

data, using a function. (10 Marks)c. Explain packages. (04 Marks)

3 a. Differentiate between PAL and PLAs. Implement the following functions, using a suitablePLA:

F1(A, B, C, D) = L m(2, 3, 5, 7,8,9, 10, 11, 13, 15)F2(A, B, C, D) = L m(2, 3, 5, 6, 7, 10, 11, 14, 15)F3(A, B, C, D) = L m(6, 7,8,9, 13, 14, 15) (10 Marks)

b. Write a state graph and VHDL code for the traffic light controller. (10 Marks)

4 a. With a neat block diagram, explain the operation of serial adder with accumulator. (05 Marks)b. Write a state graph and VHDL description of a binary divider that divides an 8-bit dividend

by 4-bit divisor. (08 Marks)

c. Write a behavioral model for signed 4-bit x4-bit faster multiplier. (07 Marks)

PART-B5 a. Briefly explain the state machine charts. (06 Marks)

b. For the dice game based on the following rules, draw the SM chart, state graph and hencedevelop the behavioral model:

i) After the roll of the dice, the player wins if the sum is 7 or 11. The player loses ifthe sum is 2,3 or 12. Otherwise, the sum obtained by the player on the first roll isreferred to as a point and he/she must roll the dice again.

ii) On the second or subsequent roll of the dice, the player wins if the sum equalsthe point and he/she loses if the sum is 7. Otherwise, the player must roll againuntil he/she finally wins or loses. ' (14 Marks)

Outline the steps of procedure to design a digital system with FPGA. (04 Marks)With XILINX 3000 series, implement a parallel-adder-subtractor, with an accumulator.

(10 Marks)Explain the architecture of ALTERA 7000 series CPLD. (06 Marks)

6 a.b.

c.

7 a.b.c.

8 a.b.c.

Explain the transport and inertial delays, with an example, using waveforms.Briefly explain the synthesis.Explain the resolution of signal drivers.

Write a behavioral description of RAM 6116.Write a SM chart for simplified 486 bus interface with CPU.Write a VHDL description of floating-point subtractor.




Sixth Semester B.E. Degree Examination, May/June 2010Digital System Design using VHDL

a. Write dataflow model VHDL code for 4 : 1 multiplexer.

b. Starting from a D flip-flop on a component, write the structural VHDL4-bit serial in serial out shift register.

c. Compare signal and variables. Give an example for each.

(06 Marks)

description for a(08 Marks)

(06 Marks)

a. Write a VHDL function in a package for binary to integer conversion. Declare clock, resetas global signal in package (08 Marks)

b. Write a VHDL structural description of an 8-bit bidirectional shift register that uses two74194 as components. Write behavioral VHDL code for 74194 to perform followingfunction table: (12 Marks)

CLR CLK SISO D3D2DIDo SDR SDL Q; Q; Qt Q~0 x x xxxx x x 0 0 0 01 t 1 1 1 010 x x 1 0 1 01 t 1 0 xxxx 1/0 x SDRQ3 Q2 QI1 t o 1 xxxx x 1/0 Q3 Q2 QI SDL1 t 00 xxxx x x Q3 Q2 QI Qo

a. Realize the following table using ROM and D flip-flops. Write block diagram and VHDLcode. Assume that ROM and each FF has IOns delay. (08 Marks)

Q2QI Q; Qt zx=O x=1 x=O x=1

00 01 10 0 101 10 00 1 110 00 01 1 0

b. Find the minimized row PLA table to implement the following functions:fl(A, B, C, D) = ~m (3, 4, 6, 9, 11)f2(A, B, C, D) = ~ m (2, 4,8, 10, 11, 12)f3(A, B, C, D) = ~ m (3, 6, 7, 10, 11)

c. Write a neat sketch, explain output macrocell of CMOS PLD 22CEVI0.

(06 Marks)

(06 Marks)

a. Write a VHDL code for keypad scanner (4x3) with state diagram and decoder truth table.(10 Marks)

b. Design a 32-bit serial adder with accumulator. Adder control network uses 5-bit counter andstart pulse N. Draw the state diagram and write VHDL code. (10 Marks)

a. Draw the block diagram, state gram for faster multiplier [4-bit]. Write VHDL code for fastermultiplier. (14 Marks)

b. Write SM chart for binary multiplier. Explain briefly. (06 Marks)


6 a. Draw the block diagram for unsigned binary divider that divides an 8-bit dividend by 3-bitdivisor to give 5-bit quotient. Write VHDL description ofthe divider. (12 Marks)

b. Write a behavioral description of model of RAM 6116. (08 Marks)

7 a. With a neat sketch, explain Xilinx3000 series logic cell.b. With SM chart and state graph, explain floating point multiplier.

(10 Marks)

(~OMarks)

8 a. Write a VHDL code to generate signals, with the following attributes:i) Delayed (time)ii) Stable (time)iii) Quiet (time)iv) Transaction. (08 Marks)

b. With waveform, explain transport and inertial delay. (04 Marks)

c. Write a VHDL code for overloading + operation which can perform addition of an integerand a bit vector. (08 Marks)




Documents

SHIRDI SAI ENGG COLLEGE - · PDF fileWrite a behavioral description of JKFF with ... Differentiate between the functions and procedures. Write a VHDL code to ... Briefly explain the