Upload
ronat
View
36
Download
0
Embed Size (px)
DESCRIPTION
Shift Registers. Module M11.1 Section 7.3. 4-Bit Shift Register. shift4.abl. MODULE Shift4 TITLE '4-bit Shift Register A. Student, 7/22/02' DECLARATIONS " INPUT PINS " PB PIN 10; " push-button switch (clock) Clear PIN 7; " Switch 2 - PowerPoint PPT Presentation
Citation preview
Shift Registers
Module M11.1
Section 7.3
CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q
data_in
CLK
Q0 Q1 Q2 Q3
4-Bit Shift Register
shift4.abl
MODULE Shift4
TITLE '4-bit Shift Register A. Student, 7/22/02'
DECLARATIONS
" INPUT PINS "
PB PIN 10; " push-button switch (clock)
Clear PIN 7; " Switch 2
Load PIN 11; " Switch 3
data_in PIN 70; " Switch 8
" OUTPUT PINS "
Q3..Q0 PIN 39,37,36,35 ISTYPE 'reg buffer'; " LED 5..8
Q = [Q3..Q0]; " 3-bit output vector
shift4.abl (cont’d)
EQUATIONS
Q.c = PB;
Q0.d = !Clear & data_in;
Q1.d = !Clear & Q0;
Q2.d = !Clear & Q1;
Q3.d = !Clear & Q2;
END Shift4CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q
data_in
CLK
Q0 Q1 Q2 Q3
4shift.si
Listing 7.12 4shift.si
Name 4shift;Partno OU0031;Revision 01;Date 8/07/91;Designer R. E. Haskell;Company Oakland University;Location Rochester, MI;Assembly CSE 171;Device G16V8;Format j;
/********************************************************//* This is a 4-bit shift register *//********************************************************//* Target Device: G16V8 *//********************************************************/
CUPL SimulationFile
4shift.siORDER: clock,%2,clear,%2,data_in,%2,q0,%2,q1,%2,q2,%2,q3;
VECTORS:C10 LLLL /* clear register */C01 HLLLC00 LHLLC00 LLHLC00 LLLHC00 LLLLC01 HLLLC00 LHLLC01 HLHLC00 LHLHC01 HLHLC00 LHLHC00 LLHLC00 LLLHC00 LLLL
CUPL SimulationFile
CUPL SimulationOutput File
Ring Counter
CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q
CLK
Q0 Q1 Q2 Q3
ring4.abl
MODULE Ring4
TITLE '4-bit Ring Counter A. Student, 7/22/02'
DECLARATIONS
" INPUT PINS "
PB PIN 10; " push-button switch (clock)
Clear PIN 7; " Switch 2
" OUTPUT PINS "
Q3..Q0 PIN 39,37,36,35 ISTYPE 'reg buffer'; " LED 5..8
Q = [Q3..Q0]; " 3-bit output vector
ring4.abl (cont’d)
EQUATIONS
Q.c = PB;
Q0.d = !Clear & Q3;
Q1.d = !Clear & Q0;
Q2.d = !Clear & Q1;
Q3.d = !Clear & Q2 # Clear;
END Ring4
CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q
CLK
Q0 Q1 Q2 Q3
ring4.si
Listing 7.14 ring4.si
Name ring4;Partno OU0032;Revision 01;Date 8/07/91;Designer R. E. Haskell;Company Oakland University;Location Rochester, MI;Assembly CSE 171;Device G16V8;Format j;
/********************************************************//* This is a 4-bit ring counter *//********************************************************//* Target Device: G16V8 *//********************************************************/
CUPL SimulationFile
ring4.si
ORDER: clock,%2,clear,%2,q0,%2,q1,%2,q2,%2,q3;
VECTORS:C1 LLLHC0 HLLLC0 LHLLC0 LLHLC0 LLLHC0 HLLLC0 LHLLC0 LLHLC0 LLLHC0 HLLLC0 LHLLC0 LLHLC0 LLLHC0 HLLLC0 LHLLC0 LLHLC0 LLLH
CUPL SimulationFile
CUPL SimulationOutput File
Ring Counter
CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q
CLK
Q0 Q1 Q2 Q3
Johnson Counter
CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q
CLK
Q0 Q1 Q2 Q3
ExerciseDetect input sequence 1101
fsm
din
doutclk
clr
dindout
1 0 1 1 0 1 1 0 1 0 0 1 1 0 1 00 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0
Use Shift Register
CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q
CLK
Q0 Q1 Q2 Q3
1 0 1 1
dout
din
Lab 8Johnson Counter & Random
Number Generator
CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q
CLK
Q3 Q2 Q1 Q0
Random Number Generator
CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q
CLK
Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0
0 0 0 1 11 0 0 0 81 1 0 0 C1 1 1 0 E1 1 1 1 F0 1 1 1 71 0 1 1 B0 1 0 1 5
Q3 Q2 Q1 Q0
1 0 1 0 A1 1 0 1 D0 1 1 0 60 0 1 1 31 0 0 1 90 1 0 0 40 0 1 0 20 0 0 1 1