SHANKAR NARAYANAN PDate of Birth : 13-06-1991

Address

No.18 ,

8th Cross School Street,

Jafferkhanpet,

Chennai-600083

Objective Seeking an opportunity to work in the field of silicon where I can put all of my efforts and ideas to innovate under the valuable guidance of the concern.

Education

Degree Institute Board / University

Year % marks /CGPA

M.E(VLSI Design)

ADHIPARASAKTHI ENGINEERING COLLEGE,MELMARUVATHUR

ANNA UNIVERSITY

2013-2015 7.57

B.E (ECE) RRASE COLLEGE, PADAPPAI ANNA UNIVERSITY

2008-2012 6.73

12th M.A.K MAT.HR.SEC SCHOOL,ASHOK NAGAR, CH-83

STATE BOARD 2007-2008 61.5

10th M.A.K MAT.HR.SEC SCHOOL,ASHOK NAGAR, CH-83

STATE BOARD 2005-2006 65

Contact

Tel : +919789884214e-mail : Shankar.narayanan2012@gmail.com

Project UG

Title : IMPLEMENTATION OF 8 BIT BCD ADDER USING REVERSIBLE LOGIC GATES

Description : The project involves in the design of a low power BCD added the help of reversible logic gates.

These gates are said to be consuming lower power than the conventional gates, they also consume

lower space for fabrication. Then the design are implemented over a test FPGA ( Spartan 3E).

Environment : Xilinx ISE design suite

Project PG

 Title : ASIC DESIGN USING PROGRAMMABLE INTERCONNECTS BASED ON CBRAM

Description : The project involves in the design of a non-volatile memory CBRAM (Conductive Bridging

Random Access Memory) this NVM will replace the SRAMs that are in the conventional ASIC design. The selection of this CBRAM is choose in a way that in physical constrains it is easier to fabricate, the design does not required any special algorithms thus making the design much easier. The conclusion of the product will be requiring low power and lower area consumption.

Environment : Silvaco T CAD tools & Cadence tools

Technical Profile

Programming Languages : C,C++,EMBEDDDED-C

HDLs : VERILOG HDL,VHDL,SYSTEM VERILOG

Scripting Languages : Perl,Shell,Python,Tcl

Programming Platforms : Mentor Graphics, Synopsys,Cadence,Xilinx ISE,PSPICE,Silvaco TCAD

Protocols/Methodology : OVM,UVM,VVM,AHB,APB,AXI,USB(V2.0/3.0),PCI,PCIe,SATA 2,SATA 3

Area of Interest : VLSI Verification & ASIC/SoC Design

Operating Family : Linux,Windows Family

Extra Courses

Name of the course : Embedded Programming

Year : 2012

Name of the center : ACCEL IT ACCADEMY, Tambaram

Aim of the course : To learn the programming for microprocessor, microcontroller & ARM based devices

Strength

Good team worker and flexible to take up any responsibilities.

Work with positive attitude to contribute the healthy functioning of the organization.

Willing to work in rotational shifts.

Ability to adapt to different environment in the workplace.

Interested in travelling to take abroad work.

Love to innovate and imply new ideas.

Achievements

Name of the Paper : “ASIC design using programmable interconnects based on CBRAM”

Paper presentation : National Level conference titled as “National Conference On Model Electronics” at Jeppiar Institute of Technology,Sriperumbudur.

Paper publication : International Journal of Innovative Science, Engineering & Technology,Vol.2 Issue 4, April 2015,pp886-890.

Personal Details

Fathers Name : V.PachaiappanGender : MaleLanguages Known : English & TamilPermanent Address : No 18, 8th cross school street, Jafferkhanpet, Chennai-600083

Declaration

I hereby declare that the above information is true to the best of my knowledge.

Place:

Date: (SHANKAR NARAYANAN P)