MICROFILM

SERVICE MANUAL

COMPACT DISC CHANGER

US ModelCanadian Model

AEP ModelUK Model

E Model

SPECIFICATIONS

CDX-727

Model Name Using Similar Mechanism CDX-715

CD Drive Mechanism Type MG-250C-137

Optical Pick-up Name KSS-521A/J2N

CDX-727

– 29 – – 30 –

7-6. SCHEMATIC DIAGRAM – RF/SW Boards – • See page 41 for Waveforms. • See page 43 for IC Block Diagrams.

The components identified by mark ! or dottedline with mark ! are critical for safety.Replace only with part number specified.

Les composants identifiés par une marque ! sontcritiques pour la sécurité. Ne les remplacer quepar une piéce portant le numéro spécifié.

(Page 35)

CDX-727

– 35 – – 36 –

7-9. SCHEMATIC DIAGRAM – MAIN Board (1/2) – • See page 41 for Waveforms. • See page 44 for IC Block Diagrams.

(Page 30)

CDX-727

– 37 – – 38 –

7-10. SCHEMATIC DIAGRAM – MAIN Board (2/2) – • See page 42 for Waveforms. • See page 45 for IC Block Diagrams.

(Page 40)

– 39 –

7-11. PRINTED WIRING BOARD – JACK Board –

(Page 31)

– 40 –

7-12. SCHEMATIC DIAGRAM – JACK Board –

(Page 38)

– 41 –

• Waveforms– RF Board –

1 IC11 #£ (RF O)500 mV/DIV, 500 ns/DIV

2 IC11 2 (FEI)50 mV/DIV, 1 µs/DIV

3 IC11 $¶ (TEI)200 mV/DIV, 500 µs/DIV

2 IC101 #§ (V16M)

3 IC101 $ª (WDCK)

4 IC101 %º (LRCK)

5 IC101 %¢ (BCKO)

6 IC101 ^™ (RFCK)

7 IC101 &º (C4M)

8 IC101 &¢ (WFCK)

9 IC101 *ª (XTAI)

0 IC201 #¡ (EXTAL)

1.4 Vp-p

Approx. 110 mVp-p

Approx. 280 mVp-p

– MAIN Board (1/2) –

1 IC101 @¶ (MDP)

2.5 Vp-p

7.6 µs

6.5 Vp-p

119 ns

6.3 Vp-p

11.4 µs

6.2 Vp-p

22.7 µs

6.5 Vp-p

474 ns

6.4 Vp-p

13.6 µs

6.3 Vp-p

119 ns

136 µs

5.8 Vp-p

6.2 Vp-p

59.4 ns

4.9 Vp-p

124 ns

– 42 –

– MAIN Board (2/2) –

!¡ IC501 @ª (EXTAL)

!™ IC501 &¶ (WRCK)

!£ IC401 3 (WFCK)

!¢ IC401 5 (C4M)

!∞ IC401 7 (RFCK)

!§ IC401 9 (BCKI)

!¶ IC401 !™ (LRCI)

!• IC401 !£ (WDCI)

!ª IC401 !§ (XTAI)

@º IC401 !¶ (BCK)

@¡ IC401 !ª (LRCK)

@™ IC601 !£ (MCK)

@£ IC601 !∞ (XI)

@¢ IC601 @£ (BCK)

@∞ IC601 @¢ (LRCK)

3.1 Vp-p

100 ns

5.8 Vp-p

136 µs

5.8 Vp-p

136 µs

6.4 Vp-p

136 µs

6.5 Vp-p

474 ns

6.3 Vp-p

22.7 µs

6.9 Vp-p

11.3 µs

6.4 Vp-p

59.4 ns

6.2 Vp-p

474 ns

5.6 Vp-p

22.7 µs

5.8 Vp-p

59.4 ns

2.5 Vp-p

59.4 ns

474 ns

6.2 Vp-p

22.7 µs

5.6 Vp-p

6.3 Vp-p

119 ns

– 43 –

• IC Block Diagrams– RF Board –

IC11 CXA1992BR

FZC

VC

TDFCT

TZC

ATSC

TEI

LPFI

TEOVEE

EI

E

F

FEBIAS

SL P

SL M

SL O

ISET

VCC

XRSTDATAXLTCLKLOCK

SENS2SENS1C. OUT

VCC

DFCT

O

IFB1

– IF

B6BA

L1 –

BAL

4TO

G1 –

TOG

4

FS1

– FS

4

TG1

– TG

2

TM1

– TM

7

PS1

– PS

4

TGH

TGL

BALH

BALL

ATSC

DFCT

TM1

TG1

FS2

IFB1 – IFB6

VCC

VEE

VCC

VEE

VEE

PD 2I-V AMP

FOK

CC2

CC1

CBCPRF O

RF I

RFTC

PD2

PD1

PD LD RF M

TA O

TA M

FSET

TG2

TGU

SRCHFE

O

FEI

FDFC

T

FGD

FLB

FE O

FE M

TZC

FZC

FOL

FOH

MIR

R

LDON

LPCL

LPC

TGFL

DFCT

1

CC1

1 2 3 4 5 6 7 8 9 10

262524

2322212019

18

17

16

15

14

40

41

42

434445

46

47

48

49

50

51

52

39

PD 1I-V AMP

38

PDAMP

37

LDAMP

LASERPOWER

CONTROL

FOCUS BIASWINDOW

COMPARATOR

FOCUS ERRORAMP

F I-VAMP

E I-VAMP

TGFL TRACKING GAINWINDOW

COMPARATOR

E-F BALANCEWINDOW

COMPARATOR

ATSCWINDOW

COMPARATOR

TZCCOMPARATOR

TRACKING PHASECOMPENSATION

CENTERVOLTAGE

GENERATOR

FZCCOMPARATOR

FOCUS PHASECOMPENSATION CHARGE UP

FSET

ISET

IIC DATA REGISTER, INPUT SHIFT REGISTER,ADDRESS DECODER, SENSE SELECTOR,

OUTPUT DECODERTTL↓IIL

IIL↓

TTL

IIL↓

TTL

RF SUMMINGAMP FOCUS OK

COMPARATOR

PEAK/BOTTOMHOLD

PEAK/BOTTOMHOLD

DEFECTAMP

MIRRCOMPARATOR

36 34 31 30 29 28 2735 33 32

BAL1

– B

AL4

TM6

TM2

VCC

VEE

TM5

11 12 13

TG2

TM4

VCC

VEE

TM3

FS1

VCC

VEE

TOG1

– T

OG4

TM7

FS4DFCT

+–

+–

– 44 –

IC52 BA6287F

1

2

3

4

OUT1

VM

VCC

FIN

8

7

6

5

GND

OUT2

VREF

RIN

CONTROL LOGIC

TSD

POWERSAVE

DRIVER DRIVER

– MAIN Board –

IC101 CXD2530Q

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

43424140

39383736

3534333231

5049

4847464544

888990919293949596979899100

81828384858687

71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 5180 79 78 77 76 75 74 73 72

ASYMMETRYCORRECTOR

DIGITALPLL

CLOCKGENERATOR

D / AINTERFACE

DIGITAL CLV

SUB CODEPROCESSOR

TIMINGLOGIC CPU

INTERFACE

SERVOAUTO

SEQUENCER

ERRORCORRECTOR

16K RAM DIGITAL OUT

OSC

EFMDEMODULATOR

TES6

VDD

VSS

EXCK

SBSO

SCOR

WFC

KTE

S5EM

PH

DOUT

C4M

FSTT

XTSL

MNT

0M

NT1

MNT

3XR

OFC2

PORF

CKGF

SXP

CKXU

GFGT

OPVD

DVS

STE

S4BC

KTE

S3PC

MD

TES9

LRCKWDCK

ASYEASYOASYIBIASRFAVDDCLTVAVSSFILI

FILOPCOVCTLV16M

VCKIVPCO1VPCO2TES1TES0

LOCK

PWM

I

MDP

MDSVS

SM

ONFOK

VDD

SPOD

XLON

SPOB

SPOC

CLKO

SPOA

DATO

XLTO

SEIN

CNIN

XLAT

CLOK

SENS

DATA

SQCK

SQSO

TES2

CKOU

T

LMUT

RMUT

VDD

VSS

NCXRST

VSSNC

NCVDD

NCTES8

XVSSVSS

XTAIXTAO

VSSXVDD

TES7NC

VDDNC

NCVSS

– 45 –

IC202 AT24C16N-10SI-TR

DEVICEADDRESS

COMPARATOR

Y DEC

H.V. PUMP/TIMING

DATA RECOVERY

E2PROM

SERIAL MUX

STARTSTOPLOGIC SERIAL

CONTROLLOGIC

DATA WORDADDR/COUNTER

DOUT/ACKLOGIC

123

4

5

6

7

8

X DE

C

VCC

TST

SDL

SDA

A0A1A2

GND

COMPLOAD

LOAD INC

R/W

EN

DOUT

DIN

IC301 BA6287F

IC302 BA8272F-E2 IC401 CXD2522Q

1

2

3

4

OUT1

VM

VCC

FIN

8

7

6

5

GND

OUT2

VREF

RIN

CONTROL LOGIC

TSD

POWERSAVE

DRIVER DRIVER

1 2 3 4 5 6 7

891014 13 12 11

VCC

BUS

ON

LINK

OFF

CLK

OUT

DATA

OUT

DATA

IN

BUS

RESE

T

BUS

DATA

VREF

BUS

CLK

GND

BUS

ON IN

BUS

ON O

UT

RESE

T

RESETSWITCH

VWA

ADDRESS MONITOR

WRITEBASE

COUNTER

READBASE

COUNTER

CPU I/F

SELECTOR

TIMINGGEN.

DSPI/F

DATALINKING

CONTROL DACI/F

DIGITALOUT

1 2 3 4 5 6 7 8 9 10

20

191817161514131211

21

2223242526272829303132

3334353637383940414243444546

5655545352

51 50 49 48 47

575859

60

61

626364

XWIHAM4AM3AM2AM1AM0VDD

XQOK

GSCR

SCOR

NCNCNC

GRST

XRST

WFC

KDI

NC4

MXR

OIRF

CKGT

OP

BCKI

VSS

DATI

LRCI

WDC

ITE

STXT

AO

XTAI

BCK

DATA

LRCK

DOUT

C176

A3A2A1A0VDDA9XRASXWED1D0D3

D2XCAS

XOE

A8A7A6A5A4OSCE

VSS

SPSL

XEM

PSD

TOXS

OESC

KSD

TIXL

TXR

DEXW

RE

DRAMI/F

– 46 –

IC402 MSM514400D-60TS-K

WRITECLOCK

GENERATOR

DATA INPUTBUFFER

DATA OUTPUTBUFFER

COLUMNDECODER

SENSE AMPI/O GATE

4M BITMEMORY

CELL

ROW DECODER

ADDRESSBUFFER

PRE-DECODER

REFRESHADDRESSCOUNTER

BOARDBIAS

GENERATOR

MODECONTROL

CLOCKGENERATOR

1

CLOCKGENERATOR

2

18

242526

17161514

5

4

12

3

910111213

2322

DQ1DQ2

WE

RAS

A9A0A1A2A3

VCC

VSSDQ4DQ3

CAS

OE

A8A7A6A5A4

IC502 KM62256DLG-7LT IC601 TC9464FN-EL

MEMORYMATRIX512X512

ROWDECODERBUFFER1A14

2345A5

A12A7A6

26 A1325 A82423 A11

A9

I/O GATECOLUMNDECODER

BUFFER

6A478910A0

A3A2A1

27

28 VCC

WE

22 OE

21 A10

BUFFER

18 I/O717 I/O616

I/O4I/O5

19 I/O8

15I/O BUFFER

111213I/O3

I/O1I/O2

20 CE

14GND

LEVELSHIFT

LEVELSHIFT

LEVELSHIFT

DIGITAL FILTER CIRCUITATTENUATOR OPERATIONAL CIRCUIT

DEEMPHASIS FILTER CIRCUITD-∆ MODULATION CIRCUIT

INTERFACECIRCUIT

TESTCIRCUIT

OUTPUTCIRCUIT

ANALOGFILTER

TIMINGGENERATOR

OSCMICROCOMPUTER

INTERFACECIRCUIT

OUTPUTCIRCUIT

ANALOGFILTER

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13

1211

21222324

LRCK

BCK

DATA

HS (SM

)AT

T

(EM

P)SH

(BS) LA VDX

XO XI GNDX

MCK

VDD T1 P/S

VDA

RO

GNDA VR

GNDA LO

GNDDZDVD

A

– 47 –

7-13. IC PIN FUNCTION DESCRIPTION

• MAIN BOARD IC201 CXP84332-210Q (SYSTEM CONTROLLER)

Pin No. Pin Name I/O Function

1 to 3 — O Not used (open)

4 CH.F OMotor drive signal (load chucking direction) output to the chucking motor drive (IC52)“L” active *1

5 CH.R OMotor drive signal (save direction) output to the chucking motor drive (IC52)“L” active *1

6 LOAD2 IChucking end detect switch (SW11) input terminal“L”: When completion of the disc chucking operation

7 LOAD1 ISave end detect switch (SW12) input terminal“L”: When completion of the disc chucking operation

8 SENS2 I Internal status signal (sense signal) input from the CXA1992BR (IC11)

9 LIM.SW ISled limit in detect switch (SW1) input terminal“L”: When the optical pick-up is inner position

10 EE.INIT I Initialize signal input for the EEPROM (IC202) “H”: format Fixed at “L” in this set

11 EE.CLK O Serial data transfer clock signal output to the EEPROM (IC202)

12 EE.DATA I/O Two-way data bus with the EEPROM (IC202)

13 to 19 — O Not used (open)

20 SINGLE ISetting terminal for the single disc/multiple discs mode“L”: single mode, “H”: multiple discs mode (fixed at “H”)

21 XRST OSystem reset signal output to the CXA1992BR (IC11), CXD2530Q (IC101) and CXD2522Q (IC401) “L”: reset

22 FOK I Focus OK signal input from the CXA1992BR (IC11) “L”: NG, “H”: OK

23 SENS I Internal status signal (sense signal) input from the CXD2530Q (IC101)

24 GFS I Guard frame sync signal input from the CXD2530Q (IC101) “L”: NG, “H”: OK

25 GRSRT O Reset signal output to the CXD2522Q (IC401) “L”: reset

26 XQOK O Subcode Q OK pulse signal output to the CXD2522Q (IC401) “L” active

27 SDTI I ESP status signal input from the CXD2522Q (IC401)

28 XSOE O ESP status read enable signal output to the CXD2522Q (IC401) “L” active

29 ESPXLT O ESP latch pulse signal output to the CXD2522Q (IC401) “L” active

30 RST ISystem reset signal input from the SONY bus interface (IC302) and reset signal generator (IC304) “L”: resetFor several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”

31 EXTAL I Main system clock input terminal (8 MHz)

32 XTAL O Main system clock output terminal (8 MHz)

33 VSS — Ground terminal

34 TX O Sub system clock output terminal Not used (open)

35 TEX I Sub system clock input terminal Not used (fixed at “L”)

36 AVSS — Ground terminal (for A/D converter)

37 AVREF I Reference voltage (+5V) input terminal (for A/D converter)

38 MCK IInput of signal for the fine adjustment (linear position sensor adjustment; RV201) of elevator position (A/D input)

39 EHS I Elevator height position detect input from the RV202 (elevator height sensor) (A/D input)

40 MODEL I Setting terminal for the destination (fixed at “H” in this set)

41 XRDE O D-RAM read enable signal output to the CXD2522Q (IC401) “L” active

42 XWRE O D-RAM write enable signal output to the CXD2522Q (IC401) “L” active

43 A.MUTE O Audio line muting on/off control signal output terminal “H”: muting on

44 EMP O Emphasis mode output to the D/A converter (IC601) “H”: emphasis on

45 ML O Fast speed dubbing control signal output to the D/A converter (IC601) “L”: fast speed

46 GRSCOR I Subcode sync (S0+S1) detection signal input from the CXD2522Q (IC401)

– 48 –

*1 chucking motor (M103) control

STOPLOAD

CHUCKINGSAVE BRAKE

CH.F (pin 4) “H” “L” “H” “L”

CH.R (pin 5) “H” “H” “L” “L”

ModeTerminal

*2 elevator motor (M104) control

STOPELEVATOR

UPELEVATOR

DOWNBRAKE

ELV.F (pin %•) “H” “L” “H” “L”

ELV.R (pin &º) “H” “H” “L” “L”

ModeTerminal

Pin No. Pin Name I/O Function

47 D/A.RESET O Reset signal output terminal “L”: reset Not used (open)

48 SCK I Serial data transfer clock signal input from the SONY bus interface (IC302)

49 SI I Serial data input from the SONY bus interface (IC302)

50 SO O Serial data output to the SONY bus interface (IC302)

51 SCLK O Subcode Q data reading clock signal output to the CXD2530Q (IC101)

52 SUBQ I Subcode Q data input from the CXD2530Q (IC101)

53 — O Not used (open)

54 C.OUT I Track number count signal input from the CXA1992BR (IC11)

55 BUS.ON I Bus on/off control signal input from the SONY bus interface (IC302) “H”: bus on

56 — I Not used (open)

57 MGLK I Magazine eject operation completion detect switch (SW201) input “L”: eject completed

58 ELV.F OMotor drive signal (elevator up direction) output to the elevator motor drive (IC301)“L” active *2

59 — O Not used (open)

60 MAG.SW I Magazine in/out detect switch (SW202) input “L”: magazine detected

61 BU.CHK I Battery detection signal input terminal “H”: battery on

62 W.UP I Bus on or eject switch (SW301) input terminal “H”: bus on or eject switch pushing

63 SCOR I Subcode sync (S0+S1) detection signal input from the CXD2530Q (IC101)

64 EJECT I Eject switch (SW301) input terminal “H” active

65 CD.CLK O Serial data transfer clock signal output to the CXD2530Q (IC101) and CXD2522Q (IC401)

66 CD.XLT O Serial data latch pulse signal output to the CXD2530Q (IC101)

67 CD.DATA O Serial data output to the CXD2530Q (IC101) and CXD2522Q (IC401)

68 CD.ON O D/A converter and servo section power supply on/off control signal output “H”: power on

69 ELV.ON O Mechanism deck section power supply on/off control signal output “H”: power on

70 ELV.R OMotor drive signal (elevator down direction) output to the elevator motor drive (IC301)“L” active *2

71 — O Not used (open)

72 VDD — Power supply terminal (+5V)

73 NC (VDD) — Connected to the power supply (+5V)

74 BUSY I Busy monitor input from the CD text decoder (IC501) “L”: busy status

75 RESET O Reset signal output to the CD text decoder (IC501) “L”: reset

76 REQ I Data request signal input from the CD text decoder (IC501) “L” active

77 CCCLK O Command clock signal output to the CD text decoder (IC501)

78 CSO O Command data output to the CD text decoder (IC501)

79 CSI I Command data input from the CD text decoder (IC501)

80 — I Not used (open)

– 49 –

• MAIN BOARD IC501 CXP83413-049Q (CD TEXT DECODER)

Pin No. Pin Name I/O Function

1, 2 NC O Not used (open)

3 NC I Not used (fixed at “L”)

4 REQ O Request signal output to the system controller (IC201) “L” active

5 CCLK I Serial data transfer clock signal input from the system controller (IC201)

6 CSI I Serial data input from the system controller (IC201)

7 CSO O Serial data output to the system controller (IC201)

8 SCLK O Clock signal output for subcode data reading to the CXD2530Q (IC101)

9 SSI I Subcode data input from the CXD2530Q (IC101)

10 NC O Not used (open)

11 to 18 ADD0 to ADD7 O Address signal output to the S-RAM (IC502)

19 NC I Not used (fixed at “L”)

20 to 27 DATA0 to DATA7 I/O Two-way data bus with the S-RAM (IC502)

28 RST ISystem reset signal input from the system controller (IC201), SONY bus interface (IC302) and reset signal generator (IC304) “L”: resetFor several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”

29 EXTAL I System clock input terminal (10 MHz)

30 XTAL O System clock output terminal (10 MHz)

31 VSS — Ground terminal

32 to 55 NC O Not used (open)

56 BUSY O Busy signal output to the system controller (IC201) “L”: busy status

57 to 61 NC O Not used (open)

62 CE O Chip enable signal output to the S-RAM (IC502) “L” active

63 WE O Data write enable signal output to the S-RAM (IC502) “L” active

64 to 69 ADD8 to ADD13 O Address signal output to the S-RAM (IC502)

70 VDD — Power supply terminal (+5V)

71 NC O Not used (open)

72 NC I Not used (fixed at “L”)

73 NC I Not used (fixed at “H”)

74 ADD14 O Address signal output to the S-RAM (IC502)

75 NC O Not used (open)

76 SCOR I Subcode sync (S0+S1) detection signal input from the CXD2530Q (IC101)

77 WFCK I Write frame clock (7.35 kHz) signal input from the CXD2530Q (IC101)

78 BUCK I Backup power supply detection signal input terminal (used also to reset standby)

79, 80 NC I Not used (fixed at “L”)