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Server Power System for Highest Efficiency and Density:

Practical Approach Step by Step

Rais Miftakhutdinov and John Stevens

Texas Instruments, High Performance Isolated Power, r-miftakhutdinov1@ti.com; john.stevens@ti.com

2012 IBM Power Technology Symposium

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Outline

Stringent Requirements for Server Power Supply Efficiency in 2012+

“Platinum” Power Supply Step by Step Design Example

Power Losses Budget: Where the losses come from?

How to achieve ZVS and Minimize Switching Losses on Primary Side?

Timing is Critical to Minimize Switching Losses on Secondary Side

Light Load Efficiency Handling

Summary

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10% load N/A 75% 80% 82%

20% load 81% 85% 88% 90%

50% load 85% 89% 92% 94%

100% load 81% 85% 88% 91%

PF 0.9 @ 50% load

0.9 @ 50% load

0.9 @ 50% load

0.95 @ 50% load

“80 PLUS” and “Climate Savers Computing”

“Climate Savers Computing” initiative has expanded efficiency requirement down to 10% load. To meet this requirement light load power management technique must be implemented.

http://www.plugloadsolutions.com/80PlusPowerSupplies.aspx

http://www.climatesaverscomputing.org/

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Roadmap for Front-End Power Supply in 2015

Efficiency: up to 97% for 48V output (97.5% leading edge) up to 95% for 12V output (95.5% leading edge)

Power Factor: 0.95 at half-load and full load Power Density: >40 W/cub.inch Cost per Watt: <10 cents/W Design Cycle from Spec to Volume Production: < 8 Months

Facility 208V AC

AC/DC (PFC)

DC/DC

12V, -48V, 54V DC

Server, rectifier

PSMA Power Technology Road Maps 2009 and 2011: http://www.psma.com/

Standby

5V Stb

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Platinum Server Power Supply Design: Step by Step

1. Step 1: Power Stage Components Selection a) Review efficiency requirements and break down to PFC, DC-DC and Standby PS b) Select topology: Phase Shifted, LLC or Two-Switch Forward for DC-DC c) For the next steps own or available from vendors software design tool is very helpful d) Based on efficiency goal estimate losses. Set ratio conduction to switching losses e) Select optimal primary/secondary FETS and magnetics to satisfy conduction losses

2. Step 2: Taking Care of Switching Losses at 10% to 100% load a) Review Coss of selected primary FETs and establish ZVS conditions for Ls and Lm b) Select optimal frequency based on drive, AC magnetic and body diode recovery losses c) Find optimal delay time between primary FETs switching over load range d) Find optimal timing between primary and secondary FETs switching

3. Step 3: Controller Selection and Light Load Power Management a) Select controller having optimal drive timing based on load and light load management

block: Examples from TI – UCC28950 (analog), UCD3K and C2000 families (digital) b) Set optimal conditions for operation mode changes at 0 to 20% load to minimize Ploss

4. Step 4: Additional Tuning and Modification if necessary based on Simulations and Prototype Test Results

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80+ “Platinum” AC-DC Power Supply Efficiency Breakdown

• “Platinum” 80+ requirements for post-PFC DC-DC converter are very challenging. Below is efficiency breakdown between PFC and DC/DC parts of Front-End AC/DC power supply with Vin=390V and Vout=54V, Iout = 26A. The table allows set design goals for DC-DC converter shown in the next slide.

Efficiency at % for 48-V telecom rectifier power supply Pout 10% 20% 50% 100%

AC-DC 93.5 96 96.5 95.4 PFC 98.4 98.8 98.3 98.1 DC-DC 95.0 97.2 98.2 97.2

•Note: Efficiency of PFC converter includes efficiency of Standby power supply

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Phase-Shifted Full-Bridge Power Stage for DC-DC

Depending on specific requirements most popular power stage topologies for server power supply are:

• PSFB PWM

• LLC Resonant

• Two-Switch Forward

Because PSFB PWM remains most popular topology for this application, the design example is given for PSFB

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Input Requirements Data and Efficiency Goals

In this example MathCAD based design program is used

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Set Break Down between Conduction and Switching Losses

Efficiency Goals at 10, 20, 50 and 100% load

Maximum Ploss to meet efficiency goals

Maximum efficiency point is where the losses proportional to I^2 are equal to the losses independent from load (i.e. switching losses)

Based on the above rule, the switching losses limit is set as half of overall losses at 50% load (shown as dashed red horizontal line). Another words at 50% load it is assumed that conduction losses are equal to switching losses. =Switching Losses

Conduction Losses =

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Select Power Stage Components to meet Pcond Limit

Conduction losses over load are calculated and the summary plot is shown. The losses include: primary FETs, synchronous FETs, power transformer windings, output inductor, shim inductor, OR-ing FETs, shunt resistor, PCB traces losses

with the temperature coefficient taken into account. The difference between power losses limit and conduction losses is where the switching losses must fit.

Only about 6W switching losses allowed in this example.

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Primary FETs: Switching Losses and ZVS conditions

To analyze switching losses at different operating conditions and set ZVS (zero voltage switching) conditions, the mathematical description of Coss and related Energy is very helpful. The left side plots are taken from DS of IPW65R080CFD MOSFET. The right side plots are based on equations. The analytical plots closely match experimental ones taken from DS.

Calculations show that without ZVS the Coss switching losses would be 12.8W at switching frequency 140kHz.

To guarantee ZVS, leakage and magnetizing inductance of power transformer must be selected properly.

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ZVS for node B: The End of Duty Cycle

To achieve ZVS at node B, which switches at the end of PWM duty cycle, is relatively easy because the energy is provided by the output inductor current reflected into primary side.

In this case only proper delay before turning on the FET needs to be maintained. The optimal delay increases when the load decreases as it is shown in the plot.

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ZVS for node A: The Start of Duty Cycle

To achieve ZVS at node A, which switches at the start of PWM duty cycle, the energy of leakage and magnetizing inductance of power transformer is used. In some cases the assistance from so called “Shim” inductor in series with the primary winding is used. The diodes clamping one end of shim inductor to input rails minimize the ringing at synchronous rectifier FETs.

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ZVS Boundaries and Conditions

Plot shows the current through primary FETs Q1, Q11 at the beginning of duty cycle (blue). Red lines with circles show the boundaries of ZVS based on energy available at shim inductor and magnetizing inductance.

To guarantee ZVS over all load current range, the blue line should stay in ZVS region. This is achieved by increasing shim inductor and decreasing magnetizing inductance if necessary.

No ZVS region

ZVS region

The optimal delay between FETs switching at node A also depends on load condition. The controller should sense the load current and set optimal delay accordingly.

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Turn OFF Losses

ZVS eliminates turn ON losses but turn OFF losses still exist in PSFB. To minimize turn OFF losses it is recommended: • Minimize impedance in drive path • Select FETs with low gate resistance <1 Ω • Capacitance in parallel with the FETs could be added for ZCS. This might result in losing ZVS though. In this example Rgint = 0.75Ω and Rdr = 0.2Ω. As the result the turn OFF losses are relatively small: 0.75W only at maximum load current

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Optimal Synchronous MOSFET Switching Consideration

•After Q11 is off, the Q4 should be off as well, and after Q1 is off, the Q3 should be off.

•If to turn off Q3 and Q4 too early, the body diode with poor recovery will conduct too long time thus increasing reverse recovery switching losses.

•If to turn off Q3 and Q4 too late, then the secondary winding will be shorted causing overshoot followed by voltage spike across the sync FETs

•Proper timing for Q3 and Q4 turn off depend on load current. At high load current Q3 and Q4 can be turned off later because it takes longer time to load current switch from one FET to another.

Q11 g(Q1 g)

Q2 g(Q22 g)

TAFSET2

(TBESET2)

Q3 g(Q4 g)

TAFSET1

(TBESET1)

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Synchronous Rectifier and other Switching Losses

To minimize switching losses in synchronous rectifier FETs it is critical: • Minimize body diode conduction by using adaptive delay as it was shown in previous slide •Shim inductor on primary side with clamped diodes minimizes voltage overshoot across synchronous rectifier FETs • Remaining ringing can be eliminated by R-C-D snubber In this example, Rsn = 20K between Csn and Vout dissipates 1.4W. With proper timing and relatively slow di/dti through the body diode provided by shim and leakage inductance, the recovery losses are about 2.6W. Other losses include: 0.95W - gate drive losses of primary FETs 0.36W – gate drive losses of synchronous rectifier FETs 0.7W – transformer core losses This results in overall switching losses 6.75W

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Summary of Power Losses

Overall power losses including conduction and switching losses over load current range from 10% to 100% are shown in the summary plot. The design meets “Platinum” power supply requirements at key load current points. Additional power saving at light load and no load is provided by changing operation modes using light load power management block.

Additional power saving by light load power management

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Power Saving Control Algorithm vs Load Current

Q4 g

Q3 g

Nominal Mode

Q4 g

Q3 g

Transition Mode at Vcs1 Threshold, 50% duty cycle pulses

Transformer winding

Magnetizing current

Burst Mode at light load with Tmin maintaning ZvS (different time scale

versus upper waveforms)

Q4 g

Q3 g

Discontinuous Current Diode Rectification Mode with Q3 g, Q4 g

disabled at Vcs < Vcs2

Q4 g

Q3 g

Transition Mode at Vcs2 < Vcs < Vcs1

Nominal Operation at Io from 20 to 100%

Transition Mode at Io from 10 to 20% by gradually reducing synchronous FETs conduction time

Diode rectification with DCM at Io <10%

Burst Mode at no-Load or very light load

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Controller Options: Analog UCC28950 with “Green” Features

• 20% Accurate Adaptive ZVS Dead Band Over Wide Operating Range • Adaptive Timing MOSFET Rectifier Outputs • Programmable SR ON/OFF Control • Programmable Burst Mode at Very Light or No Load • Programmable Slope Compensation • Peak Current or Voltage Mode Control • 20-mA, 1.5% Accurate VREF Regulator • Closed Loop Soft Start with Enable • 8% Accurate Switching Frequency Setting • Bi-directional Synchronization • 3% Accurate Cycle-by-Cycle Current Limit • VDD Under Voltage Lockout • Thermal Shutdown • 150 µA Start Up Current • Standard TSSOP-24 Package • Wide Temperature Range: -40 to 125 °C

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10

4

13

2

1

12

GND

VREF

VDD

5V LDO

EN

UVLO Comp.

7.3V rise6.7V fall

VDD

VDD

RT

Cycle-by-Cycle Ilim

SS/EN

Thermal Shutdown

Is

OUTB

OUTA

LogicBlock

CLK

COMP

EA-

RSUM

4

8

10

OUTD

OUTC

VDD

ReferenceGenerator

8DELAB

8DELCD

Programmable Delay CD

Programmable Delay AB

PWM COMP

RAMP

4EA+

4CS

Ramp Summing4

Oscillator

8

10

OUTF

OUTE

8DELEF

Programmable Delay EF

8ADELEF

10ADEL

SYNC4

2 VLight Load Efficiency

Block

DCM TMIN

Soft Start & Enable with 0.55 V ThersholdSynchronization

Block

ON/OFF

CS

CS

CS

CS

CS0.8V2.8V

Lower “+” Input is Dominant

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Digital Controller UCD3K – PSFB + Sync-Rec Configuration

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Digital Controller C2000 – PSFB + Sync-Rec Configuration

Secondary SideController

Piccolo-A

Comp

ADC

PWM

Q11

Q1

Q2

Q8

Q7

Q13

Q14-Q15

Secondary SideController

Piccolo-A

Comp

ADC

PWM

Secondary SideController

Piccolo-A

Comp

ADC

PWM

Q11

Q1

Q2

Q8

Q7

Q13

Q14-Q15

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Summary

Step by Step design procedure for “Platinum” Server Power Supply is provided

Power Losses Budget and break down of conduction and switching losses have been discussed

Recommendation how to achieve ZVS and minimize switching losses are provided

Digital and Analog Controllers supporting high efficiency operation over whole load current range are listed

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Thanks and Any Questions?

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References

REFERENCES 1. Fasullo, G.; Kania, M. & Pitts, A. (2008). The Green revolution in DC power systems, Proceedings of 30th International

Telecommunications Energy Conference, INTELEC’2008, pp. 1-7, ISBN: 978-1-4244-2056-8, San Diego, CA, USA, September 2008, IEEE

2. Mammano, R. (2006). Improving power supply efficiency - The global perspective, Texas Instruments Power Supply Design Seminar, Topic 1, SEM-1700, 2006

3. Rais Miftakhutdinov, “Power Saving Control Strategies and Their Implementation in DC/DC Converter for Data and Telecommunications Power Supply”, Proc. of IEEE Applied Power Electronics Conf., 2010, pp. 1897-1903.

4. Rais Miftakhutdinov, Zhenyu Yu, “New Controller Addresses Energy Saving in Server Power System”, Power Systems Design North America, January/February Issue, 2010, pp. 51-52.

5. Rais Miftakhutdinov, “Power Saving Solutions in DC/DC Converter for Data and Telecommunications Power System”, Proc. of PEDS-2009, Taipei, November 2009.

6. Rais Miftakhutdinov, “Energy Saving Drives New Approaches to Telecommunications Power System”, Chapter in the book “Telecommunications”, Intech, 2010

7. ENERGY STAR® program requirements for computer servers, version 1.0: http://www.energystar.gov/index.cfm?c=ent_servers.enterprise_servers

8. 80 PLUS Power Supplies Requirements: http://www.plugloadsolutions.com/80PlusPowerSupplies.aspx 9. Climate Savers Computing Initiative: http://www.climatesaverscomputing.org/ 10. Texas Instruments, Datasheet: TMS320F28023 PiccoloTM microcontroller,

http://focus.ti.com/docs/prod/folders/print/tms320f28023.html 11. Texas Instruments, Datasheet: UCD3020 Digital Power Controller, http://focus.ti.com/docs/prod/folders/print/ucd3020.html 12. Texas Instruments, Datasheet: Green Phase-Shifted Full-Bridge controller with synchronous rectification, UCC28950,

http://focus.ti.com/docs/prod/folders/print/ucc28070.html