1

Sequential Systems

• A combinational system is a system whose outputs depend only upon its current inputs.

• A sequential system is a system whose outputs depends on the current inputs and the system’s current state.

• All systems we have looked at to date have been combinational systems.

2

Flip-Flops/ Latches

• Latches and Flip-Flops are devices that can have two internal states (0,1)

• The output of a latch or a Flip-Flop (FF) is dependent upon its CURRENT STATE and CURRENT INPUTS.

• Latches and FF’s are the simplest examples of sequential systems.

3

Set/ Reset Nor Latch (SR Nor Latch)

S R Ps NsL L Q QL H X LH L X HH H X -

Present State Next State

S Q

R Q’

R

S

Q

Q’

Implementation

Symbolinputs,outputs high true.

S R Ps Ns0 0 Q Q0 1 X 01 0 X 11 1 X -

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Set/ Reset Nor Latch (SR Nor Latch)

S Q

R Q’

Operation Example:

S R Ps Ns0 0 Q Q0 1 X 01 0 X 11 1 X - Not Allowed

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SR latch Operation

R=0

S=0 1

Q

Q’

SET operation

1 0

0 1 R=0 1

S=0

Q

Q’

RESET operation

1 0

1 0

0 1

1 0

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SR latch Operation (cont)

R=0

S=0

Q

Q’

Stable when S=R=0, Q=1

0

0

1

1

R=0

S=0

Stable when S=R=0, Q’=1

1

1

0

0

Q

Q’

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What about S=R=1? (Set,Reset both true?)

R=0 1

Q

Q’ 0

0

1 0

1 0

S=0 1

Assume that S, R both transition to 1 simultaneously.

Q becomes ‘0’, but Q’ remains ‘0’! Outputs are no longer complements of each other.

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What happens when S,R return to 0?

R=1 0Q

Q’

0 1 0 1 0 1

S=1 0

0 1 0 1 0 1

Oscillation occurs if S,R return to 0 simultaneously! At some point the system will settle into a stable condition. The bottom line is that S=R=1 is an illegal input condition (or design the SR latch such that one input is DOMINANT).

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SR Latch, R dominant

R

Q’S

S R Ps Ns0 0 Q Q0 1 X 01 0 X 11 1 X 0

Q

When S=R=1, then acts as a RESET (R is dominant)

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SR Nor Latch -- Characteristic Equation

NotAllowed

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Terminology• A bistable memory device is the generic term for

the elements we are studying• We can use the term latch or flip-flop to refer to

these devices– latch: bistable memory device with level sensitive

triggering (no clock)– flip-flop: bistable memory device with edge-triggering

(with clock)

• Warning: Your author (Roth) uses the terminology Flip-Flop and Clocked Flip-Flop instead of latch and Flip-Flop– latch, flip-flop more standard

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Data Flip-Flop (D-FF, falling edge triggered)

CK D Ps Ns0 X Q Q1 X Q Q10 D X D

Only time D-FF changes state is on a CLOCK EDGE. This D-FF is falling edge triggered. Changes state to whatever the D value was just before the clock neg. edge occurred. (Q+ = D)

D Q

CK Q’

CK is the clock input. D input is only sampled at a clock edge.

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A Clock Waveform

time

voltage

f = 1/

Pw rising edge falling edge

- period (in seconds)Pw - pulse width (in seconds)

f - frequency pulse width (in Hertz)

duty cycle - ratio of pulse width to period (in %) duty cycle = Pw /

millisecond (ms)10-3

Kilohertz (KHz)103

microsecond (s)10-6

Megahertz (MHz)106

nanosecond (ns)10-9

Gigahertz (GHz)109

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D-FF Operation Example 1

D

CK

Q

On falling edge of CK, D=1, so Q=1

On falling edge of C, D=0, so Q=0

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D-FF Operation Example 2

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Clocked T Flip-Flop (falling edge triggered)

T Q

CK Q’

CK is the clock input.

T input sampled only at a clock edge.

Retain State

Synchronous Toggle

CK T Ps Ns0 X Q Q1 X Q Q10 0 Q Q10 1 Q Q’

T-FF

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Clocked T-FF Operation Example

T=1Toggle

T=0, RetainState

T=1Toggle

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Clocked JK Flip-Flop (falling edge triggered)

CK J K Ps Ns0 X X Q Q1 X X Q Q10 0 0 Q Q 10 0 1 X 010 1 0 X 110 1 1 Q Q’

J Q

CK

Q’

CK is the clock input.

J,K inputs are sampled only at a clock edge.K

Retain State

Synchronous Reset

Synchronous Set

Synchronous Toggle

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Clocked JK-FF Operation Example

J=1, K=0Set

J=0, K=1Reset

J=1, K=1Toggle

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JK-FF Implementation

D Q

CK Q’CK

QK

J

This is a falling edge triggered JK-FF.

We will derive this implementation at a later date.

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Master-Slave JK-FF Implementation

S

R

Master Slave

S

R

Q

Q’

P

P’

J

K

22

J

Q

CK

Q’

K

CLR PRE

D

Q

CK

Q’

CLR

Clocked FF’s with Asynchronous Preset and Clear Inputs

The small inversion symbol on the preset and clear inputs indicatethat these are active for a 0 state.These inputs are asynchronous, meaning that they override the clockand JK inputs (or clock and D inputs).CLR active Q = 0PRE active Q=1

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Unclocked T-FF

T

FFS

Q’Q

R

Q’Q

Q’Q

T

FF

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Unclocked JK-FF

Q’Q

J

FF

FFS

Q’Q

R

K

Q’Q

JK

J

K

Q

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D-FF Register

Q’3 Q1

D3CK

CLR

Q’2 Q1

D2CK

CLR

Q’1 Q1

D1CK

CLR

Q’0 Q0

D0CK

CLR

1 1 1

Clear

Clock

0 ->1 0 ->1 0 ->0 0 ->1

0

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What do you have to know?

• Definition of a sequential system• SR Nor latch, • Clocked D-FF, T-FF, JK-FF (Master-Slave and

Edge-Triggered)– Timing diagrams, state tables, characteristic eqns.

• Unclocked T-FF, JK-FF – Timing diagrams, state tables, characteristic eqns.