Sequential Multiplication

Lecture L6.4

Multiplication

13x11 1313 143 = 8Fh

1101 x1011 1101 1101 100111 0000 100111 1101 10001111

Multiplication

1101 x1011 1101 1101 100111 0000 100111 1101 10001111

11010000101101101101 adsh1101 10011110 adsh

1001111 sh1101 10001111 adsh

Sequential Multiplier

Use BTN4 to load SWinto Ra and Rb and thendisplay product in Rp

Control signals:aloadbloadploaddmselm2sel(1:0) mult_startmult_done

x7segclr

cclk

binbcd

r

x

seq_multB A

P

16p

bs

Raregc

aload

8

8

ain

as

clr

clkRbregc

bload

8

8

bin

SW(1:8)

clr

clk

0 & as

U5 (mux4g)

U1 (dmux2g)

Rpregc

ploadclr

clk

8

0 & bs

16 1616

A(3:0) AtoG(6:0)

16

16

a16 b16

pout

dmsel

m2sel(1:0)

clr

clkstart

done

Three consecutivepushings of BTN4Start multiplicationWait for mult_done

sA

sB

sC

sD

sE

sF

BTN4

Wait for BTN4 up

! BTN4

BTN4

BTN4

! BTN4

! BTN4

BTN4

BTN4

BTN4

! BTN4

! BTN4

! BTN4

Wait for BTN4 down

Wait for BTN4 down

Wait for BTN4 down

Wait for BTN4 up

Wait for BTN4 up

sH

sG

! mult_done

mult_start <= ‘1’

mult_doneControl signals:aloadbloadploaddmselm2sel(1:0)mult_startmult_done

VHDLCanonical Sequential Network

Sta

te R

egis

ter

Com

bina

tion

alN

etw

ork

x(t)

s(t+1) s(t)

z(t)clk

init

present state

present input

nextstate

present output

process(clk, init)

process(present_state, x)

-- Title: Mult Control Unit

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity mult_control is

port (

clr: in STD_LOGIC;

clk: in STD_LOGIC;

BTN4, mult_done: in STD_LOGIC;

m2sel: out STD_LOGIC_VECTOR (1 downto 0);

aload, bload, dmsel, mult_start: out STD_LOGIC;

pload: out STD_LOGIC

);

end mult_control;

architecture mult_control_arch of mult_control is

type state_type is (sA, sB, sC, sD, sE, sF, sG, sH);

signal current_state, next_state: state_type;

begin

C1: process(current_state, BTN4, mult_done)

begin

-- Initialize all outputs

pload <= '0';

dmsel <= '0';

aload <= '0';

bload <= '0';

m2sel <= "00";

mult_start <= '0';

mult_control.vhd

case current_state is

when sA => --wait for BTN4 up

if BTN4 = '1' then

next_state <= sA;

m2sel <= "11";

else

next_state <= sB;

end if;

when sB => --wait for BTN4 down

if BTN4 = '1' then

next_state <= sC;

aload <= '1'; -- A <- SW

m2sel <= "00";

else

next_state <= sB;

m2sel <= "11";

end if;

sA

sB

sC

sD

sE

sF

BTN4

Wait for BTN4 up

! BTN4

BTN4

BTN4

! BTN4

! BTN4

BTN4

BTN4

BTN4

! BTN4

! BTN4

! BTN4

Wait for BTN4 down

Wait for BTN4 down

Wait for BTN4 down

Wait for BTN4 up

Wait for BTN4 up

sH

sG

! mult_done

mult_start <= ‘1’

mult_done

when sC => --wait for BTN4 up

if BTN4 = '1' then

next_state <= sC;

m2sel <= "00";

else

next_state <= sD;

end if;

when sD => --wait for BTN4 down

if BTN4 = '1' then

next_state <= sE;

dmsel <= '1';

bload <= '1'; -- B <- SW

m2sel <= "01";

else

next_state <= sD;

m2sel <= "00";

end if;

sA

sB

sC

sD

sE

sF

BTN4

Wait for BTN4 up

! BTN4

BTN4

BTN4

! BTN4

! BTN4

BTN4

BTN4

BTN4

! BTN4

! BTN4

! BTN4

Wait for BTN4 down

Wait for BTN4 down

Wait for BTN4 down

Wait for BTN4 up

Wait for BTN4 up

sH

sG

! mult_done

mult_start <= ‘1’

mult_done

when sE => --wait for BTN4 up

if BTN4 = '1' then

next_state <= sE;

m2sel <= "01";

else

next_state <= sF;

end if;

when sF => --wait for BTN4 down

if BTN4 = '1' then

next_state <= sG;

pload <= '1';

m2sel <= "11";

mult_start <= '1';

else

next_state <= sF;

m2sel <= "01";

end if;

sA

sB

sC

sD

sE

sF

BTN4

Wait for BTN4 up

! BTN4

BTN4

BTN4

! BTN4

! BTN4

BTN4

BTN4

BTN4

! BTN4

! BTN4

! BTN4

Wait for BTN4 down

Wait for BTN4 down

Wait for BTN4 down

Wait for BTN4 up

Wait for BTN4 up

sH

sG

! mult_done

mult_start <= ‘1’

mult_done

when sG => --mult_start <= '1'

next_state <= sH;

mult_start <= '1';

when sH => --wait for mult result

if mult_done = '0' then

next_state <= sH;

pload <= '1';

m2sel <= "11";

else

next_state <= sA;

m2sel <= "01";

end if;

end case;

end process C1;

sA

sB

sC

sD

sE

sF

BTN4

Wait for BTN4 up

! BTN4

BTN4

BTN4

! BTN4

! BTN4

BTN4

BTN4

BTN4

! BTN4

! BTN4

! BTN4

Wait for BTN4 down

Wait for BTN4 down

Wait for BTN4 down

Wait for BTN4 up

Wait for BTN4 up

sH

sG

! mult_done

mult_start <= ‘1’

mult_done

statereg: process(clk, clr) -- the state register

begin

if clr = '1' then

current_state <= sA;

elsif (clk'event and clk = '1') then

current_state <= next_state;

end if;

end process statereg;

end mult_control_arch;

mpp

11010000101101101101 adsh1101 10011110 adsh

1001111 sh1101 10001111 adsh

a =

c:b =mpp (multiply partial product) if b(0) = 1 then adsh else sh end if;

seq_mult Datapath

8bin

mpp

M1m1sel

10

creg

cload

8

8

y1

c1

clr

clkb

regbload

8b1

clr

clka

regaload

8

8

a

a1

clr

clk

b

8

y1

y2

y2

pH pL

mpplibrary IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

entity mpp is

generic(width:positive);

port (

a: in STD_LOGIC_VECTOR (width-1 downto 0);

b: in STD_LOGIC_VECTOR (width-1 downto 0);

c: in STD_LOGIC_VECTOR (width-1 downto 0);

y1: out STD_LOGIC_VECTOR (width-1 downto 0);

y2: out STD_LOGIC_VECTOR (width-1 downto 0)

);

end mpp;

architecture mpp_arch of mpp isbegin mp1: process(a,b,c) variable AVector: STD_LOGIC_VECTOR (width downto 0); variable CVector: STD_LOGIC_VECTOR (width downto 0); variable yVector: STD_LOGIC_VECTOR (width downto 0); begin AVector := '0' & a; CVector := '0' & c;

if b(0) = '1' then yVector := AVector + CVector;

else yVector := CVector;

end if;y1 <= yVector(width downto 1);y2 <= yVector(0) & b(width-1 downto 1);

end process mp1; end mpp_arch;

s0

s1

s2

s3

! start

Wait for start signal

! zdly

Load a and b

Reset delay counter

start

zdly

done <= ‘1’

width clock delays

seq_mult Control

-- Title: Sequential Multiplier Control Unit

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity seq_mult_control is

port (

clr: in STD_LOGIC;

clk: in STD_LOGIC;

start, zdly: in STD_LOGIC;

done, msel: out STD_LOGIC;

aload, bload, cload, dload: out STD_LOGIC

);

end seq_mult_control;

architecture seq_mult_control_arch of seq_mult_control is type state_type is (s0, s1, s2, s3); signal current_state, next_state: state_type;

begin

C1: process(current_state, start, zdly) begin

s0

s1

s2

s3

! start

Wait for start signal

! zdly

Load a and b

Reset delay counter

start

zdly

done <= ‘1’

width clock delays

C1: process(current_state, start, zdly) begin case current_state is when s0 =>

if start = '1' then next_state <= s1; else

next_state <= s0; end if;

when s1 => next_state <= s2;

when s2 => if zdly = '1' then next_state <= s3; else

next_state <= s2; end if;

when s3 =>

next_state <= s0; end case; end process C1;

s0

s1

s2

s3

! start

Wait for start signal

! zdly

Load a and b

Reset delay counter

start

zdly

done <= ‘1’

width clock delays

statereg: process(clk, clr) -- the state register

begin

if clr = '1' then

current_state <= s0;

elsif (clk'event and clk = '1') then

current_state <= next_state;

end if;

end process statereg;

C2: process(current_state, zdly)

begin

-- Initialize all outputs

done <= '0';

aload <= '0';

bload <= '0';

cload <= '0';

dload <= '0';

msel <= '0';

case current_state is

when s0 =>

null;

8bin

mpp

M1m1sel

10

creg

cload

8

8

y1

c1

clr

clkb

regbload

8b1

clr

clka

regaload

8

8

a

a1

clr

clk

b

8

y1

y2

y2

pH pL

when s1 =>

msel <= '1'; -- load a and b

aload <= '1';

bload <= '1';

dload <= '1'; -- reload delay count

when s2 =>

msel <= '0'; -- load b and c

if zdly = '0' then

bload <= '1';

cload <= '1';

end if;

when s3 => -- done

done <= '1';

when others =>

null;

end case;

end process C2;

end seq_mult_control_arch;

8bin

mpp

M1m1sel

10

creg

cload

8

8

y1

c1

clr

clkb

regbload

8b1

clr

clka

regaload

8

8

a

a1

clr

clk

b

8

y1

y2

y2

pH pL

-- An n-bit down counter with load

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity delay_cnt is

generic(width:positive);

port (

d: in STD_LOGIC_VECTOR (width-1 downto 0);

load: in STD_LOGIC;

clr: in STD_LOGIC;

clk: in STD_LOGIC;

Z: out STD_LOGIC -- Z = 1 if q = 0

);

end delay_cnt;

delay_cnt.vhd

architecture delay_cnt_arch of delay_cnt is

signal q1: STD_LOGIC_VECTOR(width-1 downto 0);

begin

process(clk)

begin

if clr = '1' then

for i in width-1 downto 0 loop

q1(i) <= '0';

end loop;

elsif (clk'event and clk = '1') then

if (load = '1') then

q1 <= d;

else

q1 <= q1 - 1;

end if;

end if;

end process;

delay_cnt.vhd (cont.)

process(q1)

variable Zv: STD_LOGIC;

begin

Zv := '0';

for i in 0 to width-1 loop

Zv := Zv or q1(i); -- Z = '0' if all q1(i) = '0'

end loop;

Z <= not Zv;

end process;

end delay_cnt_arch;

delay_cnt

mux2g

mpp

a_reg

b_reg

c_reg

seq_mult_control

mpp

mux

-- Title: Multiply Test

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.std_logic_unsigned.all;

use work.mult_components.all;

entity mult is

port(

mclk : in STD_LOGIC;

bn : in STD_LOGIC;

SW : in STD_LOGIC_VECTOR(1 to 8);

BTN4: in STD_LOGIC;

led: out std_logic;

ldg : out STD_LOGIC;

LD : out STD_LOGIC_VECTOR(1 to 8);

AtoG : out STD_LOGIC_VECTOR(6 downto 0);

A : out STD_LOGIC_VECTOR(3 downto 0)

);

end mult;

mult2.vhd

architecture mult_arch of mult is

signal r, p, pout, x, b16, a16: std_logic_vector(15 downto 0);

signal as, bs, ain, bin: std_logic_vector(7 downto 0);

signal clr, clk, cclk, bnbuf, start, done: std_logic;

signal clkdiv: std_logic_vector(26 downto 0);

signal aload, bload, pload, dmsel: STD_LOGIC;

signal m2sel: STD_LOGIC_VECTOR (1 downto 0);

constant bus_width8: positive := 8;

constant bus_width16: positive := 16;

x7segclr

cclk

binbcd

r

x

seq_multB A

P

16p

bs

Raregc

aload

8

8

ain

as

clr

clkRbregc

bload

8

8

bin

SW(1:8)

clr

clk

0 & as

U5 (mux4g)

U1 (dmux2g)

Rpregc

ploadclr

clk

8

0 & bs

16 1616

A(3:0) AtoG(6:0)

16

16

a16 b16

pout

dmsel

m2sel(1:0)

clr

clkstart

done

begin

U00: IBUFG port map (I => bn, O => bnbuf);

led <= bnbuf;

ldg <= '1'; -- enable 74HC373 latch

clr <= bnbuf;

-- Divide the master clock (50Mhz)

process (mclk)

begin

if mclk = '1' and mclk'Event then

clkdiv <= clkdiv + 1;

end if;

end process;

clk <= clkdiv(0); -- 25 MHz

cclk <= clkdiv(17); -- 190 Hz

a16 <= "00000000" & as;

b16 <= "00000000" & bs;

U1: dmux2g generic map(width => bus_width8) port map

(y => SW, a => ain, b => bin, sel => dmsel);

U2a: reg generic map(width => bus_width8) port map

(d => ain, load => aload, clr => clr, clk =>clk, q => as);

U3b: reg generic map(width => bus_width8) port map

(d => bin, load => bload, clr => clr, clk =>clk, q => bs);

U4p: reg generic map(width => bus_width16) port map

(d => p, load => pload, clr => clr, clk =>clk, q => pout);

U5: mux4g generic map(width => bus_width16) port map

(a => a16, b => b16, c => pout, d => pout, sel => m2sel,

y => r);

U6: binbcd port map

(B => r, P => x);

U7: x7seg port map

(x => x, cclk => cclk, clr => clr, AtoG => AtoG, A => A);

U8: mult_control port map

(clr => clr, clk => clk, BTN4 => BTN4, mult_start => start, m2sel => m2sel, aload => aload, bload => bload,

mult_done => done, dmsel => dmsel, pload => pload);

U9: seq_mult generic map(width => bus_width8) port map

(A => as, B => bs, clr => clr, clk =>clk, start => start,

done => done, P => p);

LD <= SW;

end mult_arch;

Comparison to *

No. of slices No. of Flip-flops8 x 8 = 16Combinational * 79 (3%) 58 (1%)Sequential 73 (3%) 92 (1%)

16 x 16 = 32Combinational * 95 (4%) 60 (1%)Sequential 87 (3%) 109 (1%)