Sequential Logic Circuit

Yong Heui Cho @ Mokwon University

Basic Computer Design

3. Basic Computer Architecture

4. Combinational Logic Circuit

5. Sequential Logic Circuit

6. CPU Architecture - Basic

Sequential Logic • Sequential circuit consists of feedback path

and several memory elements

• Sequential circuit = Combinational Logic + Memory Elements

3 □ Courtesy to M.Y. IDRIS & N.M. NOOR, Sequential Circuit, slideshare.

Sequential Logic & CPU

4 simplified CPU model

Memory Element • Memory element device that can remember a

value for a certain period, or change value based on the input instruction

• Example: Latch and flip-flop

Commands for latches include set and reset commands

5 □ Courtesy to M.Y. IDRIS & N.M. NOOR, Sequential Circuit, slideshare.

Latch & Flip-flop • Latch: basic memory element to

store 1 bit

• Flip-flop: commonly clocked latch

latch flip-flop SR flip-flop

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Flip-flop

• Flip-flop is a memory element which change its condition based on clock signal

• Clock is a square waveform

7 □ Courtesy to M.Y. IDRIS & N.M. NOOR, Sequential Circuit, slideshare.

SR Latch • Basic SR latch

• Criteria table:

8

)()1( tQRStQ

□ Courtesy to M.Y. IDRIS & N.M. NOOR, Sequential Circuit, slideshare.

SR Latch Circuit

• NAND or NOR circuits

9

74LS279

Gated SR Flip-flop • SR latch, enable (EN) input, and 2 NAND gates

• Clear and preset

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D Flip-flop • D = delay or data

• Make input R the same as S’ = D latch with gate

• D flip-flop eliminates invalid condition of SR latch.

11 □ Courtesy to M.Y. IDRIS & N.M. NOOR, Sequential Circuit, slideshare.

Edge Triggered Flip-flop • Edge triggered flip-flops are marked with “>”

symbol at clock input.

Positive edge triggered flip-flop

Negative edge triggered flip-flop

12

□ Courtesy to M.Y. IDRIS & N.M. NOOR, Sequential Circuit, slideshare.

Gated D Flip-flop • When EN is HIGH

– D=HIGH – latch is in SET

– D=LOW – latch is in RESET

• Therefore, when EN is HIGH, Q will follow input D

• Criteria table for positive edge trigger:

13

DtQ )1(

□ Courtesy to M.Y. IDRIS & N.M. NOOR, Sequential Circuit, slideshare.

Parallel Data Transaction • Usage: to transfer 4-bit data inputs to outputs

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JK Flip-flop • JK flip-flop

• Criteria table:

15

)()()1( tQKtQJtQ

T Flip-flop • T = Toggle

• T flip-flop single input version for JK flip-flop, formed by combining JK input

• Criteria table:

16

)()()1( tQTtQTtQ

□ Courtesy to M.Y. IDRIS & N.M. NOOR, Sequential Circuit, slideshare.

Frequency Divider

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D flip-flop

T flip-flop

Master Slave Flip-flop • Master is activated when positive edge and

Slave is activated when clock negative edge triggered.

• Master Slave Flip-flop

18 □ Courtesy to M.Y. IDRIS & N.M. NOOR, Sequential Circuit, slideshare.