Sequential Circuit

Sequential Circuit Latch & Flip-flop

MOHD. YAMANI IDRIS/ NOORZAILY MOHAMED NOOR

ContentsIntroductionMemory ElementLatchSR latchD latchFlip-flopSR flip-flopD flip-flopJK flip-flopT flip-flop


IntroductionSequential circuit consists of feedback path and several memory elements

Sequential circuit = Combinational Logic + Memory Elements


IntroductionThere are two types of sequential circuit Synchronous output change at certain timeAsynchronous output change any timeMultivibrator sequential circuit category can beBistable consist of two stable conditionMonostable consist of one stable conditionAstable - no stable conditionBistable logic device is latch and flip-flopLatch and flip-flop differ by the method used to change stable condition


Memory ElementMemory element device that can remember a value for a certain period, or change value based on the input instructionExample: Latch and flip-flop

Commands for latches include set and reset commands


Memory ElementFlip-flop is a memory element which change its condition based on clock signal

Clock is a square waveform


Memory ElementThere are two types of trigger/activatorPulse triggeredEdge triggeredPulse triggeredLatchON=1, OFF=0Edge triggeredFlip-flopPositive edge triggered (ON=when 0 to 1, OFF=other time)Negative edge triggered (ON=when 1 to 0, OFF=other time)


SR LatchOutput has complement: Q and QWhen Q HIGH, latch in SET conditionWhen Q LOW, latch in RESET conditionFor SR with active high input (also known as NOR gate latch)R = HIGH (and S=LOW) RESET conditionS = HIGH (and R=LOW) SET conditionBoth LOW no condition changeBoth HIGH - Q and Q becomes LOW (invalid)


SR Latch with GateSR latch + enable (EN) input amd 2 NAND gate - SR Latch with Gate


SR Latch with GateOutput change (if needed) only when EN at HIGH conditionWhich condition is invalid?Criteria Table


D Latch with GateMake input R the same as S - D Latch with GateD latch eliminate invalid condition in SR latch


D Latch with GateWhen EN is HIGHD=HIGH latch is in SET D=LOW latch is in RESETTherefore, when EN is HIGH, Q will follow input DCriteria Table:


Edge Triggered Flip-flopFlip-flop bistable synchronous deviceOutput change its condition at certain point on input trigger named clockCondition change either at positive edge (up edge) or at negative edge (down edge) of clock signal

clock signal

Positive EdgeNegative Edge


Edge Triggered Flip-flopflip-flop SR, D and JK edge triggered is marked with > symbol at clock input

Positive edge triggered flip-flop

Negative edge triggered flip-flop


SR Flip-flopSR flip-flop, at edge triggered clock pulseS=HIGH (and R=LOW) SET conditionR=HIGH (and S=LOW) RESET conditionBoth input LOW no changeBoth input HIGH - invalidCriteria table of edge triggered SR flip-flop


SR Flip-flopIt consist of three partsNAND latchPulse steering circuitPulse transaction circuit detector (or edge detector)Pulse transaction detector circuit will detect up trigger (or down) and produce very short duration spike


D Flip-flopD flip-flop: one input D (data)D=HIGH SET conditionD=LOW RESET conditionQ will follow D at clock edge To change SR flip-flop to D flip-flop: add inverter


D Flip-flopUsage: Parallel data transactionTo transfer logical output circuit X,Y,Z to Q1, Q2, and Q3 to be stored


JK Flip-flopThere is no invalid conditionThere is toggle condition J=HIGH (and K=LOW) SET conditionK=HIGH (and J=LOW) RESET conditionBoth input LOW no changeBoth input HIGH toggle


JK Flip-flopJK Flip-flop

Criteria Table


T Flip-flopT flip-flop single input version for JK flip-flop, formed by combining JK input

Criteria Table


T Flip-flopUsage: As frequency divider


Asynchronous InputSR input, D and JK is synchronous input. Where data from input will be transferred to flip-flop output only when edge triggered of clock pulseAsynchronous Input free change condition from pulse clock. Example: preset (PRE) and clear (CLR) [or direct set (SD) and direct reset (RD)]When PRE=HIGH, Q immediately HIGHWhen CLR=HIGH, Q immediately LOWFlip flop function as normal when both PRE and CLR is LOW


Asynchronous InputJK flip-flop with active LOW preset and clear


Master Slave Flip-flopMaster is activated when positive edge and Slave is activated when clock negative edge triggeredMaster Slave Flip-flop


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Sequential Circuit