September 2019 - Microchip Technology...Start-up macro (DVDT) Load signature detection (RES DET) Classification macro (CLASS) Voltage and current monitoring registers (VMC) ADC interfacing

PD69108/FDatasheet

8-Port PSE PoE ManagerSeptember 2019

8-Port PSE PoE Manager

Microsemi Proprietary and Confidential. PD-000307817 PD69108/F Datasheet Revision 3.0

Contents

1 Revision History ............................................................................................................................. 11.1 Revision 3.0 ........................................................................................................................................ 11.2 Revision 2.0 ........................................................................................................................................ 11.3 Revision 1.7 ........................................................................................................................................ 11.4 Revision 1.6 ........................................................................................................................................ 11.5 Revision 1.5 ........................................................................................................................................ 11.6 Revision 1.4 ........................................................................................................................................ 11.7 Revision 1.3 ........................................................................................................................................ 11.8 Revision 1.2 ........................................................................................................................................ 11.9 Revision 0.6 ........................................................................................................................................ 11.10 Revision 0.5 ...................................................................................................................................... 21.11 Revision 0.4 ...................................................................................................................................... 21.12 Revision 0.3 ...................................................................................................................................... 21.13 Revision 0.2 ...................................................................................................................................... 21.14 Revision 0.1 ...................................................................................................................................... 2

2 Product Overview .......................................................................................................................... 32.1 Features .............................................................................................................................................. 32.2 Typical Application ............................................................................................................................. 4

3 Functional Descriptions ................................................................................................................. 53.1 Logic Main Control Module ................................................................................................................ 5

3.1.1 Line Detection Generator ........................................................................................................................ 5

3.1.2 Classification Generator .......................................................................................................................... 6

3.1.3 Current Limiter ........................................................................................................................................ 6

3.1.4 Main MOSFET .......................................................................................................................................... 6

3.1.5 Analog-to-Digital Converter (ADC) .......................................................................................................... 6

3.1.6 Power on Reset (POR) ............................................................................................................................. 6

3.1.7 Voltage Regulator .................................................................................................................................... 6

3.1.8 CLK ........................................................................................................................................................... 7

3.2 Application Information ..................................................................................................................... 73.2.1 Line Detection ......................................................................................................................................... 7

3.2.2 Legacy (Capacitor) Detection .................................................................................................................. 7

3.2.3 Classification ............................................................................................................................................ 7

3.2.4 Port Start Up ............................................................................................................................................ 7

3.2.5 Over-Load Detection and Port Shut Down .............................................................................................. 8

3.2.6 Disconnect Detection .............................................................................................................................. 8

3.2.7 Over-Temperature Protection ................................................................................................................. 8

3.2.8 V MAIN Out-of-Range Protection ............................................................................................................ 8


Microsemi Proprietary and Confidential. PD-000307817 PD69108/F Datasheet Revision 3.0

4 Electrical Specifications ................................................................................................................ 104.1 Dynamic Characteristics ................................................................................................................... 114.2 Absolute Maximum Ratings .............................................................................................................. 134.3 Power Dissipation Information ......................................................................................................... 13

5 Pin Descriptions ........................................................................................................................... 14

6 Package Specification ................................................................................................................... 186.1 RoHS and Solder Reflow Information ............................................................................................... 186.2 Thermal Specifications ..................................................................................................................... 206.3 Tape and Reel Packaging Information .............................................................................................. 21

7 Ordering Information ................................................................................................................... 23


Microsemi Proprietary and Confidential. PD-000307817 PD69108/F Datasheet Revision 3.0 1

1 Revision HistoryThe revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

1.1 Revision 3.0Revision 3.0 is published in September 2019. The following is a summary of changes made in revision 3.0 of this document.

The package marking is updated in the ordering information table. For more information, see .Ordering Information (see page 23)

Figure 5 is updated.

1.2 Revision 2.0Revision 2.0 was published in March 2018. The format of this document was updated to the latest template.

Part marking is updated. For more information, see .Ordering Information (see page 23)

1.3 Revision 1.7Revision 1.7 was published in July 2015. In revision 1.7 of this document, a NOTE was added specifying "Fuses per port are not required for use in circuits with total power level of up to 3 kW."

1.4 Revision 1.6Revision 1.6 was published in June 2013. In revision 1.6 of this document, a full temperature range P/N was added.

1.5 Revision 1.5Revision 1.5 was published in December 2012. In revision 1.5 of this document, Tape and Reel Data was added.

1.6 Revision 1.4Revision 1.4 was published in February 2012. In revision 1.4 of this document, I lim was updated according to UL and IEEE standards.

1.7 Revision 1.3Revision 1.3 was published in January 2012. In revision 1.3 of this document, the Footer address was updated.

1.8 Revision 1.2Revision 1.2 was published in October 2011. In revision 1.2 of this document, Θ was added.JC

1.9 Revision 0.6Revision 0.6 was published in August 2011. In revision 0.6 of this document, SPI Timing data was added.



1.10 Revision 0.5Revision 0.5 was published in April 2011. In revision 0.5 of this document, minor corrections were made.

1.11 Revision 0.4Revision 0.4 was published in July 2010. In revision 0.4 of this document, the catalog numbers metrology and Ordering Information was updated.

1.12 Revision 0.3Revision 0.3 was published in April 2010. In revision 0.3 of this document, minor corrections were made.

1.13 Revision 0.2Revision 0.2 was published in January 2010. In revision 0.2 of this document, the Power Dissipation was updated.

1.14 Revision 0.1Revision 0.1 was published in November 2009. It was the initial release of this document.



2 Product OverviewMicrosemi’s PD69108/F Power over Ethernet (PoE) manager integrates power, analog, and state-of-the-art logic into a single 48-pin, plastic QFN package. The device is used in Ethernet switches and midspans, enabling network devices to share power and data over the same cable. The PD69108/F device is an eight port, mixed-signal, high-voltage PoE driver.

The PD69108/F enables detection of IEEE802.3at-2009 compliant Type 1 and Type 2 Power Devices (PDs). This ensures safe power feeding and disconnection of ports with full digital control and a minimum of external components.

The PD69108/F device executes all real-time functions as specified in the IEEE802.3af-2003 (AF) and IEEE802.3at-2009 high power (AT) standards. This includes load detection, AF, and AT classification. In addition, the PD69108/F device features Multiple Classification Attempts (MCA) port status monitoring. This provides system-level activities such as power management and MIB support for system management.

The PD69108/F device is designed to detect and disable disconnected ports. This utilizes the DC disconnection methods, as specified in the IEEE 802.3af-2003 and IEEE802.3at-2009 standards.

The PD69108/F device provides PD protection such as over-load, under-load, over-voltage, and short-circuiting. It supports supply voltages ranging from 44 to 57 voltage DC (V ) with no additional power DC

supply sources. The chip includes built-in internal thermal protection. Optionally, the PD69108/F can detect legacy/pre-standard PD devices.

The PD69108/F is a low-power device using an internal MOSFET and an external 0.36 Ω sense resistor.

2.1 FeaturesIEEE802.3af-2003 compliantIEEE802.3at-2009 compliant, including two-event classificationSupports pre-standard PD detectionSupports Cisco devices detectionSingle DC voltage input (44 V to 57 V )DC DC

Input voltage out of range protectionWide temperature range: –10 °C to 85 °CPD69108F version covering 40 °C to 85 °C– Over-temperature protectionLow power dissipation (0.36 Ω sense resistor and 0.3 Ω MOSFET R (ON)DS

Includes reset command pinFour times direct address configuration pinsContinuous port monitoring and system dataConfigurable load current settingConfigurable AT/AF modesConfigurable standard and legacy detection modePower soft start mechanismOn-chip thermal protectionVoltage monitoring/protectionBuilt in 3.3 V and 5 V regulatorsDC DC

Internal power on resetRoHS compliant



RoHS compliantMSL3Emergency power management supporting four configurable power bank I/OsCan be cascaded to up to 12 PoE devices (96 ports)

2.2 Typical ApplicationThis typical application illustrates a simple PoE system solution for eight Ethernet ports, switch, or hub.

The positive (POS) and negative (NEG) signals should be connected to the switch RJ45 jack.

Figure 1 • Typical Application

Note: Fuses per port are not required for use in circuits with total power level of up to 3 kW. The PD69108/F is designed to fulfill limited power source (LPS) requirements per the latest editions of IEC60950-1 and EN60950-1.

For more information on detailed schematics of application and layout recommendations, contact your local Microsemi account representative.



3 Functional DescriptionsThe PD69108/F has two major sections: a digital section that controls and monitors the logical PoE functions (like state machines and timings) and an analog section that performs the front-end analog PoE functionality.

The following illustration shows the internal functional blocks of the PD69108/F device.

Figure 2 • PD69108/F Internal Block Diagram

3.1 Logic Main Control ModuleThe logic main control module block includes the digital timing mechanisms and state machines. This synchronizes and activates the PoE functions according to the following MCU control commands:

Real-time protection (RTP)Start-up macro (DVDT)Load signature detection (RES DET)Classification macro (CLASS)Voltage and current monitoring registers (VMC)ADC interfacingDirect digital signals with analog block

3.1.1 Line Detection GeneratorUpon request from the MCU to the main control module, four different voltage levels are generated by the line detection generator. This ensures robust AF/AT line detection functionality.



3.1.2 Classification GeneratorUpon request from the MCU to the main control module, the state machine applies a regulated class event and mark event voltage to the ports. This is required by the IEEE standard.

3.1.3 Current LimiterThis circuit continuously monitors the current of powered ports and limits the current to a specific value, according to pre-defined limits as set by AF/AT and current_set pins. In cases where the current exceeds this specific level, the system starts to measure the elapsed time. If this time period is greater than a preset threshold, the port is disconnected.

3.1.4 Main MOSFETThis is the main power switching FET, used to control PoE current into the load.

3.1.5 Analog-to-Digital Converter (ADC)A 10-bit analog-to-digital converter, used to convert analog signals into digital registers for the logic control module.

3.1.6 Power on Reset (POR)This circuit monitors the internal 3.3 V voltage DC levels. If this voltage drops below specific thresholds, a reset signal is generated and the PD69108/F is reset.

3.1.7 Voltage RegulatorThe voltage regulator generates 3.3 V and 5 V for the internal circuitry. These voltages are derived DC DC

from the V supply. To use the internal voltage regulator connect: MAIN

VAUX5 to DRV_VAUX5VAUX3P3 to VAUX3P3_INTREG_EN_N to AGND

There are two options to reduce the PD69108/F power dissipation by regulating the voltage outside the chip:

Use an external NPN transistor to regulate the 5 V . In this setup, the configuration of the DC

regulator's pins should be:

DRV_VAUX5 is connected to the NPN BASEVAUX5 is connected to the NPN EMITTER

(Connect the to VMAIN)Collector

VAUX3P3 is connected to VAUX3P3_INTREG_EN_N is connected to AGND

Supply the PD69108/F with an external 3.3 V voltage regulator. In this setup, the configuration of the regulators pins should be:

VAUX5 is connected to DRV_VAUX5VAUX3P3_INT is connected to VAUX5VAUX3P3 is connected to the external 3.3 VREG_EN_N is connected to VAUX3P3

The above two options can be implemented simultaneously.



3.1.8 CLKCLK is an internal 8 MHz clock oscillator.

3.2 Application InformationThe PD69108/F performs IEEE 802.3af and IEEE 802.3at functionality as well as legacy (capacitor) and Cisco PD detection, in addition to protections such as short circuit and dV/dT protection upon startup.

3.2.1 Line DetectionThe line detection feature detects a valid AF or AT load, as specified in the AF/AT standard. The resistor value should range from 19K Ω to 26.5K Ω. Line detection is based on four different voltage levels generated over the PD (the load), as shown in the following illustration.

Figure 3 • Typical PoE Voltage Timing Diagram

3.2.2 Legacy (Capacitor) DetectionIn cases where legacy is set, the PD69108/F's detection mechanism is configured to detect and power-up legacy PDs, as well as AF/AT-compliant. This mechanism also detects and powers up Cisco legacy PDs.

3.2.3 ClassificationThe classification process takes place right after the resistor detection, when the resistor detection has completed successfully. The main goal of the classification process is to detect the PD class, as specified in the IEEE 802.3AF and AT standards. In AF mode, the classification mechanism is based on a single voltage level (single finger). In AT mode, the classification mechanism is based on two voltage levels (dual finger), as defined in IEEE 802.3at-2009.

3.2.4 Port Start UpUpon a successful detection and classification process, power is applied to the load through a controlled start-up mechanism. During this period, current is limited to 425 mA for a typical duration of 65 mS, which enables the PD load to charge and to enter a steady state power condition.



3.2.5 Over-Load Detection and Port Shut DownAfter power up, the PD69108/F automatically initializes its internal protection mechanisms to monitor and disconnect power from the load in cases where extreme conditions (such as over-current or short port terminal scenarios) occur, as specified in the IEEE 802.3AF/AT standard.

3.2.6 Disconnect DetectionThe PD69108/F supports the DC disconnect function as per the IEEE 802.3AF/AT standard. This mechanism continuously monitors the load current and disconnects power in cases where the load current is below 7.5 mA (typical) for more than 322 mS.

3.2.7 Over-Temperature ProtectionThe PD69108/F has internal temperature sensors that continuously monitor the main MOSFET junction temperature and disconnect load power when the junction temperature exceeds 200 °C. This mechanism protects the device from extreme events such as high ambient temperature or other thermo-mechanical failures that may damage the PD69108/F.

3.2.8 V MAIN Out-of-Range ProtectionThe PD69108/F automatically disconnects port power when V exceeds 60 V . This is an extremely MAIN DC

valuable feature that protects the load if the main power source is faulty or damaged. The following image shows the SPI detailed timing information.

Figure 4 • SPI Detailed Timing Information



The following table describes the SPI timing details.

Table 1 • SPI Timing Details

Name Min Delay Max Delay Description

D1 714 ns SPI clock period

D2 45 ns 55 ns SPI duty cycle

D3 340 ns SPI_CS setup to SPI clock Positive Edge (delay after SPI_CS active signal)

D4 340 ns SPI_CS hold to SPI clock Positive Edge (delay before SPI_CS inactive signal)

D5 2 SPI clock cycles Delay between last SCK in eSPI1 frame and first SCK at adjacent eSPI1 frame.

D6 1 SPI clock cycles Between byte 0 (IC addr) and byte 1(addr).

D7 1 SPI clock cycles Between byte 1 (addr) and byte 2(data).

D8 1 SPI clock cycles Between byte 2 (MS data byte) and byte 3(LS data byte).

D9 340 ns MOSI setup time

D10 210 ns MOSI hold time

D11 140 ns MISO tri-state to valid data from clock positive edge.

D12 300 ns MISO valid data to tri-state from SPI_CS positive edge.

D13 1 SPI clock cycles SPI_CS width (Delay eSPI1 frame to adjacent eSPI1 frame).

D14 60 ns Filtered Glitch Width

D15 D3 + 15.5 SPI clock cycles

D3 + 23.75 SPI clock cycles

MISO tri-state from SPI_CS negative edge to valid data.



4 Electrical SpecificationsThe following specifications apply to the operating ambient temperature.

Table 2 • PD69108/F Power Supply

Parameter Symbol Test Conditions/Comment

Min. Typ. Max. Unit

Input voltage VMAIN Supports full IEEE 802.3 functionality

44 55 57 V

Power supply current at operating mode

V = 55 VMAIN DC 20 mA

5 V output voltage VAUX5 4.5 5 5.5 VDC

3.3 V output voltage VAUX3P3 2.97 3.3 3.63 VDC

3.3 V output current Without external NPN 5 mA

With external NPN transistor on VAUX5

30 mA

3.3 V input voltage VAUX3P3 REG_EN_N pin = 3.3 V

(internal reg. is disabled)VAUX3P3_INT = 5 V

3 3.3 3.6 VDC

Table 3 • Digital I/O

Parameter Symbol Test Conditions/Comment

Min. Typ. Max. Unit

Input logic, high threshold VIH 2.2 V

Input logic, low threshold VIL 0.8 V

Input hysteresis voltage 0.4 0.6 0.8 V

Input high current IIH –10 10 µA

Input low current IIL –10 10 µA

Output high voltage VOH For I = – 1 mAOH 2.4 V

Output low voltage VOL I = 1 mAOH 0.4 V

Table 4 • PoE Load Currents

Parameter Symbol Test Conditions/Comment Min. Typ. Max. Unit

AF, limit mode AF_LIM 400 425 450 mA

AT limit AT_LIM 775 850 925 mA

AT limit dynamic range

Configurable by communication

R = 0.36 Ω 1%SENSE

connected at Port_Sense pin

540 1200 mA



Table 5 • Main Power Switching FET

Parameter Symbol Typ. Unit

On resistance RDS(ON) 0.3 Ω

Internal thermal protection threshold 200 °C

4.1 Dynamic CharacteristicsThe PD69108/F utilizes three current level thresholds (I , I , I ) and three timers (T , T , T ).MIN CUT LIM MIN CUT LIM

Loads that consume I current for more than T are labeled as "short circuit state" and shut down.LIM LIM

Loads that dissipate more than I for longer than T are labeled as overloads and are CUT CUT

automatically shut down.If output power is below I for more than T , the PD is labeled as "no load" and is shut down.MIN MIN

Automatic recovery from overload and no load conditions is attempted every T periods (typically, 1 OVLREC

second). Output power is limited to I which is a maximum peak current allowed at the port.LIM,

Table 6 • IEEE 802.3 AF Mode Parameters

Parameter Symbol Conditions Min. Typ. Max. Unit

Automatic recovery from no load shutdown

T value, measured from port shutdown point UDLREC

(can be modified through control port) 1 s

Cutoff timer accuracy

Typical accuracy ofTcut

2 ms

Inrush current IInrsh For t = 50 ms,C = 180 μF (max)load

400 450 mA

Output current operating range

IPORT Continuous operation after startup period 10 350 mA

Output power available operating range

PPORT Continuous operation after startup period, at port output

0.57 15.4 W

Off-mode current IMIN1 Must disconnect for T greater thanTUVL

0 5 mA

IMIN2 May or may not disconnect when T is greater than TUVL

5 7.5 10 mA

PD power maintenance request drop-out time limit

TPMDO Buffer period to handle transitions 300 400 ms

Over-load current detection range

ICUT Time limited to TOVL 350 400 mA

Over-load time limit

TOVL 50 75 ms

Turn-on rise time TRISE From 10% to 90% of Vport

(specified for PD load consisting of 100 μF capacitor in parallel to 200 Ω)

15 µs

Turn-off time TOFF From V to 2.8 Vport DC 500 ms




Time maintain power signature

TMPS DC modulation time for DC disconnect 49 ms

Table 7 • IEEE 802.3 AT Mode Parameters


Automatic recovery from no load shutdown

T value, measured from UDLREC

port shutdown point (can be modified through control port)

1 Sec

Cutoff timer accuracy Typical accuracy of Tcut 2 ms

Inrush current IInrsh For t = 50 ms, C = 180 μF load

(max)400 450 mA

Output current operating range IPORT Continuous operation after startup period

10 600 mA

Output power available operating range PPORT Continuous operation after startup period, at port output

0.57 36 W

Off-mode current IMIN1 Must disconnect when T is greater than TUVL

0 5 mA

IMIN2 May or may not disconnect when T is greater than TUVL

5 7.5 10 mA

PD power maintenance request drop-out time limit

TPMDO Buffer period to handle transitions

300 400 ms

Over-load current detection range ICUT Time limited to TOVL 600 775 mA

Over-load time limit TOVL 50 75 ms

Turn-on rise time TRISE From 10% to 90% of Vport

(specified for PD load consisting of 100 μF capacitor in parallel to 200 Ω).

15 µs

Turn-off time TOFF From V to 2.8 Vport DC 500 ms

Time maintain power signature TMPS DC modulation time for DC disconnect

49 ms



4.2 Absolute Maximum RatingsThe following table shows the absolute maximum ratings for the PD69108.

Exceeding these ratings can cause damage to the device. All voltages are with respect to ground. Currents are marked positive when flowing into a specified terminal and marked negative when flowing out of a specified terminal.

Table 8 • Absolute Maximum Ratings

Parameter Rating

Supply input voltage (V )MAIN –0.3 V to 74 VDC DC

Port_Neg [0..7] pins –0.3 V to 74 VDC DC

Port_Sense [0..7] pins –0.3 V to 3.6 VDC DC

QGND, GND pins –0.3 V to 0.3 VDC DC

All other pins –0.3 V to 3.6 VDC DC

PD69108 Operating ambient temperature range –10 °C to 85 °C

PD69108F Operating ambient temperature range –40 °C to 85 °C

Maximum operating junction temperature 150 °C

Storage temperature range –65 °C to 150 °C

ESD protection at all I/O pins JESD22 Class 1C HBM (±2KV)

4.3 Power Dissipation InformationThe following table shows the power dissipation values of the respective parameters.

Table 9 • Power Dissipation

Parameter Value

Rsense power dissipation 0.36 Ω × IPORT2

Rds_ON power dissipation 0.3 Ω × IPORT2

Pport_AF = 15.4 W PRsense = 28.2 mW

PRds_ON = 23.4 mW

Pport_AT = 30 W

NOTE: Calculated for supply input voltage of 55 V.

PRsense = 107 mW

PRds_ON = 88.5 mW

PD69108 self power dissipation (including internal 3.3 V regulator) 1.1 W

PD69108 8 ports AF application power dissipation 1.1 W + [ 8 × (28.2 mW + 23.4 mW) ] = 1.51 W

PD69108 8 ports AT application power dissipation 1.1 W + [ 8 × (107 mW + 88.5 mW) ] = 2.66 W

PD69108 self power dissipation (including external 3.3 V regulator) 0.5 W

PD69108 AF 8 ports application power dissipation 0.5 W + [ 8 × (28.2 mW + 23.4 mW) ] = 0.91 W

PD69108 8 ports AT application power dissipation 0.5 W + [ 8 × (107 mW + 88.5 mW) ] = 2.06 W



5 Pin DescriptionsThe following illustration shows the pin diagram (top and bottom views) for the PD69108/F device.

Figure 5 • PD69108/F Pinout

PD69108 for –10 °C to 85 °C operating ambient temperature rangePD69108F for –40 °C to 85 °C operating ambient temperature range

The following table shows the pin descriptions for the PD69108/F device.

Table 10 • Pin Descriptions

Number Name Type Description

EPAD Analog ground

Exposed pad; metal plate on the IC bottom side connected to analog ground.A high-quality ground plane (about 500 mil. inch over 500 mil. inch) should be deployed around this pin whenever possible.

1 PG0 Digital input

Power supply monitoring

2 PG1

3 PORT_SENSE0 Analog input

Sense resistor port input(Connected to 0.36 Ω, 1% resistor to QGND with ~12 mΩ trace for measurements accuracy).

4 VPORT_NEG0 Analog I/O Negative port output


Sense resistor port input

(Connected to 0.36 Ω, 1% resistor to QGND with ~12 mΩ trace for measurements accuracy).


7 AGND Power Analog ground.




8 N/C Power Not Connected


Sense resistor port input(Connected to 0.36 Ω, 1% resistor to QGND with ~12 mΩ trace for measurements accuracy)



Sense resistor port input(Connected to 0.36 Ω, 1% resistor to QGND with ~12 mΩ trace for measurements accuracy)

12 VPORT_NEG3 AnalogI/O

Negative port output

13 N/C Analog I/O Test pin (for production use only); keep open (not connected).

14 N/C

15 VMAIN Power Supplies voltage for the internal analog circuitry. A low ESR 1 µF (or higher) bypass capacitor, connected to AGND should be placed as close as possible to this pin through low resistance traces.

16 VAUX5 Power Regulated 5 V output voltage source; it needs to be connected to a filtering DC

capacitor of 4.7 µF or higher.If an external NPN is used to regulate the voltage, connect this pin to the "Emitter" (the "collector" should be connected to V ).MAIN

17 DRV_VAUX5 Power Zapping input for IC production trimming.Should be connected to DVDD.

18 AGND Power Analog ground

19 VAUX3P3_INT Power Connected to VAX3P3 (pin 20) if internal 3.3 V regulator is used.DC

Connect to VAUX5 (pin 16) if external 3.3 V regulator is used.DC

20 RESET_N Power Regulated 3.3 V output voltage source. A 4.7 μF or higher filtering capacitor should be connected between this pin and AGND.When an external 3.3 V regulator is used, connect it to this pin to supply the DC

chip.

21 QGND Power Quiet analog ground.

22 IREF Analog input

Reference resistor pin. Connect a 30.1 kΩ 1% resistor to QGND.

23 TRIM Analog input

Trimming Input for IC production.It should be connected to VAUX3P3.

24 REG_EN_N REG_EN_N Enable/Disable the internal 3.3 V regulator in case an external 3.3 V is DC DC

used to supply the chip.

GND: Internal regulator enabled.

3.3 VDC: Internal regulator disabled

25 Reserved Analog I/O Keep this pin open (un-connected).

26 AGND Connect to analog ground

27 Reserved Keep this pin open (un-connected)


29 N/C Not Connected

30 AGND Power Analog ground








35 PG2 Digital input

Power supply monitoring

36 PG3

37 TST Digital I/O Test pin for production use only.Keep connected to DGND.

38 RESET_N Digital input

Reset input; active low ('0' = reset)An external 10K pull-up resistor should be connected between this pin and DVDD.

39 MOSI Digital input

SPI bus, Master Data out/slave in

40 MISO Digital output

SPI bus, Master Data in/slave out

41 SPI_CS Digital input

SPI bus, Chip Select

42 DVDD Power Digital 3.3 V input. It needs to be connected to filtering capacitor of 1 µF.

43 DGND Digital I/O Digital GND

44 SCK Digital input

SPI bus, serial clock input

45 ADDR3 Digital input

SPI address bit 3 to set chip address.

46 ADDR2 Digital Input






Address Pin Description (ADDR<3:0>)

The following tables shows the address pin description for the PD69108/F device.

Note: 0 = Connect to DGND (digital ground), 1 = connect to DVDD (3.3 V).

Table 11 • Address Pin Description

ADDR3 ADDR2 ADDR1 ADDR0 SPI ADDRESS [HEX]

0 0 0 0 0

0 0 0 1 1

0 0 1 0 2

0 0 1 1 3

0 1 0 0 4

0 1 0 1 5



1.

ADDR3 ADDR2 ADDR1 ADDR0 SPI ADDRESS [HEX]

0 1 1 0 6

0 1 1 1 7

1 0 0 0 8

1 0 0 1 9

1 0 1 0 A

1 0 1 1 B

1 1 0 0 C

1 1 0 1 D

1 1 1 0 E - Broadcast 1

1 1 1 1 F

Note:

This address is used for Broadcast. Do not set any PD69108/Fs in the system to this address.



6 Package SpecificationThis section shows the package drawing, RoHS and solder reflow information, and thermal specifications for the PD69108/F device.

The following illustration shows the QFN package for the PD69108/F device. This package measures 8 mm by 8 mm and is a 48-pin QFN.

Figure 6 • QFN Package

The dimensions do not include protrusions. The protrusions do not exceed 0.155 mm (0.006 in) on any side. The lead dimensions do not include solder coverage.

The following table shows the dimensions for the QFN package.

Table 12 • Package Dimensions

Dimension Millimeters Inches

Min. Max. Min. Max.

A 0.80 1.00 0.031 0.039

A1 0.00 0.05 0 0.002

A3 0.20 REF 0.008 REF

K 0.20 MIN 0.008 MIN

e 0.50 BSC 0.02 BSC

L 0.30 0.50 0.012 0.02

b 0.18 0.30 0.007 0.012

D2 6.35 6.60 0.250 0.260

E2 6.35 6.60 0.250 0.260

D 8.00 BSC 0.315 BSC

E 8.00 BSC 0.315 BSC



6.1 RoHS and Solder Reflow InformationThe PD69108/F device is rated RoHS 6/6. The package is lead(Pb)-free, with a 100% matte tin finish. The package peak temperature for solder reflow (40 seconds maximum exposure) is 260 °C (0 °C–5 °C).

The following table shows the classification reflow profile information.

Table 13 • Classification Reflow Profiles

Profile Feature Pb-Free Assembly

Average ramp-up rate (TS to Tp)max 3 °C/s max

Preheat

Temperature min (TS )min

Temperature max (TS )max

Time (ts to ts )min max

150 °C

200 °C60–180 s

Time maintained

Temperature (T )L

Time (t )L

217 °C60–150 s

Peak classification temperature (T )P 240 - 255 °C

Time within 5 °C of actual peak temperature (tp) 20–40 s

Ramp-down rate 6 °C/s max

Time 25 °C to peak temperature 8 minutes max

Note: All temperatures refer to topside of the package, measured on the package body surface.

Note: Exceeding these ratings can cause damage to the device.

Following is the classification reflow profile diagram.



Figure 7 • Classification Reflow Profile Diagram

6.2 Thermal SpecificationsThe following table shows the thermal specifications for the PD69108/F device.

Table 14 • Thermal Specifications

Parameter Value

Typical thermal resistance: junction to ambient 25 °C/W

Typical thermal resistance: junction to case 4 °C/W

The θ numbers are guidelines for the thermal performance of the device/PC-board system. All JA

specifications assume no ambient airflow.



6.3 Tape and Reel Packaging InformationThe following figure shows the Pin-1 orientation of QFN packages for the PD69108/F device.

Figure 8 • Pin-1 Orientation of QFN Packages Diagram

The following figures represents the tape and reel shipment specifications.

Figure 9 • Tape Shipment Specifications

The following table shows the tape mechanical data:

Table 15 • Tape Mechanical Data

Dimensions (mm)

Ao 8.35 ±0.10

Bo 8.35 ±0.10

Ko 1.40 ±0.10

K1 N/A

Pitch 12.00 ±0.10

Width 16.00 ±0.30



The following image shows the reel shipment specifications for the PD69108/F device.

Figure 10 • Reel Shipment Specifications

The following table lists the reel specification details for the PD69108/F device.

Table 16 • Reel Mechanical Data

Component Dimension (mm) Dimension (in.)

Tape size 16.00 ±0.3 0.630 ±0.012

A max 330 13

B max 1.5 0.059

C 13.0 ±0.20 0.512 ±0.008

D min 20.2 0.795

N min 50 1.968

G 16.4+2.0/–0.0 0.645+0.079/–0.0

T max 29 1.142

Base Quantity 2000 pcs



1. 2.

7 Ordering Information

Table 17 • Ordering Information

Part Number Package Temperature Part Marking

PD69108ILQ Plastic 48 pin QFN 8 mm × 8 mm –10 °C to 85 °C Microsemi LogoPD69108ZZ e3YYWWNNN

PD69108FILQ Plastic 48 pin QFN 8 mm × 8 mm –40 °C to 85 °C Microsemi LogoPD69108FZZ e3YYWWNNN

Note: Available in tape and reel. Append the letters TR to the part number.

ZZ e3: ZZ = Random Character with no meaning, and e3 = 2nd Level Interconnect.YY = Year, WW = Week, NNN = Trace Code.



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Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.

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PD-000307817

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