Navigating Challenges at the Leading Edge of Test Technology

Don’t miss COMPASS 2015, Cascade Microtech’s third annual users’ conference, to network with your peers, share best practices and real-world experiences using Cascade Microtech’s products. COMPASS 2015 offers six track sessions focused on the following subject areas: 1. RF/mmW probing, 2. Thermal, 3. High power, 4. Device characterization, 5. Automation, 6. Reliability test.

At COMPASS 2015, you will learn:

Keynote: The Future of Power Electronics and the Impending Challenges to MetrologyThomas Neyer Fellow, High-Voltage Device and Technology Development, Fairchild SemiconductorPower electronics has successfully established its foothold in most domestic, industrial and automotive applications like power supplies, household machines, air conditioners, power generation and transmission units, all type of electrical motors and automotive drives and pumps. In addition, the power devices have increased their conduction and switching inefficiencies by a multitude by utilizing novel device architectures, novel materials or extreme current densities enabled by ultra-thin wafer technology or narrow mesa trench technology. Testing these devices for function, conformity with datasheet, and reliability stretches the test requirements significantly, particularly on wafer level. High-voltage (> 1 kV), high-current (> 150 A) and extreme switching speeds sometimes present considerable challenges. In this paper the author will present trends for silicon and wide-bandgap power devices, and will walk through some of the issues industry encounters when characterizing and testing these advanced power switches and passives.

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September 15-16*, 2015OMNI Parker House, Boston, MAcompass.cascademicrotech.com* Welcome reception on September 14, 6:00-8:00 PM

• Screen DUTs in less time using post calibrations, real-time evaluations, and suggestive test properties

• Understanding failure fundamentals in the era of nanoelectronics

• Constant voltage vs constant current electromigration for advanced BEOL interconnects

• On-line probe card cleaning methods and its benefits • Measurement challenges for high-voltage C-V

• Device extraction and calibration techniques at cryogenic temperatures

• Automated test cell for accurate calibrations and verifications at 1.1 THz

• New techniques to overcome challenges of on-wafer load pull measurements

• How to maintain high positioning accuracy on 30 x 30 µm pads across temperature

• Innovative characterization metrology for wide-bandgap power devices up to 3 kV

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Featured Session

The Importance of Understanding Reliability in Today’s Unforgiving EnvironmentDr. James Lloyd Senior Research Scientist and Professor, State University of New York, Polytechnic Institute, College of Nanoscale Science and Engineering (CNSE)As the microelectronics industry becomes the nanoelectronics industry, new reliability issues and old ones that, unlike old soldiers, do not fade away, will continue to make life “interesting.” Complexity is rising, dimensions are becoming smaller and new, inherently less reliable materials and processes are being implemented to satisfy the needs of a relentless technology. Reliability testing has become even more important now than ever, and properly designed tests based on a firm fundamental understanding of failure physics are needed. Reliability testing comes in two major flavors. First and foremost is the testing required during process/product development and qualification, and the other is testing to maintain the quality of the manufacturing line. In this talk we will concentrate on the former, but the latter should not be ignored in today’s very complex and unforgiving environment.

General Sessions

Automated Testing of Singulated Die-to-Die Stacks Frank Thiele, Ph.D.Product Marketing Manager, Systems Business Unit, Cascade MicrotechDie-to-Die (D2D) stacking is an efficient way to generate stacks, allowing stacking of dies of various sizes and of different wafer processes with special features on a smaller footprint. The testing of these stacks is on one hand a challenge because they are no longer aligned with perfect pitch as a wafer, but on the other hand one can restrict the stacking and the tests on as pass-tested dies on pass-tested dies, thus significantly improving test throughput and assembly yield. However, the feasibility of automated index stepping and aligning on arrays of “pick-n-placed” bare D2D stacks on substrate carriers has been never tested before. This presentation will illustrate how singulated die stacks testing in matrix structure can be automated with Cascade Microtech’s CM300 probe station and Velox™ probe station control software. Thiele will review types of carriers and test algorithms, and examine experimental results from imec on dicing tape on tape frames, sheets of single-sided thermal-release tape and double-sided thermal-release tape on 300 mm carrier wafers.

Track A: RF/mmW Probing

Verification of On-Wafer Vector Network Analyzer Systems up to 110 GHzRick JamesLead Engineer - New Product Introductions - Vector Network Analyzers, Keysight TechnologiesSystem verification above 50 GHz for on-wafer probe stations incorporating a vector network analyzer (VNA) challenges many developers. A grounded coplanar waveguide (GCPW) thin-film circuit with a wide dynamic range of verification standards has been developed with good performance up to 110 GHz. The main use model is for verification of a new system at a customer site performed up to the customer’s probe tips. Results are compared to factory-grade measurements of the same devices with limits based on an analysis with multiple probes, systems and calibrations. Problems related to VNAs, adaptors, cables, probes or calibrations will be apparent and can be corrected before making customer device measurements.

How to Automate THz Calibrations and Verification Compared to Manual MethodsGavin FisherSenior Application Engineer, Center of Expertise, Cascade MicrotechCalibration accuracy and repeatability have long been crucial for accurate on-wafer device models. Probe placement tolerances are more critical to the calibration as operation frequency increases. Cascade Microtech recently launched a range of on-wafer probes that allow testing up to 1.1 THz. The company considered the additional requirements needed for the test cell to achieve reliable, repeatable results. For instance, 1 μm of misplacement represents approximately 3° phase deviation at 1.1 THz. Given the tolerances involved, it was believed that an automated multiline TRL calibration would deliver the best results. With that in mind, a large area programmable positioner was developed to handle the combination of probe and large test head. This works in conjunction with Wincal XE™ calibration software and a semi-automatic prober running Velox™ software, allowing fully-automatic calibration after initial probe placement. However, not all customers have access to semi-automated stations or programmable positioners, and so the tradeoffs involved were evaluated. The presentation will go through the methods required to setup an automated on-wafer 1.1 THz test cell. Error term variation on consecutive calibrations and variation of validation structure measurements will be presented and compared with the same metric for both the fully manual and also manual stage/motorized positioning cases. A comparison will be shown of the on-wafer repeatability achieved with that achieved via successive waveguide calibrations.

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Measurement Uncertainty for THz On-Wafer Probing Scott BarkerCEO, Dominion MicroProbesDMPI’s technology has exhibited excellent RF measurement performance probing 140 GHz to 1.1 THz, with typical insertion loss below 2 dB at 200 GHz and rising to 5-7 dB for 500 GHz to 1.1 THz. However, the challenges of measurement uncertainty increase rapidly above 500 GHz. The contributing factors to this uncertainty have been investigated through the use of an on-wafer probe with integrated strain sensors. The uncertainty for 500-750 GHz measurements, broken down between source uncertainty, contact force variation, and stage accuracy, will be presented at the conference.

Track B: Thermal

Influence of Calibration Techniques on Device Extraction at Cryogenic TemperaturesAhmet Hakan CoskunResearch Assistant /Ph.D. Student, University of Massachusetts Amherst(Co-Author: Joseph Bardin, Professor, University of Massachusetts Amherst)This presentation will compare small-signal model extraction results for state-of-the-art semiconductor devices (90 nm SiGe HBT and 32 nm CMOS FET) obtained with different calibration techniques such as LRRM, SOLT, LRM+ and TRL. Measurements and calibration will be carried out using Cascade Microtech’s |Z| Probes® with the appropriate calibration standard. In order to understand temperature dependence, the comparison will also be carried out at room temperature. To minimize the landing errors between different calibration techniques, all measurements will be carried out simultaneously; that is different calibrations will be applied on multiple channels of VNA. Measurements will be performed in the range of 0.01 – 67 GHz using a Keysight 5247A VNA and a cryogenic probe station that can cool down to 6 K.

Methodologies for Accurate RF Calibration and Testing at TemperatureDaniel BockSenior Application Engineer, Center of Expertise, Cascade Microtech(Author: Gavin Fisher, Senior Application Engineer, Center of Expertise, Cascade Microtech)Full temperature-dependent broadband device models are frequently essential for device utilization in today’s multi-function designs, which encompass ever-increasing sophistication. In addition, for many, device reliability and operating temperature range are key considerations. Of principle importance to the S-parameter measurement from which the models are extracted is the calibration accuracy and long-term stability. In this presentation, we will evaluate the temperature dependencies and causes for calibration drift in modern on-wafer probing systems and probes which pose significant challenges to accurate device modeling. Practical methods to minimize and evaluate these variations will be discussed in conjunction with the WinCal XE™ calibration and measurement software. The changes seen in a selection of extracted model parameters due to temperature related calibration error will be also discussed.

Automating Probe Card Exchange and Docking for RADAR Products Running at 40 GHz and BeyondJory TwitchellHardware Engineer, Probe, Freescale SemiconductorFreescale plans to take the current probe card from Cascade Microtech, which requires 3.5 mm Gore cabling and waveguides attached manually to a probe card capable of a fully-automatic probe card exchange using the TEL SACC docking mechanism built into the prober. In order to accomplish this task, Freescale will be soliciting the help of InTest Silicon Valley to develop the stiffener, pogo tower which will be mounted to the prober, and guide pins to ensure the blind mate connectors align. InTest will also develop the Probe Interface Board (PIB) which will replace the current stack configuration with blind mate connections. Freescale will also include Cascade Microtech to develop a probe card from the current configuration which fits a M101 prober interface to a probe card which is 11” in diameter. This probe card will include the blind mate connectors which will handle greater than 40 GHz frequency. It will also be built with Cascade Microtech Pyramid® technology for the probe tips.

Track C: Power

New Techniques for Characterizing Switching and Driving Loss in Wide-Bandgap Power DevicesAlan WadsworthMarket Development Manager, Keysight Technologies Wide-bandgap power semiconductor devices have many advantages over conventional silicon power devices, including the ability to operate at higher temperatures and faster switching frequencies. Wide-bandgap devices also typically have lower on-resistances that result in decreased conduction power loss. However, because they operate at higher switching frequencies, switching and driving loss typically dominate overall power loss during circuit operation. To accurately predict this loss, wide-bandgap devices need to have their capacitances (Ciss, Coss and Crss) and gate charge (Qg) characterized at thousands of volts of DC bias. Unfortunately, until now, there have not been any commercially available solutions capable of doing this. Keysight Technologies will present novel techniques and methods that permit the characterization of wide-bandgap power device capacitance, gate charge and gate resistance at drain to source voltages of up to 3 kV. The practical issues of making these measurements on both packaged and on-wafer devices will be discussed. Wadsworth will also show software that can combine these measurements with device IV characteristics and calculate switching power loss versus frequency.

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Using On-Wafer High-Current Probing for the Design and Characterization of Next-Generation IGBT Current SensorsMehrdad BaghaieManager, Power Solution Center, Fairchild SemiconductorNext-generation IGBTs are capable of carrying currents up to 200 A per die. These high currents are both challenging to monitor within the device and challenging to probe using lab test setups. Fairchild uses Cascade Microtech’s newly-designed high-current probes in conjunction with the Tesla system to facilitate measurements up to 330 A at wafer level. This setup is used to characterize, for the first time, Fairchild’s next-generation field stop trench IGBTs at above-nominal current operation. These conditions are used to study the behavior of a series of newly-designed on-chip current sensors to find the optimum design for the upcoming on-chip IGBT current sensors. The presentation will include both the results of initial beta testing of the Cascade Microtech’s high-current probes on Fairchild’s 200 A IGBTs, as well as the results of current sensor testing under high-current conditions.

Simplifying Instrumentation and Prober Configuration for On-Wafer Power Device CharacterizationLee StaufferSenior Staff Technologist, Semiconductor Measurements Group, Keithley InstrumentsOn-wafer characterization of high-power semiconductor devices involves several different types of measurements: on-state (high-current I-V), off-state (high-voltage I-V) and capacitance-voltage (C-V) at high bias voltages. Unfortunately, each of these measurements involves complex reconfiguration including different instrumentation, cabling, electrical connections, and probes. Operator safety cannot be compromised, and the goal of course is valid measurement data. Stauffer will discuss ways to simplify the test setup between high-voltage I-V, high-current I-V and high-voltage C-V power device measurements. Doing so will save time, increase measurement confidence, deliver optimal results, keep the operator safe, and reduce the risk of equipment damage. Specific attention will be paid to typical measurement errors and high-voltage C-V, where optimal measurements can be especially challenging.

Track D: Device Characterization

Increased Throughput Means More DataDarnell LaneElectronics Engineer, Northrop GrummanA surge of information in the “I want it now” generation has begun to bridge the gap between engineering and high-volume production wafer testing. Having the ability to acquire arduous measurements from your DUT is becoming less of an achievement and more of a basic requirement due to highly advanced test instrumentation. Tools such as Keysight’s PNA-X and NI HSDIO hardware give test engineers the ability to acquire data in less than a second. However, this advantage has evolved testing from “how to make the measurement” to “what to do with the measurement”. This challenge poses unique complications, such as determining when to perform yield screening or DVT. Performing real-time evaluations can reduce overall test time, support data analysis, and reduce data quantities. However, data handling presents a significant amount of challenges due to sharing data across platforms, and presenting visual aids from massive amounts of data sets. Lane is often faced with these challenges, and will share a few ideas that have helped with processing information. Various strategies such as post calibrations, real-time evaluations, and suggestive test properties have assisted in screening DUTs in a fraction of the time.

Overcoming On-Wafer Measurement Challenges with Advanced Load-Pull TechniquesGary SimpsonCTO, Maury MicrowaveThe goal of load pull is to measure the response of a transistor as a function of load impedance and is typically achieved using automated slide-screw impedance tuners. In a passive mechanical tuner system, impedances are synthesized by interrupting the electric field of an airline using a metallic probe. The probe is inserted into the air line at a varying depth to control the magnitude of reflection, and is moved towards or away from the DUT to alter the electrical length and hence the phase of reflection. Several challenges exist when performing on-wafer load pull: mechanical vibrations may exist when moving the probe; insertion losses between the tuner and DUT causes a reduction in Smith Chart tuning coverage; harmonic load pull requires multiple tuners or a single large multiple-probe tuner. Active load pull is an alternate form of impedance control, which replaces a passive tuner with an active tuning chain consisting of a magnitude- and phase-controllable signal source and amplifier. Active load pull has no mechanical moving parts and can be used to overcome all system losses, thereby solving the aforementioned problems. This presentation will discuss the challenges faced with traditional on-wafer load pull measurements, offer multiple advanced solutions, and review measured data.

Excellent Electrical Data Comparison Between Two Probers - CM300 vs S300Osbert ChanProgram Manager, Applied MaterialsThis case study evaluates Cascade Microtech’s S300 semi-automated probe station and CM300 fully-automated probe station with capacitance-current (CV) curves and leakage current using the same Keysight E4980A precision LCR meter and 4156C precision semiconductor parameter analyzer. The TiN high-K film for N7 node FinFETs (field effect transistor) was measured CV curves at both probers on the same day to eliminate humidity (environment) issues. The study found that contact resistance between probe

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tips and wafer is one of the main reasons to cause CV differences between the S300 and the CM300. The co-axial cables and adaptors connecting from LCR meter to prober were checked to eliminate parasitic resistance and capacitance. After verifying all testing components, the CV curves between these two systems have excellent match. The CMAX variance between two systems is only 0.11%. The reproducibility in CM300 has 99.94%. Repeating the CV measurement on the same device shows that these two probers are showing excellent correlation.

Track E: Automation

Why is Device Test and Cleaning Such a Challenge? Fundamentals, Techniques and New IdeasJerry BrozVice President of Applications, International Test SolutionsRequirements driving device test data integrity include high-frequency performance, device configurations, good/bad die identification, traditional vs. advanced and MEMS probe technologies, temperature effects and other factors that can affect data quality. Fundamentally, all device testing is a “dirty business” and the probe technologies need some level of consistent on-line cleaning to maintain stable performance. Advanced probe technologies do have non-oxidizing metallurgies and contactor shapes designed to reduce the need for on-line cleaning; however, with repeated touchdowns, debris, adherent materials, and device metals accumulate on the probe contact surface. Investigating the performance of probe technologies, contactor shape and composition and cleaning requirements require extensive and often empirical testing. Understanding contact mechanics, i.e., probe to pad, probe to bump and probe to cleaning material, are important for stable results, high throughput and consistent up-time. In order to define when the probe contact surface reaches a critically “dirty” level point, a systematic methodology will be proposed. Various probe related challenges and on-line cleaning solutions for reduced probe card repairs, maintaining high yield and throughput, and reducing damage will then be discussed.

Customized Probe Card for On-Wafer Testing of AlGaN/GaN Power TransistorsNicolò RonchiResearcher, Power and Mixed Signal Technologies Group (PMST), imecAlGaN/GaN power transistors are discrete power devices primarily designed to be used in high-frequency switching converters. High switching speed, high power and the electrical behavior of the device materials call for specific characterization techniques in the power domain, such as pulsed high-current DC measurements and fast double pulsed IV to characterize dynamic effects. Access to on-wafer measurements for a rapid evaluation of devices after processing is a must in a production environment, either for process development or for production Quality Assurance (QA). Use of microsecond high-current pulses poses difficult signal integrity problems, particularly for on-wafer measurements using semi-automated probers. imec’s solution employs a CELADON VC20 VersaCore with multiple needles and a 45E interface in combination with a Keysight B1505A for DC characterization and an Auriga AU4850 for pulsed IV. Careful design of probe card and ground tracing is required. In this session, an ID-VDS curve measured in pulsed condition will be shown. Maximum current displayed is over 17 A for a 36 mm device. Typical current waveform shows a smooth curve is smooth without appreciable parasitic oscillations. Ronchi will also show the pulsed ID-VDS for different quiescent drain bias (VDS_q). The increase of the RDS(on) is clearly visible from the slope of the curves. Also in this case, the waveforms are very smooth for all the VDS_q applied. These results demonstrate the validity of the chosen approach. Ronchi will discuss a detailed approach, and compare to other common solutions which cannot give the same signal quality in the pulsed power domain.

Motorized DC Positioner Control Automation Over TemperatureKoby DuckworthSr. Product Support Specialist, Center of Expertise, Cascade MicrotechLeading-edge device characterization relies on the precise, repeatable measurement across temperature of test structures or devices that are interfaced through ever-shrinking aluminum or copper test pads. Current state-of-the-art test pad sizes are 30 μm x 30 μm with near-term roadmaps to 20 μm x 20 μm as soon as test process capability allows. The ability to land on and stay in optimal contact with these small pads at multiple temperatures requires the dynamic management of error components from several test system elements. Often test teams are faced with high-mix, low-volume device layout challenges which are best served by using discrete probes mounted on positioners which allows users to avoid the cost of expensive fixed layout probe cards that may become obsolete prior to wearout. Furthermore, time-to-market pressures drive engineers to test early device prototypes as soon as possible, which further supports the need for layout flexibility offered by using discrete probes on positioners instead of ordering new probe cards with long lead times. However, the challenge with using discrete probes on positioners is managing the precise probe to pad registration as well as contact pressure of each probe across temperature and staying within the borders of a 30 μm x 30 μm test pad. For applications with larger test pads, traditional compensation methods consisted mostly of thermal variation control (soak management) and chuck position correction. However for small pad applications, chuck position correction alone is insufficient in compensating for individual tip position drift in a dynamic thermal environment. Additionally, for optimal tip position accuracy with the least amount of correction iteration, direct measurement of the actual tip position is highly desired over encoder position feedback located on the positioner motors which may not comprehend thermal effects on the positioner arm. This presentation will explore an alternative solution for automatically maintaining probe to pad registration of four DC probes on motorized positioners across temperature through the use of Cascade Microtech’s automation utility which incorporates iterative closed-loop control of optical probe models for actively managing discrete probe positional accuracy throughout the test process.

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Track F: Reliability Test

Constant Voltage Electromigration and its Impact on Distributional ShapesEric WilcoxApplications Specialist, Center of Expertise, Cascade Microtech(Author: Kristof Croes, Group Leader, Reliability, Electrical Test and Modeling, imec)Electromigration is a key reliability concern for back-end-of-line interconnects. Since electromigration is a current-driven process, today’s mainstream test methodologies consist of applying a constant current through the test line at elevated temperatures while the voltage-drop across the line is monitored over time to electrically detect void formation. At COMPASS 2014 and at IRPS 2015, the world’s largest reliability symposium, we proposed constant voltage electromigration as an alternative to constant current electromigration for advanced BEOL interconnects. We proved that constant voltage electromigration is the proper test methodology for highly-scaled lines that have extremely-scaled, non-conductive barriers because the current cannot flow through the barriers anymore when large voids occur, which leads to unrealistically high voltages over the voids. In this session, we will quantify another reported benefit of constant voltage electromigration using N10-compatible test samples: the reduction in distributional shape. We will compare these shapes between traditional, constant current electromigration tests and constant voltage electromigration tests.

Wafer-Level Electromigration; A Quick-Turn Complementary Method Which Correlates to Package-Level EM Reliability TestTimothy McMullenDirector of Product Marketing, Reliability Test Products, Cascade MicrotechAccelerating development cycles and increasing uncertainty in new process nodes call for quick reliability test results. In response, wafer-level reliability (WLR) testing has risen in prominence for many intrinsic quality test disciplines because it eliminates the time-consuming step of dicing and packaging test structures. However, intrinsic Electromigration (EM) evaluation has remained almost exclusively within the package-level test domain because it presents unique probing challenges for WLR implementation such as very high temperature (350°C), copper oxidation risk at elevated temperature, a non-static thermal profile, and test times which can stretch into several weeks. A full system solution for WLR EM test is described which overcomes those difficult execution barriers and demonstrates good correlation to traditional package level EM results, while delivering the faster time-to-data results demanded by today’s semiconductor industry.

Self-Heating Effect on Hot Carrier Degradation Characteristics in LNDMOSJifa HaoMember of Technical Staff, Fairchild SemiconductorLDMOS (Laterally Diffused MOSFETs) have been widely used in smart power applications with high currents and high voltages. For these devices, one of the main reliability issues is hot carrier degradation (HCD). However, seldom attentions are paid on self-heating effect on LDMOS HCD. Jifa will first review HCD mechanism in LNDMOS, and report that self-heating, caused by HC stress in packaged thick gate-oxide n-channel high-voltage LDMOS (HV LNDMOS) devices, significantly affects the HC degradation characteristics. Although a thick gate-oxide LNDMOS experiences less self-heating due to lower drive current compared to thin gate-oxide LNDMOS, the self-heating still significantly affects the HC degradation characteristics. The change in delay time between the removal of the HC stress after each stress cycle and the parameter measurement results in a significant difference in HC Idlin degradation. For a longer delay time, lower Idlin degradation is observed. We observed that the HC degradation difference is mainly due to self-heating effect. The Idlin degradation from self-heating effect seems to be more than from HC effect in packaged HV LNDMOS. The degradation between package level and wafer level has been compared. Based on the data, some methods are suggested to reduce the self-heating effect and to separate the local HC injection effect and self-heating effect on the device parameter degradation.

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Program At A Glance

COMPASS 2015 SPONSORS

Tuesday, September 15, 2015

17:30 – 19:0018:00 – 20:00

Monday, September 14, 2015RegistrationWelcome Reception

Rooftop Terrace,15F

08:00 – 08:3008:30 – 08:40

Registration and Networking BreakfastDay 1 Agenda Preview

08:40 – 08:55 Welcome: Michael Burger, President and CEO08:55 – 09:55 Keynote: The Future of Power Electronics and the Impending Challenges to Metrology (Thomas Neyer, Fairchild Semiconductor) 09:55 – 10:10 Networking Break and Sponsor Expo

King Room, 2F

Wednesday, September 16, 201508:00 – 08:30 Networking Breakfast King Room, 2F

09:45 – 10:05 Networking Break and Sponsor Expo Foyer, 2F

12:00 – 13:00 Networking Lunch and Sponsor Expo Foyer, 2F

14:15 – 15:00 Navigating Future Challenges – A Strategic Perspective (Steve Harris, VP Integrated Measurement Systems and Mark Stager, VP Probes Business Unit, Cascade Microtech) Press Room, 2F15:00 – 17:00 Happy Hour Networking Reception at Ruth’s Chris Steakhouse Boston City Hall (Across from Omni Parker)

13:00 – 14:15Cascade Microtech InteractiveRF/mmW Calibration Techniques; Velox Probe Station Control Software Usability Lab; Automated Wafer-Level Reliability Test; Production RF Calibration TechniquesMeasurement Automation with Velox and Keysight’s WaferPro Express

Alcott A Room, 2F

08:30 – 08:45 Day 2 Agenda Preview08:45 – 09:45 Featured Presentation: The Importance of Understanding Reliability in Today’s Unforgiving Environment (Dr. James Lloyd, SUNY/CNSE)

Press Room, 2F

Press Room, 2FAlcott B Room, 2F

Press Room, 2F

Foyer, 2F

14:55 – 15:15 Networking Break and Sponsor Expo Foyer, 2F

17:00 – 18:30 Historic Boston Downtown Tour and Scavenger Hunt Boston Downtown18:30 – 20:30 Happy Hour and Dinner at Chart House Boston Long Wharf

15:15 – 16:00 Automated Testing of Singulated Die-to-Die Stacks (Dr. Frank Thiele, Cascade Microtech) Press Room, 2F16:00 – 16:10 Day 1 Closing

Press Room, 2FAlcott B Room, 2F

Press Room, 2FAlcott B Room, 2F

Track A: RF/mmW Probing (Press Room, 2F) Track B: Thermal (Alcott B Room, 2F)Influence of Calibration Techniques on Device Extraction at Cryogenic Temperatures Ahmet Hakan Coskun, University of Massachusetts Amherst

How to Automate THz Calibration and Verification Compared to Manual MethodsGavin Fisher, Cascade Microtech

Methodologies for Accurate RF Calibration and Testing Over TemperatureDaniel Bock, Cascade Microtech

Track C: Power (Press Room, 2F) Track D: Device Characterization (Alcott B Room, 2F)

Track E: Automation (Press Room, 2F) Track F: Reliability Test (Alcott B Room, 2F)

Verification of On-Wafer Vector Network Analyzer Systems up to 110 GHzRick James, Keysight Technologies

10:10 – 10:45

Increased Throughput Means More DataDarnell Lane, Northrop GrummanOvercoming On-Wafer Measurement Challenges with Advanced Load-PullTechniques Gary Simpson, Maury MicrowaveExcellent Electrical Data Comparison Between Two Probers: CM300 vs S300Osbert Chan, Applied Materials

New Techniques for Characterizing Switching and Driving Loss in Wide-BandgapPower Devices Alan Wadsworth, Keysight Technologies

13:00 – 13:35

Constant Voltage Electromigration and its Impact on Distributional ShapesEric Wilcox, Cascade Microtech on behalf of Kristof Croes, imec

Why is Device Test and Cleaning Such a Challenge? Fundamentals, Techniques,and New Ideas Jerry Broz, International Test Solutions

10:05 – 10:40

Self-Heating Effect on Hot Carrier Degradation Characteristics in LDMOSJifa Hao, Fairchild Semiconductor

Motorized DC Positioner Control Automation Over TemperatureKoby Duckworth, Cascade Microtech

11:25 – 12:00

Wafer-Level Electromigration; A Quick-Turn Complementary Method WhichCorrelates to Package-Level EM Reliability Test Timothy McMullen, Cascade Microtech

Customized Probe Card for On-Wafer Testing of AIGaN/GaN Power TransistorsNicolò Ronchi, imec10:45 – 11:20

Using On-Wafer High-Current Probing for the Design and Characterization ofNext-Generation IGBT Current Sensors Mehrdad Baghaie, Fairchild Semiconductor

13:40 – 14:15

Simplifying Instrumentation and Prober Configuration for On-Wafer Power DeviceCharacterization Lee Stauffer, Keithley Instruments

14:20 – 14:55

10:50 – 11:25

Measurement Uncertainty for THz On-Wafer ProbingScott Baker, Dominion MicroProbes

Automating Probe Card Exchange and Docking for RADAR Products Runningat 40 GHz and Beyond Jory Twitchell, Freescale Semiconductor

11:30 – 12:05

“Birds of a Feather” Roundtable Lunch1. Production RF, 2. Measurement Automation, 3. PTPA, 4. RF Calibration, 5. Reliability Test, 6. Power12:05 – 13:00 King Room, 2F