Sepic 1

ICSET 2008

I. INTRODUCTION

AbstractA novel single switch two diodes wide conversion ratio step down/up converter is presented. The proposed converter is derived from the conventional Single Ended Primary Inductor Converter (SEPIC) topology and it can operate into a capacitor-diode voltage multiplier, which offers simple structure, reduced electromagnetic interference (EMI), and reduced semiconductors voltage stress. The main advantages of the proposed converter are the continuous output current, higher voltage conversion ratio, and near zero input/output current ripples compared with the conventional SEPIC converter. The principle of operation and comparison with the conventional SEPIC converter are presented. The performance of the proposed converter is verified through computer-aided simulations and experimental results.

WITCHED mode power supplies (SMPS) are used widely in consumer electronic appliances. They are

designed with the intent to pass the electromagnetic compatibility (EMC) certification test which is mandatory and vital for some applications like telecommunication, automotive, and medical equipments. Designing high performance power converter with low cost, small size, and high efficiency make the electromagnetic interference (EMI) design a more challenging task. The designing task becomes even more difficult for applications that demand wide range of voltage gain with reduced input and output current ripple. For these applications, the Cuk converter seems to be a potential candidate within the basic converter topologies [1]. The flyback converter requires and additional input/output L-C filter to reduce the switching ripple and noise level at both terminals. Moreover, it was shown in [1], that the Cuk converter is more efficient than the flyback converter with the input filter. The boost converter with an output filter results in a more bulky converter when compared to the Cuk converter. This is because the input and output inductor cannot be coupled into a single magnetic core as in the Cuk converter [2].

The SEPIC converter [3] has similar advantages as the Cuk converter; both have the same DC voltage gain, low input noise, and overload protection feature. In addition,both converters have adequate level of intrinsic immunity

Manuscript received April 29, 2008.E. H. Ismail is with Electrical Engineering Department, College of

Technological Studies, P.O. Box: 35007, AL-Shaab, Kuwait, 36051 (phone: +96599788776; fax: +9655381284; e-mail: [email protected]).

A. A. Fardoun is with Electrical Engineering Department, University of United Arab Emirates, P.O. Box: 17555, Al-Ain, UAE (e-mail: [email protected]).

to electromagnetic interference (EMI) when a coupled inductor techniques is implemented to achieve near zero-ripple input current [4]-[5]. Moreover, unlike Cuk converter, SEPIC converter does not suffer from an output polarity inversion but it requires an additional output L-Cfilter to maintain continuous output current.

The main disadvantage of the single switch topologies presented above is the need for the high voltage blocking capability of the active power switch; hence, they require a MOSFET with a higher RDS-ON leading to higher cost and conduction losses. Moreover, in conventional pulse-width modulation (PWM) dc-dc converter topologies operating in continuous conduction mode (CCM), maximum attainable dc conversion ratios are limited in practical applications bythe maximum duty cycle (D) of the converter. On the other hand, extreme duty cycles impose inefficiently small off-times or low switching frequencies. Small off-times cause severe diode reverse-recovery current, which will increase the EMI level. Lower switching frequency causes higher ripple current and increase magnetic components [6]. Thus, the net results are increased size and degrading the overall converter efficiency.

In order to overcome these problems, a modified boost topology is proposed in [7] with some significant features of reduced switch voltage stress, wide dc conversion ratio, and continuous output current as compared with the conventional boost converter. Detail analysis of this converter is presented in [8].

This paper presents a new high performance single-switch DC-DC converter. The proposed converter in Fig.1 is based on the SEPIC configuration, with the output capacitor replaced by two identical capacitors connected through two diodes in a way that they can be charged in parallel and then discharged in series through the load. The operation of the new converter is similar to the conventional SEPIC, but it posses several substantial performance advantages, most notably are: 1) Higher step up/down voltage conversion ratios. 2) Lower voltage stress on the semiconductor devices, thus alleviating the conduction losses. 3) Continuous input and output current. 4) Reduced ripple current in the output capacitor reduces the output ripple voltage and allows the use of smaller and less expensive output capacitors.

In the modified converter, the absence of both a transformer and an extreme duty cycle permits the proposed converter to operate at high switching frequencies. Hence, the overall advantages will be: higher efficiency, reduced

SEPIC Converter with Continuous Output Current and Intrinsic Voltage Doubler Characteristic

Esam H. Ismail, Senior Member, IEEE and Abbas A. Fardoun, Senior Member, IEEE

S

431978-1-4244-1888-6/08/$25.00 c 2008 IEEE

Authorized licensed use limited to: CZECH TECHNICAL UNIVERSITY. Downloaded on June 5, 2009 at 02:39 from IEEE Xplore. Restrictions apply.

size and weight, simpler structure and control.The modified converter structure utilizes three inductors

which is often described as a disadvantage. However, the three inductors can be coupled on the same core [4], allowing considerable size and cost reduction and additionally, the 'zero-ripple-current' condition at both the input and output terminal can be reached without compromising performance. This condition is very desirable, because the generated EMI noise is minimized, dramatically reducing input and output filtering requirements. Moreover, the 'zero-ripple-current' at both the input and output terminal can be also obtained in discontinuous conduction mode (DCM). This is a very desirable feature for power factor correction (PFC) applications since it will dramatically reduce the high switching ripple current.

II. BASIC OPERATION OF THE PROPOSED CONVERTERFig. 1 shows the proposed SEPIC converter with

continuous output current and voltage-doubler characteristics. As can be seen from Fig. 1, the proposed circuit resembles the conventional SEPIC converter except that its output port has been modified to include two identical capacitors C connected through two diodes followed by L3-Co filter. The two capacitors C appear in a parallel configuration during the switch off-time, hence they are charged equally by the energy stored in the filter inductors L1, L2, and L3. During the switch on-time, the two capacitors C are discharged in series through the load and the filter inductor L2. Thus, for the same duty-cycle, the proposed converter is capable of supplying an output voltage level twice as much than the conventional SEPIC converter.

When the converter operates in continuous conduction mode (CCM), then the ac ripples in all inductor currents can be assumed to be negligible. Based on this, the circuit operation in one switching cycle (Ts) can be divided into two stages as shown in Fig. 2(a-b). The operational mode is described briefly next.

Stage 1 [t0, t1], Fig. 2(a): when the power switch S is turned-on, diodes D1 and D2 are turned-off by the negative voltage -(Vg + VC) across them. In this stage, the current through both the C capacitors are the same, and it is equalto the negative inductor L3 current. Thus, in this stage, both capacitors C are effectively in series charging the load. At the end of this interval, the switch S is turned-off initiating the next subinterval.

Stage 2 [t1, Ts], Fig. 2(b): At the instant tl, switch S is turned-off, both D1 and D2 are turned-on simultaneously providing a path for the input and output inductor currents. In this stage, the two capacitors C are effectively in Parallel; hence, they are being charged equally.

The volt-second relationship of inductor L1, L2, and L3gives the following relations

Fig. 1. Proposed modified SEPIC converter.

Fig. 2. Topological stages for the converter of Fig. 1.

1'g C CV D V V (1)

1C CDV VD

(2)

12o C CV D D V D V (3)

respectively, where D'=1-D is the normalized switch-off time and D is the switch duty-cycle. The input to output voltage transfer ratio of the proposed converter can be determined from (1) - (3),as

2'

o

g

V DMV D

(4)

It is clear from (4) that the voltage gain is twice the voltage gain of conventional SEPIC converter.

III. COMPARISON BETWEEN THE PROPOSED AND THE CONVENTIONAL SEPIC CONVERTER

A. Duty-Cycle DIn comparison with the conventional SEPIC converter,

the proposed converter operates at lower duty ratio for the same overall conversion ratio. The relation between the respective duty ratios D and DC is obtained from2

1 1C

C

DD MD D

(5)

+

Vo

-

L1

Vg S Co RL

D1C1

L2

L3

CC

D2

+

Vo

-

L1

Vg SCo RL

C1

L2

L3CC

+ VL1 -

+VC-

+ VC1 -

+VC--

VL2+

+ VL3 -

IoiL1

iL2

iL3

a) Switch on topology

- VD +

+ VD -

iS

iC

+

Vo

-

L1

VgS Co RL

D1

C1

L2

L3CC

D2

+ VL1 -

+VC-

+ VC1 -

+VC--

VL2+

+ VL3 -

IoiL1

iL2

iL3

+VS-

iD2

iC

b) Switch off topology

iD1

432


where the subscript C is used to refer to the conventional SEPIC. Solving for D in (5) gives,

2C

C

DDD

(6)

it is clear from (6) that D is always less than DC. This is an attractive feature for high DC voltage gains, since the conventional SEPIC converter must operate at extremely high duty-cycle ratios. This means that the output diode in the SEPIC must sustain a short pulse width current with high amplitude. Thus, resulting in severe reverse-recovery as well as high EMI problems.

B. Semiconductors StressesThe comparison between the semiconductors normalized

stresses for the proposed SEPIC topology and conventional SEPIC converter are listed in Table I. Voltages and currents are normalized with respect to Vo and Io, respectively. Referring to Table I, it can be seen that the proposed SEPIC topology has lower switch and diode blocking voltages than the conventional SEPIC converter. Moreover, the switch voltage stress in the proposed SEPIC topology decreases as M increases, approaching half of the output voltage in the limit. This is unlike the conventional SEPIC converter where the switch voltage stress approaches the output voltage for high values of M. Thus, the proposed converters enable the use of a lower voltage rated with low RDS-ONMOSFET switch that are smaller and less costly; hence, it reduces switch conduction and turn-on losses.

Table I also shows that the average diode current in both the proposed topology and the conventional SEPIC are equal to the output load current Io. However, the peak diode current in the proposed topology is lower than its counterpart in the conventional SEPIC converter. Consequently, the diode root-mean-square (rms) current is lower for the proposed topology. On the other hand, the switch current in the proposed convert is equal to the sum of the three inductor currents, whereas in the conventional SEPIC the switch current equals to the sum of two inductor currents. As a result, the switch rms current in the proposed converter is slightly higher than its counterpart in the conventional SEPIC. This is the main disadvantage of the proposed converter. However, this does not mean that the switch conduction loss in the proposed converter is much higher than the switch conduction loss in the conventional SEPIC, since the power switch in the proposed converter has lower voltage stress with lower RDS-ON.

C. Active Switch UtilizationActive switch utilization factor U, which is defined as

the converter output power divided by the total product of the peak voltage times the rms current through the given set of converter active switches, represents how well a circuit topology uses the capability of its switches to achieve the

TABLE I.A COMPARISON BETWEEN CONVENTIONAL SEPIC AND PROPOSED SEPIC

TOPOLOGY OPERATING IN CCM

Item Proposed Converter (Fig. 1)SEPIC

Converter

Peak switch and diode voltage

22

MM

1 MM

Switch rms current 2M ( M ) 1M ( M )

Diode rms current 12M

1 M

Diode average current 1 1

output power [9]. Converters having high values of U factor implies the power that a switching device processes for agiven output is reduced, which can alleviate conduction and switching loss, hence it operates with relatively higher efficiency. Thereby, evaluating active switch utilization factor is a good tool to compare different converter topologies. The U factor for the proposed topology is given by

32 (2 )MUM

(7)

whereas for the conventional SEPIC converter is given by

31C

MUM

(8)

Graphical representation of (7) and (8) are shown in Fig. 3. The maximum U factor for both converter is equal to 0.385, whereas both converters have the same value of U=0.377 when M=0.7. It is clear from Fig. 3 that for values of M>0.7, the switch is utilized much better in the proposed topology than the switch in the conventional SEPIC converter.

Fig. 3. Active switch utilization U as a function of voltage conversion ratio, M.

0 1 2 3 4 50.0

0.1

0.2

0.3

0.4

0.5

Proposed Topology Conventional Sepic

Activ

e swi

tch

uitli

zatio

n, U

Voltage conversion ratio, M

M=0.7

433


D. Output Capacitor CoThe expression of the normalized output voltage ripple

for the proposed converter of Fig. 1 is given by2

38 (2 )o s

o o

v TV L C M

(9)

In conventional SEPIC converter, the output capacitor supplies the entire output load current during the switch on-time. Thus, the normalized output voltage ripple for the conventional SEPIC converter is given by,

1o C s

o L o

v T MV R C M

(10)

For comparison purpose, the ratio between (9) and (10) result in

3

1 14 (2 )

o

o C

v Mv K M M

(11)

where

33

2

L s

LKR T

(12)

Unlike the conventional SEPIC converter, (9) shows that the output voltage ripple is independent of load. Moreover, for CCM operation, the defined ratio in (11) is always less than one when M>0.13. Another advantage of the proposed converter over the SEPIC converter is the low peak ripplecurrent through the output capacitor Co due to the absence of the output diode. Thus, it is possible to use output capacitors with higher equivalent-series-resistance (ESR) than would be allowed for a conventional SEPIC converter.The ratio between the rms currents for the proposed topology and the SEPIC converter is given by,

3

12 3

Co rms

Co rms C

II K M M

(13)

Graphical representation of (11) and (13) are shown in Fig. 4 for several values of K3. The minimum value of K3that will insure the converter of Fig. 1 to operate in CCM is 0.75 (assuming that L1=L2=L3). It is clear from Fig. 4 that the proposed SEPIC topology has an advantage of lower output voltage ripple and output capacitor rms current over the conventional SEPIC converter. Moreover, the reduction in both the voltage ripple and the rms current becomes more pronounced with increasing M. For example, consider when K3=1 and M=5, output voltage ripples are 24 times less, and the rms current through the output capacitor is 27 times less, than the conventional SEPIC converter.

E. Input Current RippleThe peak-to-peak input inductor current ripple ( iL1) in

both the proposed and the conventional SEPIC converters are proportional to the operating duty-cycle, hence, their ratio is given by

Fig. 4. a) Output voltage ripple ratio, b) Output capacitor rms current ratio, between the proposed and conventional SEPIC converters as a function of M.

1

1

12

L

L C C

i D Mi D M

(14)

From (14), it clear that the defined ratio value is always less than one for any operating point of M. This is true since the proposed topology always operates at lower duty-cycle than the conventional SEPIC converter provided M is the same.

IV. THE PROPOSED CONVERTER WITH COUPLED INDUCTORS

In the proposed circuit of Fig. 1, the three inductors have identical voltage waveforms; hence they can be magnetically coupled into a single magnetic core as shown in Fig. 5. Note that Fig. 5 shows that the input inductor L1and the output inductor L3 are both coupled to L2, but that L1 and L3 are not directly coupled. Moreover, by proper selection of the coupling coefficients k12 and k23, near zero current ripples in input and output inductors can be obtained. This is an attractive feature since zero ripple input current tends to minimize both the system noise level and EMI at the input port of the converter. Whereas zero ripple output input current tends to eliminate or reduce the size of the output filter capacitor. In reality, the ripple current is not exactly reduced to zero but is highly reduced. The reason for this is that the voltages across the inductors are not exactly identical because of the ripple voltage across the capacitors.

Referring to Fig. 5, the rate of change of the inductor currents iL1, iL2, and iL3 during switch on-time is given by,

21 2 3 23 12 23 3 12 23

2 12 3 1 3 23 12 3 12 2

3 12 23 1 2 23 1 1 2 12

1

( ) 2

L g

L C

L C o

i L L M M M L M M Vd i M L L L M M L Vdt

i M M L L M M L L M V V

(15)

where2 2

1 2 3 1 23 3 12 0L L L L M L M (16)

1 2 3 4 50.00

0.05

0.10

0.15

0.20

1 2 3 4 50.00

0.05

0.10

0.15

0.20

v o /

v o-C K3=1

K3=2 K3=5

(a)

(b)

I Co-

rms /

I Co-

rms-C

Voltage conversion ratio, M

K3=1 K3=2 K3=5

434


and

12 12 1 2 23 23 2 3,M k L L M k L L (17)

are the mutual inductances of the windings. At steady state, VC1=Vg and Vo=2VC, then from (15) the following two conditions must be satisfied for zero ripple in the input and output inductors,

212 3 12 23 3 23 0

gL Vdi L L M M L Mdt

(18)

231 2 23 12 1 12 0

gL Vdi L L M M L Mdt

(19)

respectively. Solving (18) and (19) gives the following result,

212 2 1

1

12 23 2

223 2 3

3

,

,

Lk L LL

M M LLk L LL

(20)

with2 2

12 23 1k k (21)During switch off-time, the conditions for zero ripple in

the input and output inductor is similar to the one in (20). In order to verify (20), the circuit of Fig. 1 and Fig. 5 have been simulated for the following values: Vg = 20 V, Vo =40 V, RL = 10 , fs = 50 kHz, C1 = C = 100 F, Co = 47 F, L1 = L3 = 100 H, and L2 = 46.24 H. It is clear from the simulation results shown in Fig. 6 that near zero current ripples at both input and output is achieved by coupling the three inductors into a single magnetic structure.

Fig. 5. Proposed converter with coupled inductors.

Fig. 6. Simulated inductors current waveforms in CCM. (a) Un-coupled inductors, Fig.1. (b) Coupled inductors, Fig. 5.

The circuit of Fig. 5 can supply free ripple current in the input and output inductor not only in CCM but in DCM as well where the high switching ripple are of concern. This is a very desirable feature for power factor correction (PFC) applications since it will minimize the EMI effect and the input filtering stage [10]-[13]. On the other hand, the proposed converter is suitable for PFC applications when operating in DCM. In this case, the averaged input current over one switching period is given by

2

1 2g s

Le

V D Ti

L(22)

where

e 1 2 3

1 1 1 1=L L L L

(23)

Thus, if Vg is a rectified sinusoid voltage, then the average or low frequency component of the converter input current naturally follows the ac line voltage waveform, provided that the switching frequency and the duty-cycle are kept roughly constant. Note that (22) is similar to result obtained for conventional SEPIC and Cuk converters [10], except for the definition of Le which is defined as a parallel combination of three inductors instead of two.

In order to demonstrate the effect of coupling the inductors on the input line current, the circuit of Fig. 5 has been simulated with ac line input voltage followed by a bridge rectifier for two cases: a) with three separate inductors (uncoupled), b) with coupled inductors. No additional input filtering has been included in the simulation. The simulated input line voltage and input current waveforms for uncoupled and coupled case are shown in Fig. 7(a) and 7(b), respectively. The percent of the total harmonic distortion (%THD) in the input line current is about 1.5% for the two cases. However, Fig. 7(b) shows that the high frequency switching ripple current is greatly reduced due to the coupling of the three inductors. Thus, the generated EMI noise level is greatly minimized as well as the requirement for the input filtering. Another advantage of coupling the three inductors is a significant reduction in the rms current through the output filter capacitor Co. It should be mentioned here that the zero ripple input and output current feature presented in this section for the converter of Fig. 5 can be also obtained in the conventional Cuk converter using coupled inductors [4]. However, the proposed converter has an advantage of wider voltage conversion ratio, reduced switch and diode voltage stress, better switch utilization, as well as non-inverted output polarity.

V. EXPERIMENTAL RESULTSThe circuit in Fig. 1 has been built in the laboratory. The

converter is designed for a nominal voltage conversion ratio M = Vo/Vg = 48 V/24 V=2, and with fs = 75 kHz. The

+

Vo

-

L1

Vg S Co RL

DC1

L2

L3CC

D

iL1

iL2

iL3

M12, k12 M23, k23

iL1 iL3

0 20 40 60 80 1000A

2A

4A

6A

8A

10A

iL3iL2

iL1

0 20 40 60 80 1000A

2A

4A

6A

8A

10A

iL3iL2

iL1

(a) (b)Time [s] Time [s]

435


switch duty-cycle is set to 0.5 (according to (4)). Fig. 8shows the measured input/output voltage waveforms and the switch blocking voltage VS. It is evident from Fig. 8that the experimental results show a good agreement with the predicted results.

Fig. 7. Simulated waveforms for the converter of Fig. 4 with rectified ac input voltage source: a) Un-coupled inductors. b) Coupled inductors. Simulation parameters: vac = 100 Vrms, Vo = 220 Vdc, RL = 150 , fs = 50kHz, C1 = 4 F, C = 20 F, Co = 2 mF, L1 = L3 = 150 H, and L2 = 54 H.

Fig. 8. Measured waveforms for the converter of Fig. 1 in CCM.

VI. CONCLUSIONNew technological advances are requiring converter with

wider conversion ratios. This paper presented a new simple high performance SEPIC derived converter with wide voltage conversion ratio, continuous output current and reduced voltage stress on all the semiconductors. The input and output current ripple can be greatly reduced to near zero level due to the utilization of a coupled inductor techniques. The proposed converter has few extra components in comparison to a standard SEPIC and it is regulated by the conventional PWM technique at constant frequency. However, the additional components is far outweighed by the remarkable advantages gained, thus expecting the popularity of this technique to other exiting topologies. The performance of the converter is verified by means of simulation and experimental tests. The experimental substantiate the analyses carried out throughout the paper.

REFERENCES[1] S. Cuk and R. D. Middlebrook, A new optimum topology switching

DC-to-DC converter, in Conf. Rec. 1977 IEEE Power Electronics Specialists Conference, pp. 160-179.

[2] S. Cuk and R. D. Middlebrook, Coupled-inductor and other extensions of a new optimum topology switching DC-to-DC converter, in Conf. Rec. 1977 IEEE Industry Applications Society Annual Meeting, pp. 1110-1126.

[3] R. Massey and E. Snyder, High voltage single ended DC-DC converter, in Conf. Rec. 1977 IEEE Power Electronics Specialists Conference, pp. 156-159.

[4] S. Cuk, A new zero-ripple switching DC-to-DC converter and integrated magnetics, IEEE Trans. on Magnetics, vol. 19, no. 2, pp. 57-75, Mar. 1983.

[5] F. S. Dos Reis, J. Sebastian, and J. Uceda, Characterization of conducted noise generation for Sepic, Cuk and Boost converters working as power factor preregulators, in Con. Rec. 1993 IEEE Industrial Electronics, Control, and Instrumentation (IECON), pp. 965970.

[6] L. Huber and M. M. Jovanovic, A design approach for server power supplies for networking, in Conf. Rec. 2000 IEEE Applied Power Electronics Conference, pp. 11631169.

[7] B. Axelrod, Y. Berkovich, and A. Ioinovici, Transformerless DC-DC converters with a very high DC line-to-load voltage ratio, in 2003 Proc. IEEE International Symposium on Circuits and Systems,vol. 3, pp. 435-438.

[8] H. Nomura, K. Fujiwara, and M. Yoshida, A new DC-DC converter circuit with larger step-up/down ratio, in Conf. Rec. 2006 IEEE Power Electronics Specialists Conference, pp. 1-7.

[9] R. W. Erickson and D. Makismovic, Fundamentals of power electronics, 2nd ed, Spinger Science, USA, 2001, ch. 6.

[10] D. S. L. Simonetti, J. Sebastian, The discontinuous conduction mode Sepic and Cuk power factor preregulators: analysis and design, IEEE Trans. on Industrial Electronics, vol. 44, no. 5, pp. 630-637, Oct. 1997.

[11] J. Chen and C. Chang; Analysis and design of SEPIC converter in boundary conduction mode for universal-line power factor correction applications, in Conf. Rec. 2001 IEEE Power Electronics Specialists Conference, pp.742-747.

[12] J. Lam, P. K. Jain, and V. Agarwal A novel SEPIC type single-stage single switch electronic ballast with very high power factor and high efficiency, in Conf. Rec. 2008 IEEE Power Electronics Specialists Conference, pp. 2861-2866.

[13] H-M Huang, S-H Twu, S-J Cheng, and H-J Chiu, A single-stage SEPIC PFC converter for multiple lighting LED lamps, in Proc. 4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA 2008), Hong Kong 2008, pp. 15-19.

(a) (b)Time [s] Time [s]

0.98 0.99 1.00 0.98 0.99 1.00

20

10

0

10

-20

20

10

0

10

-20

vac/10 vac/10

iac iac

Volt,

Am

pere

436


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