Analog & Mixed Signal IC Design Department Of ECE NIT Warangal-506004

Sense Amplifiers for SRAMsDetails of registrationNameMudasir BashirRoll No.714025SupervisorDr. PATRI SRIHARI RAODate of 18-July 2014registrationType of Full-timeregistration No. of semesters 01completed

Presentation Outline:Course WorkMotivationSRAMsSense AmplifierClassificationBit-line modelLiterature SurveyDesign IssuesProposed WorkFuture WorkReferences

Course Work:S.NoSubjects CreditsTypeSemester1.Analog IC Design4Class WorkIst Sem2.Device Modelling3Class WorkIst Sem3.English for Scientific CommunicationAuditClass WorkIst SemMotivationAccording to the 2002 ITRS, the memory chip will occupy 90% of the chip area by 2013.SRAM is widely used to store digital dataHighly compatible to standard CMOS processesMajor Issues: Charge retentionEnduranceScalingSense amplifiers are one of the important peripheral devices in SRAMs.6T SRAM CellCell size accounts for most of array sizeReduce cell size at expense of complexity6T SRAM CellUsed in most commercial chipsData stored in cross-coupled invertersRead:Precharge bit, bit_bRaise wordlineWrite:Drive data onto bit, bit_bRaise wordline

Source [9]Sense AmplifiersActive circuitsUsed to retrieve the stored data in the memory cellReduces the access timeAmplify the signal variations on the bit line

outputinputs.a.smalltransitionSensing Amplifier Design Objective and ClassificationDesign Objective Minimum sense delay Required amplification Minimum power consumption Restricted layout area Highly reliableMinimum Sense Dead ZonesClassification

Circuit Types Opration Mode

Differential Voltage-mode

Non-differentialCurrent-mode

Methods of Sensing

Source: [10]Bit Line Model

Source [1]Delay for Voltage-Mode [Evert Seevinck et.al]

RC delayFor voltage-mode signals, RL is infinite and the output signal is the open-circuit voltage Vo .

Delay for Current-Mode

For current-mode signals, RL is ideally zero and the output signal is the short-circuit current Io.ExampleWhen RB = 2500 RT=250 CT=2pf

Voltage-mode tv = 5.25ns

Current-mode ti = 0.235nsPaper NameTopology ProposedProsConsModificationMacro.et.al, "Analog S/A for high density NOR flash memories, IEEE, 1992Two Voltage mode S/A,1 CMSA,Performance comparisonLow area overhead,CMSA better performance,CMSA can be made llel & more than one cells can be accessedData retention,Current conveyerConsideration of mismatch effectsDaejin Park. et.al, "Built in binary code inversion technique for on chip S/A, IEEE, 20143 Inversion schemes introduced,Clamped bit line S/AReduced the sensing current of S/AComputational overhead,Large no. of gate counts,Access delay ---------Y.Tsiatouches et.al, "New memory S/A design in CMOS technology, IEEE, 2007Current sensing approach,Proposed two topologies:-CMS & CCSSmall voltage swing on the bitlines,CMS has better performance than CCS,areaCurrent conveyer,Sense Access timeAccuracy,Access timeOtsuk et.al, "Circuit techniques for 1.5V power supply flash memory, IEEE,2001Self biasing,Clamped bit line S/A,N channel transistorLow power operationUse of dummy bitline for every SA.Need of n-channel transistorCurrent mirror A conte et.al, "A 1.35V S/A for non volatile memories based on CM applications , IEEE 2004Folded mirror active loadGain is increased by factor 2,Improves slew rate,Speed up the precharge phaseArea ------------Ali Hajimiri et.al, "Design issues in cross coupled inverters S/A, IEEE,2009+ve feedback is exploited in CMOS cross coupled inverter pair S/AFast sensing operationMismatch effects,Current conveyerAccuracy,Mismatch effectsLiterature Survey (contd):

Chrisanthopoulo et.al, Comparative study of different current mode sense amplifiers in submicron CMOS technology, IEEE Proc. Circuits Devices Syst., Vol. 149, No. 3, June 2002 .Siti Lailatul Mohd et.al, Comparative study on 8T SRAM with different types of sense amplifiers IEEE-ICSE 2014 Proc. 2014.

Contd..

Sense Amplifier Design Issues:Most of the CMSA configurations use current conveyer for PrechargingSense dead zonesBit-line leakage Mismatch effects :Threshold mismatchTransconductance mismatch

Source [7]VBL =VBLProposed Work:Modification of Clamped Bit-line CSA by replacing the current conveyer circuits for accurate results.Optimization of design issuesProposed CSA

V01V02Simulations:Transient response of CSA during read operation

Simulations (contd):

Power Dissipation VS TemperatureVariation of Sense Delay w.r.t. Bitline CapacitanceComparison table:This work[11]CMOS Technology180 nm180 nmInput Differential Current (A)9880Frequency (MHz)500500Power Supply (V)1.81.8Sense Delay (pS)596.6 (764)723Power Consumption (uW)~ 88-------Layout

Extracted viewFuture Work:Complete my course workSense Dead zonesMismatch & bitline leakage effectsNew Analog/Mixed signal design layout strategiesADCs

Memory section (SRAM +SA)ADCAnalog application like Image Sensors, Touch screens, pace maker Proposed work flowReferences:[1] E. Sccvinck, P. J. van Beers, and H. Ontrop, Current-Mode Techniques for High- Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAMs, IEEE Journal of Solid-State Circuits Vol.26 No.4 pp.525-536 April 1991.[2] T. P. Haraszti, High Performance CMOS Sense Amplifiers, United States Patent No. 4,169, 233, Sep. 1979.[3] Tegze P. Haraszti, CMOS Memory Circuits, Kluwer Academic Publishers, 2000.[4] V.Kristovski and Y. L. Pogrbeny, New Sense Amplifier for Small-Swing CMOS Logic Circuit, IEEE Trans, On Circuit and Systems, vol. 47, p.p. 573~576, June 2000.[5] Evert Seevinck, Petrus J. van Beers, Hans Ontrop, Current mode techniques for high speed VLSI circuits with the application of CSMA for CMOS SRAMs, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 26, No. 4, April 1991.[6] Do Anh-Tuan et. Al, Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing, IEEE Transactions On Circuits And Systemsii: Express Briefs, Vol. 55, No. 10, October 2008

References:[7] A. Chrisanthopoulo et.al, Comparative study of different current mode sense amplifiers in submicron CMOS technology, IEEE Proc. Circuits Deuices Syst., Vol. 149, No. 3, June 2002 .[8] ROBERTO BEZ et.al, Introduction to Flash Memory, Proceedings of the IEEE, Vol. 91, No. 4, April 2003.[9] Majumdar, B et. Al, Low power single bitline 6T SRAM cell with high read stability, International Conference on Recent Trends in Information Systems (ReTIS), 2011.[10] B. Wicht, "Current Sense Amplifiers for Embedded SRAM in High Performance System on a Chip Designs", Springer,1st edition ,2003.[11] S. Patil, M. Wieckowski, and M. Margala, A self-biased charge transfer sense amplifier, in IEEE Int. Symp. Circuits Syst., vol. 4, pp. 30303033, 2007.

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