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SPIN TORQUE TRANSFER RAM 1 Introduction 4 1.1 Non volatile RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Spin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 Spin Transfer 2 Introduction 2.1 Spintronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 Metal based spintronics devices. . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 Semiconductor based spintronics devices. . . . . . . . . . . . . . . . . . . 9 2.2 Tunnel Magneto resistance effect (TMR). . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 STTRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Page 1

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Page 1: Seminar Sridhar Report

SPIN TORQUE TRANSFER RAM

1 Introduction 4

1.1 Non volatile RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Spin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3 Spin Transfer

2 Introduction

2.1 Spintronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1.1 Metal based spintronics devices. . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1.2 Semiconductor based spintronics devices. . . . . . . . . . . . . . . . . . . 9

2.2 Tunnel Magneto resistance effect (TMR). . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 STTRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Memory concept

3.1 History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 Universal memory concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4 Working of STTRAM

4.1 Spin torque transfer RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.2 Writing ‘0’ and ‘1’. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3 Reading ‘0’ and ‘1’. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5 Fabrication of STTRAM 22

6 Research undergoing on STTRAM 23

7 Scope of STTRAM 28

8 Comparison with conventional memory RAM 30

9 Applications STTRAM in Aviations and Military 32

10 IC designers benefits 34

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11 Conclusions 35

12 References 36

LIST OF FIGURES & TABLES

FIGURE 1.2 : SPIN...………………………….………………………………………….4

FIGURE 2.3 : MAGNETIC TUNNEL JUNCTION ……………………………………11

FIGURE 4.1.1 : NANOMAGNETS USED TO CONTROL THE SPIN…….…………...13

FIGURE 4.1.2 : MATERIAL USED IN MTJ…………......................................................14

FIGURE 4.1.3 : THE MTJ STATE CHANGES FROM PARALLEL TO

ANTIPARALLEL……………………………………………………….14

FIGURE 4.1.4 : SIMULATION MODEL SYMBOL IN THE SPECTRE

SIMULATOR……………………………………………………………15

FIGURE 4.1.5 : RESISTANCE EQUIVALENT CIRCUIT………………………..……15

FIGURE 4.1.6 : STT-RAM ARCHITECTURE…..……………………………………….15

FIGURE 4.1.7: WRITING LOGIC 0 AND LOGIC 1 IN STT-RAM................................16

FIGURE 4.1.8 : CONVENTIONAL MRAM AND STT-RAM………………………….18

FIGURE 4.2.1 : ION MILLING AND LIFT-OFF METHOD…………….……………....19

FIGURE 4.2.2 : STT-RAM OVERCOMING POWER TRADE OFF PROBLEM ……...20

FIGURE 4.2.3 : DC AND TRANSIENT SIMULATION………..……………………….21

FIGURE 4.2.4 : DC SIMULATION OF MTJ (PARALLEL) ………..…………………..21

FIGURE 4.2.5 : TRANSIENT SIMULATION OF MTJ FOR PARALLEL AND

ANTI-PARALLEL..………...…………………………………………...22

FIGURE 6.4.1 : INPUT SPIN-LUT ARCHITECTURE..….………..…………………….31

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FIGURE 6.4.2 : THE FULL SCHEMATIC OF SPIN-MTJ BASED NON-VOLATILE FLIP-FLOP (SPIN-FF)………………………………...

………...........…31

FIGURE 6.4.3 : MTJ MEMORY CELLS ARE IMPLEMENTED ABOVE THE

CMOS CIRCUITS………………………………………………....……32

FIGURE 6.4.4 : FULL LAYOUT (5.65UM×10.15UM) OF SPIN-FF..……...……….…..32

TABLE 6.2.1 : STT-RAM PROTOTYPE VERSUS EXISTING MEMORY CHIP.........28

LIST OF SYMBOLS & ABBREVIATIONS

1. µ : INTRINSIC MAGNETIC MOMENT OF THE SPIN

POLARIZED ELECTRON.

2. Å : ANGSTROM=10-10 meters.

3. CMOS : COMPLEMENTARY METAL OXIDE SEMICONDUCTOR.

4. DRAM : DYNAMIC RANDOM ACCESS MEMORY.

5. ESPV : EXCHANGE-BIASED SPIN VALVES.

6. F : FERMI= 10 -15 meters.

7. FPGA : FIELD PROGRAMMABLE GATE ARRAY.

8. GMR : GAINT MAGNETO RESISTANCE.

9. MCP : MULTI-CHIP PACKAGES.

10. MRAM : MAGNETIC RANDOM ACCESS MEMORY.

11. MTJ : MAGNETIC TUNNEL JUNCTIONS.

12. NVRAM : NON- VOLATILE RANDOM ACCESS MEMORY.

13. RAP : RESISTANCE INTRODUCED IN TMR DUE TO ANTI

PARALLEL ACTION IN THE FREE

FERROMAGNETIC LAYER.

14. RP : RESISTANCE INTRODUCED IN TMR DUE TO

PARALLEL ACTION IN THE FREE FERROMAGNETIC

LAYER.

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15. SPIN-LUT : SPIN LOOK UP TABLE.

16. SPIN-FF : SPIN FLIP FLOP

17. SOC : SYSTEM ON CHIP.

18. SRAM : STATIC RANDOM ACCESS MEMORY.

19. STS : SPIN TRANSFER SWITCHING.

20. STT-RAM : SPIN TORQUE TRANSFER RANDOM ACCESS MEMORY.

21. TMR : TUNNEL MAGNETO RESISTANCE .

22. VLSI : VERY LARGE SCALE INTEGRATION.

CHAPTER-1:

BASIC TERMINOLOGIES

1.1 NON-VOLATILE RAM

Non-Volatile Random Access Memory (NVRAM) is the general name used to describe

any type of random access memory which does not lose its information when power is turned

off. This is in contrast to the most common forms of random access memory today, DRAM and

SRAM, which both require continual power in order to maintain their data. NVRAM is a

subgroup of the more general class of non-volatile memory types, the difference being that

NVRAM devices offer random access, like hard disks.

1.2 SPIN

In quantum mechanics, spin is a fundamental property of atomic nuclei, hadrons, and

elementary particles. For particles with non-zero spin, spin direction (also called spin for short) is

an important intrinsic degree of freedom.

As the name indicates, the spin has originally been thought of as a rotation of particles

around their own axis. This picture is correct insofar as spins obey the same mathematical laws

as do quantized angular momenta. On the other hand, spins have some peculiar properties that

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distinguish them from orbital angular momenta: spins may have half-integer quantum numbers,

and the spin of charged particles is associated with a magnetic dipole moment in a way (g-factor

different from 1) that is incompatible with classical physics.

The electron spin is the key to the Pauli Exclusion Principle and to the understanding of

the periodic system of chemical elements. Spin-orbit coupling leads to the fine structure of

atomic spectra, which is used in atomic clocks and in the modern definition of the fundamental

unit second. Precise measurements of the g-factor of the electron have played an important role

in the development and verification of quantum electrodynamics. Electron spins play an

important role in magnetism, with applications for instance in computer memories. Manipulation

of spins in semiconductor devices is the subject of the developing field of spintronics. The

manipulation of nuclear spins by radiofrequency waves (nuclear magnetic resonance) is

important in chemical spectroscopy and medical imaging. The photon spin is associated with the

polarization of light.

The head-on collision of a quark (red ball) from one proton (orange ball) with a

gluon (green ball) from another proton with opposite spin, spin is represented by the blue

arrows circling the protons and the quark. The blue question marks circling the gluon

represent the question: Are gluons polarized? Ejected from the collision are a shower of

quarks and a photon of light (purple ball).

Figure 1.2 SPIN

Particles with spin can possess a magnetic dipole moment, just like a rotating electrically

charged body in classical electrodynamics. These magnetic moments can be experimentally

observed in several ways, e.g. by the deflection of particles by inhomogeneous magnetic fields in

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a Stern–Gerlach experiment, or by measuring the magnetic fields generated by the particles

themselves. The intrinsic magnetic moment μ of an elementary particle with charge q, mass m,

and spin S, is

Where the dimensionless quantity g is called the g-factor. For exclusively orbital rotations it

would be 1.

In ordinary materials, the magnetic dipole moments of individual atoms produce magnetic fields

that cancel one another, because each dipole points in a random direction. Ferromagnetic

materials below their Curie temperature, however, exhibit magnetic domains in which the atomic

dipole moments are locally aligned, producing a macroscopic, non-zero magnetic field from the

domain. These are the ordinary "magnets" with which we are all familiar.

The study of the behavior of such "spin models" is a thriving area of research in

condensed matter physics. For instance, the Ising model describes spins (dipoles) that have only

two possible states, up and down, whereas in the Heisenberg model the spin vector is allowed to

point in any direction. These models have many interesting properties, which have led to

interesting results in the theory of phase transitions.

1.3 SPIN TRANSFER

Spin transfer is the phenomenon in which the spin angular momentum of the charge

carriers (usually electrons) gets transferred from one location to another. This phenomenon is

responsible for several important and observable physical effects.

Most famously, spin polarized current passing into a nanoscale magnet tends to deposit

some of its spin angular momentum into the magnet, thereby applying a large torque to the

magnetization. This enables magnetic manipulations far more efficiently than can be achieved

with magnetic fields alone, especially as device applications shrink in scale. In the hard disk

industry, where a series of nanoscale magnetic layers called a spin valve is often used to measure

the small local magnetic fields above the disk surface, this is an undesirable effect, as it hinders

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the ability to measure the state of the valve without disturbing it. In the MRAM industry,

however, this effect may prove incredibly useful in reducing power consumption.

CHAPTER 2:

INTRODUCTION

2.1. SPINTRONICS:

Spintronics (a neologism meaning "spin transport electronics"), also known as magneto

electronics, is an emerging technology which exploits the intrinsic spin of electrons and its

associated magnetic moment, in addition to its fundamental electronic charge, in solid-state

devices.

Electrons are spin-1/2 fermions and therefore constitute a two-state system with spin "up"

and spin "down". To make a spintronic device, the primary requirements are to have a system

that can generate a current of spin polarized electrons comprising more of one spin species – up

or down – than the other (called a spin injector), and a separate system that is sensitive to the

spin polarization of the electrons (spin detector). Manipulation of the electron spin during

transport between injector and detector (especially in semiconductors) via spin precession can be

accomplished using real external magnetic fields or effective fields caused by spin-orbit

interaction.

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Spin polarization in non-magnetic materials can be achieved either through the Zeeman

Effect in large magnetic fields and low temperatures, or by non-equilibrium methods. In the

latter case, the non-equilibrium polarization will decay over a timescale called the "spin

lifetime". Spin lifetimes of conduction electrons in metals are relatively short (typically less than

1 nanosecond) but in semiconductors the lifetimes can be very long (microseconds at low

temperatures), especially when the electrons are isolated in local trapping potentials (for

instance, at impurities, where lifetimes can be milliseconds).

9.1 2.1.1 Metals-based spintronic devices

The simplest method of generating a spin-polarized current in a metal is to pass the

current through a ferromagnetic material. The most common application of this effect is a Giant

Magneto Resistance (GMR) device. A typical GMR device consists of at least two layers of

ferromagnetic materials separated by a spacer layer. When the two magnetization vectors of the

ferromagnetic layers are aligned, the electrical resistance will be lower (so a higher current flows

at constant voltage) than if the ferromagnetic layers are anti-aligned. This constitutes a magnetic

field sensor. Two variants of GMR have been applied in devices:

Current-In-Plane (CIP), where the electric current flows parallel to the layers.

Current-Perpendicular-to-Plane (CPP), where the electric current flows in a direction

perpendicular to the layers.

Other metals-based spintronics devices:

Tunnel Magneto Resistance (TMR), where CPP transport is achieved by using quantum-

mechanical tunneling of electrons through a thin insulator separating ferromagnetic layers.

Spin Torque Transfer , where a current of spin-polarized electrons is used to control the

magnetization direction of ferromagnetic electrodes in the device.

9.1.1 The storage density of hard drives is rapidly increasing along an

exponential growth curve, in part because spintronics-enabled devices like

GMR and TMR sensors have increased the sensitivity of the read head which

measures the magnetic state of small magnetic domains (bits) on the spinning

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platter. The doubling period for the areal density of information storage is

twelve months, much shorter than Moore's Law, which observes that the

number of transistors that can cheaply be incorporated in an integrated

circuit doubles every two years.

MRAM, or magnetic random access memory, uses arrays of TMR or Spin torque transfer

devices. MRAM is nonvolatile (unlike charge-based DRAM in today's computers) so

information is stored even when power is turned off, potentially providing instant-on computing.

Motorola has developed a 256 kb MRAM based on a single magnetic tunnel junction and a

single transistor. This MRAM has a read/write cycle of fewer than 50 nanoseconds. Another

design in development, called Racetrack memory, encodes information in the direction of

magnetization between domain walls of a ferromagnetic metal wire.

9.2 2.1.2 Semiconductor-based spintronic devices

In early efforts, spin-polarized electrons are generated via optical orientation using

circularly-polarized photons at the band gap energy incident on semiconductors with appreciable

spin-orbit interaction (like GaAs and ZnSe). Although electrical spin injection can be achieved in

metallic systems by simply passing a current through a ferromagnet, the large impedance

mismatch between ferromagnetic metals and semiconductors prevented efficient injection across

metal-semiconductor interfaces. A solution to this problem is to use ferromagnetic

semiconductor sources (like manganese-doped gallium arsenide GaMnAs), increasing the

interface resistance with a tunnel barrier, or using hot-electron injection.

Spin detection in semiconductors is another challenge, which has been met with the

following techniques:

Faraday/Kerr rotation of transmitted/reflected photons

Circular polarization analysis of electroluminescence

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Nonlocal spin valve (adapted from Johnson and Silsbee's work with metals)

Ballistic spin filtering

The latter technique was used to overcome the lack of spin-orbit interaction and materials

issues to achieve spin transport in Silicon, the most important semiconductor for electronics.

Because external magnetic fields (and stray fields from magnetic contacts) can cause

large Hall effects and magneto resistance in semiconductors (which mimic spin-valve effects),

the only conclusive evidence of spin transport in semiconductors is demonstration of spin

precession and de-phasing in a magnetic field non-collinear to the injected spin orientation. This

is called the Hanle effect.

Advantages of semiconductor-based spintronics applications are potentially lower power

use and a smaller footprint than electrical devices used for information processing. Also,

applications such as semiconductor lasers using spin-polarized electrical injection have shown

threshold current reduction and controllable circularly polarized coherent light output. Future

applications may include a spin-based transistor having advantages over MOSFET devices such

as steeper sub-threshold slope.

2.2 TUNNEL MAGNETORESISTANCE EFFECT (TMR)

In physics, the Tunnel Magneto Resistance effect (TMR), occurs when a current flows

between two ferromagnets separated by a thin (about 1 nm) insulator. Then the total resistance of

the device, in which tunneling is responsible for current flowing, changes with the relative

orientation of the two magnetic layers. The resistance is normally higher in the anti-parallel case.

The effect is similar to Giant Magneto Resistance except that the metallic layer is replaced by an

insulating tunnel barrier.

2.3 STT-RAM

STT-RAM is underway to fine tune a digital-data-recording technology, which will lead

to durable, high density memory chips impervious to radiation and capable of virtually unlimited

read/write cycles called SPIN TRANSFER TORQUE RANDOM ACCESS MEMORY (STT-

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RAM) chips, the devices are expected to be cost-competitive with conventional magnetic

memory chips and provide a “revolution in military and space electronics”.

STT-RAM chips use SPINTRONICS, a technology that controls the spin of an electron

to record binary data- the zeroes and ones of digital language. (Spintronics is short for “spin

electronics”).

An STT-RAM chip is somewhat similar, in manufacture at least, to the conventional

magnetic memory chips used in computers known as SRAM (STATIC RANDOM ACCESS

MEMORY), DRAM (DYNAMIC RANDOM ACCESS MEMORY) and MRAM

(MAGNETORESISTIVE RANDOM ACCESS MEMORY-a relatively recent nonvolatile chip

technology), and to NOR and NAND flash memory chips.

Toward the end of the manufacturing process, however, a magnet and thin film structure

are added to the chip. Rather than using a magnetic field to write zeroes and ones as with

conventional chips, an STT-RAM chip records digital data by passing a current through the

magnet and then over the film structure, which is about 700Å thick. As the current moves

through the magnet, it becomes polarized. Transferring the current through a pre-layer of film

20Å thick creates torque. The torque changes the direction of the polarized current and the

orientation of the pre-layer to the film below. By adjusting the current that passes through the

magnet, it can be made to move the pre-layer in parallel or low- resistance direction to the film,

which is recorded zero. If the current is adjusted so the pre-layer moves counter parallel or in a

high-resistance direction to the film, a one recorded.

STT-RAM is a novel nonvolatile memory which utilizes spin torque transfer

magnetization switching, the spin-RAM is programmed by magnetization reversal through an

interaction of a spin momentum-torque-transferred current and a magnetic moment of memory

layers in Magnetic Tunnel Junctions (MTJs), and therefore an external magnetic field is

unnecessary as that for a conventional MRAM.

In this spin transfer torque switching technique, data is written by re-orienting the

magnetization of a thin magnetic layer in a Tunnel Magneto Resistance (TMR) element using a

spin-polarized current. An electrical current is generally unpolarized (consisting of 50% spin-up

and 50% spin-down electrons), a spin polarized current is one with more electrons of either spin.

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By passing a current through a thick magnetic layer one can produce a spin polarized current. It

uses currents of spin-aligned electrons (spin-polarized currents) rather than fixed magnetic fields

for processing and storing information. Spin-polarized currents can be generated by driving a

current through a ferromagnetic layer. If the ferromagnetic electrode has a magnetization aligned

in one direction, the magnetic moments of electrons passing through it become aligned in the

same direction. It was theoretically predicted that such a spin-polarized current could transfer its

angular momentum to a second magnetic layer and therefore switch the magnetization of this

second layer into an alignment parallel with the reference layer, provided the dimensions of the

device are about 100 nm or less. Further research into the STT phenomena has led to new

materials and the replacement of metallic films with MTJs. MTJ resistance levels can be adjusted

through material selection and MTJs also provide greater difference between the resistance states

of the cell. Operation at room temperature has been reported using Aluminum Oxide as the

tunneling barrier, and more recent efforts with Magnesium Oxide have shown promise for a

reduction in power. Based on innovations in the MTJ, it is quite possible to develop a very

compact and scalable memory that exploits spin and avoids the circuit issues surrounding prior

art. With the optimal choice of materials, this STT memory would have fast read/write and be

non-volatile, low power, and scalable. It would also be uncomplicated to fabricate and could

conceivably be done in a silicon foundry if the process and materials were designed for

compatibility as well. This seeks innovative research proposals for achieving a STT technology

for dense solid-state memories for defense applications.

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Figure 2.3: Magnetic tunnel junction. Resistance is low when the magnetization of the

reference and storage layer is aligned in same direction and high when the layers aligned in

opposite direction.

CHAPTER 3:

HISTORY

Prior research in micro-magnetic and spintronics has led to the exploitation of Giant

Magneto Resistance (GMR) effects for rotating magnetic disk drive memories, as well as

Magnetic Tunneling Junctions (MTJ) for Magnetic Random Access Memory (MRAM). The

Spin-Torque Transfer (STT) switching effect is a new physics phenomenon that exploits

magnetic spin states to electrically change the magnetic orientation of a material that was

theoretically predicted in 1996 and first demonstrated in metallic thin films as recently as 2000.

Although STT switching currents were initially orders of magnitude too high for application in

practical devices, Grandis was founded in 2002 with the goal of developing a novel non-volatile

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memory technology that applies the many benefits of STT switching to Magnetic Tunnel

Junctions (MTJs). Researchers at Grandis undertook pioneering research in spintronics and

pursued new magnetic materials and innovative MTJ structures to lower STT switching currents.

Through these advances in materials research, coupled with its extensive modeling, simulation,

integration, cell architecture, circuit and system design capabilities, Grandis has developed a

package that enables its licensees to incorporate stand-alone or embedded STT-RAM non-

volatile memory into their products.

The prototype chips are available for testing. The different companies are working hard to reduce

Time-To-Market. The STT-RAM will be available in the market by this year or by 2010.

CHAPTER 4:

WORKING OF STT-RAM

4.1 SPIN-TRANSFER TORQUE RAM as universal memory

Nanomagnet are used to control the spin. By passing electrons through the nanomagnet,

the spin of the electrons can be aligned in the same magnetization direction as the nanomagnet.

As shown in Figure 4.1.1, below a Magnetic

Tunnel Junction (MTJ) is at the heart of a

STT-RAM bit cell. The MTJ consists of two

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ferromagnetic electrodes with a thin insulating layer in-between. The top nanomagnet is the

storage layer or "free" layer; the middle is the barrier; and the bottom nanomagnet is the

reference or "pinned" layer or spin filter.

Figure 4.1.1: Nanomagnets used to control the spin.

Spin Transfer Switching (STS) changes the MTJ's state from antiparallel or "1" to

parallel or "0" and vice versa. This is performed by running current from the top to the bottom of

the MTJ and vice versa. An STT-RAM chip addresses each bit individually by flowing current

directly through the bit.

Consequently, unintended writing errors are completely eliminated. A conventional

CMOS transistor below the MTJ produces the current. In this instance, switching is performed

via spin polarized currents. By polarizing the current, data is passed from the fixed MTJ layer

that is the polarizer to the free MTJ layer.

The materials used as ferromagnet in MTJ is CoFe and the layer in between the

ferromagnet i.e., tunnel barrier layer is made of AlxO or MgO, as shown in figure4.1.2 below.

Figure 4.1.2: Material used in MTJ.

TMR= (Rap-Rp) / Rap , Tunnel Magneto Resistance Ratio

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Figure 4.1.3: The

MTJ state changes from Parallel (P) to Antiparallel (AP) if the positive

direction current density I>Ic, on the contrast, its state will return if the

negative direction current density I > Ic. Where Ic is critical current

density.

This process is called spin-transfer torque switching. Current running through the fixed

layer polarizes the electrons. Those polarized electrons then affect the switching of the free layer,

hence the parallel and anti-parallel configurations.

Unlike the STT-RAM cell that exploits electron spins for writing, the conventional

MRAM cell, shown in Figure 4.1.8 at 20 to 30 F2 cell size uses a magnetic field to perform

switching. When the cell is activated, the bit line and write word line become active with current

pulses flowing through them, thus creating a magnetic field around the bit.

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Figure. 4.1.4 Simulation model symbol in the specter simulator.

Figure 4.1.5: Resistance equivalent circuit

Figure-4.1.6: STT-RAM architecture.

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Figure 4.1.7: STT-RAM writing logic 0 and logic 1- it addresses each bit individually by

flowing current directly through the bit. Unintended writing errors are completely

eliminated.

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It is this magnetic field that changes the state of the bit from "1" to "0" and vice versa.

The scalability issue is exacerbated as a conventional MRAM chip is subjected to increasingly

smaller geometries. As feature size shrinks, more current is required to create the magnetic field.

In a conventional MRAM cell, conductors or wires above and below the MTJ are used to

generate the fields necessary to switch the state of the free magnetic layer. The additional write

word line and bypass line required in this cell geometry translate into a more complicated

architecture. Hence, more lithographic steps and a more costly manufacturing process are

required.

Each conductor or wire requires a minimum of 5 to 10 mill amperes (mA) of current to

perform a switch. Conversely, STT-RAM technology incurs a considerably lower switching

current on the order of 100 microamperes, as a result of its more efficient spin-transfer torque

techniques.

Magnetic fields produced by first-generation switching methods typically expose an

entire column or row of bits, leading to inadvertent bit or write errors. As conventional MRAM

technology is scaled and memory cells become smaller, the cells must be structured with an

increasingly higher switching field to maintain each cell's thermal stability. Otherwise, the

probability of write disturbance increases.

A cell's thermal instability can erroneously trigger random switching to the opposite state.

This means the cell stability in conventional MRAM demands an increasingly higher current

flowing in the conductors or wires to efficiently switch states. Due to this bit or write

disturbance, the number of bad bits in conventional MRAM is very high. Consequently MRAM

vendors must resort to redundancy architectures with as much as 25 percent redundancy.

Shown at a cell size of 6 F2, the STT-RAM cell, Figure 4.1.8 on the other hand, does not

require the metal wire below the MTJ. The write word line, bypass line, and cladding associated

with the conventional MRAM cell are eliminated. Instead, current flows perpendicular through

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the MTJ memory cell. As STT-RAM technology is scaled and its cells become increasingly

smaller, the cross-sectional area becomes smaller and smaller.

Figure-4.1.8: Conventional MRAM and STT-RAM cell - Magnetic field, generated by the

bit line and write word line, is used to switch between the ‘0’ and ‘1’ states. STT-RAM cell

by eliminating the write word line and bypass line, it is considerably smaller than the first

generation MRAM cell.

Because STT-RAM uses a current running through the cell, the required writing current

that flows through the smaller MTJs decreases. As a result, STT-RAM has superior scaling

properties. That is the reason total required current in STT-RAM continues to be considerably

less with increasingly smaller geometries, whereas in conventional MRAM, the required

switching current increases with scalability, as shown in Figure 4.2.2.

Attempts have been made to correct the half-select bit write disturbance issue with

conventional MRAM by modifying its bit cell. One such technique is the toggle MRAM bit cell.

Its intent is to increase the operating window of the write operation. The objective is to create a

significant margin between the level of fields required for switching all bits and the level at

which write disturbs occur.

Attempts have been made to correct the half-select bit write disturbance issue with

conventional MRAM by modifying its bit cell. One such technique is the toggle MRAM bit cell.

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Its intent is to increase the operating window of the write operation. The objective is to create a

significant margin between the level of fields required for switching all bits and the level at

which write disturbs occur.

The toggle MRAM bit cell adds a second free magnetic layer and an anti-ferro-magnetic

coupling layer above the first free magnetic layer. Studies performed by the conventional

MRAM vendor reveal an increasing percentage of bits properly switch as a result of applying the

new toggle MRAM bit cell. However, it incurs higher currents (nearly 2X higher) and tighter

thickness control is required (control within one atomic layer).

DC and transient simulations have been performed to verify the bias-voltage dependent

resistance, TMR effect, the switching current and performance from parallel configuration (P) to

antiparallel configuration (AP) and AP to P (see Figure 4.2.3 to 4.2.5).

4.2 FABRICATION OF STT-RAM:

The fabrication of STT-RAM is done using Ion-milling and Lift-off Method.

Figure 4.2.1: ION MILLING AND LIFT-OFF METHOD

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Figure 4.2.2: STT-RAM overcoming power trade off problem - “Total required current in

STT-RAM continues to scale lower with increasingly smaller geometries. Conversely,

conventional MRAM switching current increases with smaller geometries.

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Figure 4.2.3: DC and Transient simulation.

Figure 4.2.4 DC simulation of MTJ (Parallel), the critical current is about 135.053uA and

the potential is about 80mV

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Figure 4.2.5 Transient simulation of MTJ, the critical current is about 153.206uA for

parallel and -221.202uA for anti-parallel

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CHAPTER 5:

RESEARCH UNDERGOING ON STT-RAM IN

DIFFERENT ORGANISTION

A NOVEL NONVOLATILE MEMORY WITH SPIN TORQUE TRANSFER

MAGNETIZATION SWITCHING: SPIN-RAM:

Hosomi, M. Yamagishi, H. Yamamoto, T. Bessho, K.

Higo, Y. Yamane, K. Yamada, H. Shoji, M. Hachino, H.

Fukumoto, C. Nagao, H. Kano, H. Sony Corp., Kanagawa;

This new programming mode has been accomplished owing to

tailored MTJ, which has an oval shape of 100 times 150 nm.

The memory cell is based on a 1-transistor and a 1-MTJ

structure. The 4kbit spin-RAM was fabricated on a 4 level

metal, 0.18 mum CMOS process. In this work, writing speed as

high as 2 ns, and a write current as low as 200 muA were

successfully demonstrated.

NANOELECTRONICS RESEARCH INSTITUTE- JAPAN:

To realize a large capacity Magnetic Random Access Memory (MRAM) that uses spin-

transfer switching for writing, it is essential to evaluate thermal durability and intrinsic critical

currents correctly. Here, we examined the theoretically predicted logarithmic relationship

between critical currents of spin-transfer switching and duration of injected pulsed currents using

Giant Magneto Resistive (GMR) samples with different magnetic materials, e.g., Co, Co–Fe25,

and CoFeB. This relationship was verified for the samples by giving reasonable thermal-

durability coefficients and intrinsic critical currents as fitting parameters. We found that thermal

durability was underestimated when an effective magnetic field acted on magnetic memory cells

antiparallel to their magnetization. We then experimentally demonstrated that thermal assistance

in spin-transfer switching decreased with increasing thermal durability.

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GRANDIS INC., 1123 CADILLAC COURT, MILPITAS, CALIFORNIA:

Dual Magnetic Tunnel Junction (MTJ) structures consisting of two MgO insulating

barriers of different resistances, two pinned reference layers aligned antiparallel to one another,

and a free layer embedded between the two insulating barriers have been developed. The

electron transport and spin dependent resistances in the dual MTJ structures are accounted for by

sequential tunneling with some spin-flip relaxation in the central electrode (the free layer). With

a tunneling magneto resistance ratio of 70%, a switching current density Jc (at 30 ms) of 0.52

MA/cm2 is obtained, corresponding to an intrinsic value of Jc0 (at 1ns) of 1.0 MA/cm2. This

value of Jc0 is 2–3 times smaller than that of a single MgO insulating barrier MTJ structure and

results from improvements in the spin-transfer torque efficiency. The asymmetry between

JcAP P and Jc

P AP are significantly improved, which widens the read-write margin for

memory device design. In addition, the experimental results show that the switching current

density can be further reduced when an external field is applied along the hard axis of the free

layer. Grandis is looking for STT-RAM to replace existing memory technologies at 45nm and

beyond. Since most processing at such advanced technology nodes is done on 300mm MTJ

wafers.

JAPAN SCIENCE AND TECHNOLOGY AGENCY, SENDAI 980-8579, JAPAN:

SUBSTANTIAL REDUCTION OF CRITICAL CURRENT FOR MAGNETIZATION

SWITCHING IN AN EXCHANGE-BIASED SPIN VALVE-

Great interest in current-induced magnetic excitation and switching in a magnetic

nanopillar has been caused by the theoretical predictions11, 12 of these phenomena. The concept

of using a spin-polarized current to switch the magnetization orientation of a magnetic layer

provides a possible way to realize future 'current-driven' devices13: in such devices, direct

switching of the magnetic memory bits would be produced by a local current application, instead

of by a magnetic field generated by attached wires. Until now, all the reported work on current-

induced magnetization switching has been concentrated on a simple ferromagnet/Cu/ferromagnet

trilayer. Here we report the observation of current-induced magnetization switching in

Exchange-Biased Spin Valves (ESPVs) at room temperature. The ESPVs clearly show current-

induced magnetization switching behavior under a sweeping direct current with a very high

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density. We show that insertion of a ruthenium layer between an ESPV nanopillar and the top

electrode effectively decreases the critical current density from about 108 to 107 Acm -2. In a

well-designed 'antisymmetric' ESPV structure, this critical current density can be further reduced

to 106 Acm-2. We believe that the substantial reduction of critical current could make it possible

for current-induced magnetization switching to be directly applied in spintronic devices, such as

magnetic random-access memory.

VORTEX POLARITY SWITCHING BY A SPIN--POLARIZED CURRENT

Jean-Guy Caputo, Yuri Gaididei, Franz G. Mertens, Denis D. Sheka

The spin-transfer effect is investigated for the vortex state of a magnetic nanodot. A spin

current is shown to act similarly to an effective magnetic field perpendicular to the nanodot.

Then a vortex with magnetization (polarity) parallel to the current polarization is energetically

favorable. Following a simple energy analysis and using direct spin--lattice simulations, we

predict the polarity switching of a vortex. For magnetic storage devices, an electric current is

more effective to switch the polarity of a vortex in a nanodot than the magnetic field.

DISTRIBUTION OF THE MAGNETIZATION REVERSAL DURATION IN

SUBNANOSECOND SPIN-TRANSFER SWITCHING

T. Devolder, C. Chappert, J. A. Katine, M. J. Carey, and K. Ito Institute d'Electronic

Fundamental, CNRS UMR 8622, University Paris Sud, Bat, 220, 91405 Orsay, France.

Hitachi Cambridge Laboratory, Hitachi Europe, Ltd., Cavendish Laboratory, Madingley Road,

Cambridge CB3 0HE, United Kingdom. Hitachi GST, San Jose Research Center, 650 Harry

Road, San Jose, California 95120, USA.

The experimental distribution of switching times in spin-transfer switching induced by

sub-ns current pulses in a pillar-shaped spin valve, whose free layer easy axis is parallel to the

spin polarization of the current. The pulse durations leading to successful switching events

follow a multiply stepped distribution. The step positions reflect the precessional nature of the

switching. Modeling indicates that the switching proceeds through an integer number of

gradually amplified precession cycles. This number is determined by the initial magnetization

state. The switching probability distribution can be modeled considering the thermal variance of

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the initial magnetization orientation and by analyzing the occurrence of a vanishing total torque

condition in the set possible magnetization trajectories. Modeling helps us to understand why

switching cannot happen with a reproducible sub-ns duration when the free layer easy axis is

parallel to the spin polarization of the current. To circumvent that problem, we propose to bias

the spin valve with a hard axis field, which could provide an increased reproducibility of the

switching duration.

A NOVEL SPRAM (SPIN-TRANSFER TORQUE RAM) WITH A SYNTHETIC

FERRIMAGNETIC FREE LAYER FOR HIGHER IMMUNITY TO READ DISTURBANCE

AND REDUCING WRITE-CURRENT DISPERSION:

Miura, K. Kawahara, T. Takemura, R. Hayakawa, J. Ikeda, S. Sasaki, R. Takahashi, H.

Matsuoka, H. Ohno, H.Hitachi Ltd., Tokyo;

A novel SPRAM (spin-transfer torque RAM) consisting of MgO-barrier-based Magnetic

Tunnel Junctions (MTJs) with a Synthetic Ferromagnetic (SyF) structure in a free layer was

demonstrated for both higher immunity to read disturbance and a sufficient margin between the

read and write currents. Since magnetization of the free layer becomes stable against thermal

fluctuation with increasing thermal-stability factor E/kBT, the SyF free layer of the MTJs

realized magnetic information retention of over 10 years due to its high E/kBT of 67.

Furthermore, it was found that the SyF free layer has an advantage of reducing dispersion of

write-current density Jc, which is necessary for securing an adequate margin between the read

and write currents.

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CHAPTER 6:

SCOPE OF STT-RAM

6.1. ADVANTAGES OF STT-RAM CHIPS OVER

CONVENTIONAL CHIPS

The magnetic film on which digital data are recorded in conventional chips is prone to

“write disturbance” under some conditions, which affects accuracy and retention. But this

is not in case of STT-RAM.

Conventional magnetic films have a scalability problem, this not in case of STT-RAM.

STT-RAM chip use less current as the technology becomes smaller in size, so their cells

can shrink with no tradeoffs in power. This is all dependent on the concept “more current

is needed as the chip sizes shrink to create magnetic film, which makes the cell size

bigger because a higher current requirement affects the size of transistors”.

STT-RAM technology is the front runner because it offers embedded designers the best

of all worlds.

An external magnetic field is unnecessary as that for a conventional MRAM.

The STT-RAM chips comparatively require less power than conventional chips.

1.2V is enough to run STT-RAM chip, where as DRAM chips require 2V, a NOR flash

memory chip needs 6-8V and a NAND chip uses 16-20V.

In terms of speed STT-RAM write as fast as 2 nanosecond, which is comparable to

MRAM chips.

The read/ write cycle for all practical purposes infinite (in excess of 1015- 1,000 trillion-

cycles).

The user won’t need to move data from one format to another when using STT-RAM,

because it as the ability to work with virtually all systems equally well.

It has the capacity to preserve data under radiation and other hazards.

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6.2. STT-RAM versus other Conventional Memory Chip

As shown in Table 6.2.1 below, STT-RAM technology will provide embedded designers

better features compared with conventional memory technologies and future "universal memory"

candidates.

With a two nanosecond (ns) write time, STT-RAM is as fast as SRAM, which currently

has a write time ranging from 1 to 100 ns, depending on the technology used. As far as cell size,

STT-RAM fares much better than SRAM cell size. When STT-RAM reaches the 32 nm

technology node, the cell will be equal to or smaller than DRAM or NOR flash.

Table 6.2.1-Overall STT-RAM is superior to other memory technologies.

Today, STT-RAM can replace both NOR flash and SRAM in many embedded

applications. Non-volatile storage uses NOR flash for storing code, with that data being

transferred to SRAM acting as buffer or cache memory. Low-end cell phones for example use

both NOR and SRAM, which can easily be replaced with a single STT-RAM chip.

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Comparing STT-RAM with recent universal memory candidates, read and write/erase

time are each at 2 to 20 nanoseconds (ns) for STT-RAM, while phase-change RAM (PRAM)

takes 20 to 50 ns for a read, 30 ns for write. Further, STT-RAM endurance is unlimited at >1015

while PRAM is less than 1012.

Although it is not a new technology, PRAM has recently received considerable attention.

A number of leading semiconductor companies are investing in PRAM and developing their own

sets of IP. While it is an admirable technology, PRAM has limited endurance and slow speed

compared with STT-RAM.

Chalcogenide material, usually Ge2Sb2Te5 also known as GST, is used in a PRAM for

data storage. The PRAM uses the reversible phase change between the crystalline and

amorphous states of Chalcogenide GST by applying heat. Crystalline GST has low resistivity

and amorphous GST has high resistivity. The data "0" corresponds to the crystalline state, while

data "1" is associated with the amorphous state.

Switching time between states is larger than 20 ns, which means PRAM cannot replace

SRAM since it is considerably slower. The time required to reset the state of the bit must be

made long. If it is not, the phase change material cools too fast to achieve the crystalline state.

Further, due to the constantly changing of the phases and the heat applied to them, there is

material degradation and therefore limited endurance.

RRAM, or resistive memory, relies on a resistance change caused by an electric field. It

is in an earlier state of development compared with PRAM, but suffers similar problems in terms

of reliability and endurance. In addition, the switching mechanisms involved in the many

proposed RRAM materials are not well understood.

FRAM, or ferroelectric RAM, uses a ferroelectric material to store a polarization. It

suffers from limited read endurance and a destructive read process. Also, its endurance of around

1012 cycles, while suitable for a flash replacement, cannot be used as universal memory.

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6.3. STT-RAM Application Outlook:

STT-RAM is a disruptive technology that can revolutionize the performance of products

in many areas, from consumer electronics and personal computers to automotive,

medical, military and space.

It also has the potential to create new sectors in the semiconductor industry and enable

entirely new products not yet envisaged.

STT-RAM has key initial markets replacing embedded technologies such as SRAM,

Flash and DRAM, and providing new functionality at 65 nm and beyond. In automotive

applications, it has higher speed and lower power than Flash and is denser than SRAM.

In portable and handset applications, it can eliminate Multi-Chip Packages (MCPs),

provide a unified memory subsystem, and reduce system power consumption for

extended battery life. In personal computers, it can replace SRAM for high-speed cache,

Flash for non-volatile cache, and PSRAM and DRAM for high-speed program execution.

6.4. STT-RAM in AVIONICS and MILITARY Application:

We have investigated two non-volatile logic circuits based on Spin-MTJ for Field

Programmable Gate Array (FPGA) and System On Chip (SOC). The first one is a Spin-MTJ

based non-volatile Look Up Table (Spin-LUT) (Figure 6.4.1). Working as a programmable and

reconfigurable logic function generator, it memorizes all the configuration data in the MTJ

arrays; and thus allows the FPGA logic circuit to reduce significantly its start-up latency from

some microseconds down to some nanoseconds. It also allows realizing a sub-ns dynamical

reconfiguration of the LUT during the signal processing. Spin-LUT non-volatile logic circuit has

great potential in the field of complex logic digital system such as high performance game

console and radar signal processing.

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The second one is Spin-MTJ based non-volatile Flip-Flop (Spin-FF) (Figure 6.4.2), data

register and synchronizer, it stores permanently all the intermediate data processed in the FPGA

or SOC circuit, thereby improves the data security and enable the complex logic system to restart

immediately. Spin-FF could be advantageously used in the field of aviation and space where the

security of data is one of the most important considerations. The lower critical current of STT

writing approach makes these logic circuits work in less power and occupy smaller chip surface

than with other writing techniques. Therefore the reduction of critical current has a strong impact

on the performance of these Spin-MTJ based non-volatile logic circuits. Another advantage of

Spin-MTJ technology is that the storage element does not take much die area, because it is

processed over the chip surface (see Figure 6.4.3). By using STMicroelectronics 90nm CMOS

technology and a behavior Spin-MTJ simulation Model, Spin-LUT and Spin-FF have been

demonstrated that they could work with high speed performance and small layout surface.

Figure 6.4.1: Input Spin-LUT architecture

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Figure 6.4.2: The full schematic of Spin-MTJ based Non-Volatile Flip-Flop (Spin-FF)

Figure 6.4.3: MTJ memory cells are implemented above the CMOS circuits.

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Figure 6.4.4: Full layout (5.65um×10.15um) of Spin-FF, MTJs are placed above the two

points ML and MR, see also Figure 14

6.5. IC DESIGNERS BENEFITS:

STT-RAM is a more appropriate technology for future MRAM produced using ultra-fine

processes and can be efficiently embedded in subsequent generations of such semiconductor

devices as FPGAs, microprocessors, microcontrollers and Systems-On-Chip (SOC). A special

bonus for embedded designers is the fact that the internal voltage STT-RAM requires is only 1.2

Volts.

Hence, it can operate with a single 1.5 Volt battery, whereas DRAM and flash require

charge pumps to supply higher voltages. Existing NAND flash technology requires the internal

voltage to be raised to 10 to 12 volts for write operations. That voltage is boosted with the help

of a charge pump, which requires considerable power and presents adverse design conditions for

embedded designers.

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Another major benefit STT-RAM technology hands embedded designers is low writing

current on the order of 100 to 200 microamperes at the 90 nm node, thanks to its efficient spin-

transfer torque techniques. At the 45 nm semiconductor node and beyond, writing current

continues to scale down significantly below 100 micro amps. This lower current translates to a

denser, less expensive memory.

SUMMARY OF WORK

Finally, STT-RAM combines the capacity and cost benefits of DRAM, the fast read and

write performance of SRAM, and the non-volatility of Flash, coupled with essentially unlimited

endurance. Its performance exceeds that of other prospective non-volatile memory technologies,

and it solves the key drawbacks of first-generation, field-switched MRAM. It has excellent write

selectivity, excellent scalability beyond the 45 nm technology node, low power consumption,

and a simpler architecture and manufacturing process than first-generation MRAM.

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FUTURE SCOPE OF WORK

Continuous exploration of VOx-MTJ (Vortex Magnetic Tunnel Junction); focusing on

barrier growth and interface quality.

Re-visit of AlOx-MTJs to better understand the dependence of interface and barrier

quality on TMR.

New barrier materials exploration: Oxides like TiOx, TaOx, Nitrides like BN, etc.

Further optimization of lithographic patterning process.

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REFERENCE

[1]. http://en.wikipedia.org/wiki/Spin_(physics)

[2]. http://en.wikipedia.org/wiki/File:MRAM-Cell-Simplified.svg

[3]. http://en.wikipedia.org/wiki/Spin_Torque_Transfer

[4]. http://en.wikipedia.org/wiki/File:MRAM-Cell-Simplified.svg

[5]. http://www.bama.ua.edu/~tmewes/Java/Reversal/reversal.shtml

[6]. http://www.iop.org/EJ/abstract/0953-8984/19/16/165209.

[7]. http://arxiv.org/abs/cond-mat/0009034.

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[8]. http://arxiv.org/abs/cond-mat/0607362.

[9]. http://www.nature.com/nmat/journal/v3/n6/abs/nmat1120.html.

[10]. http://www.automotivedesignline.com/

showArticle.jhtml;jsessionid=CEHFFSV3FFZX4QSNDLOSKHSCJUNN2JVN?

articleID=197008084&queryText=stt-ram.

[11]. http://www.future-fab.com/documents.asp?d_ID=4210.

http://www.freescale.com/webapp/sps/site/overview.jsp?nodeId=015424

[12]. http://www.gigascale.org/pubs/1479.html.

[13]. www.grandisinc.com/technology/index.html https://www.fbo.gov/index?

s=opportunity&mode=form&id=ddf20ec1bb1cf832bbfc7266cf50cf2e&tab=core&_cview=1&cc

k=1&au=&ck=

[14]. http://www.dgmarket.com/eproc/np-notice.do~2311168

[15]. http://www.darpa.mil/MTO/Programs/sttram/index.html

[16]. “A novel SPRAM (Spin-transfer torque RAM) with a synthetic ferrimagnetic free layer

for higher immunity to read disturbance and reducing write-current dispersion”, Miura, K.

Kawahara, T.Takemura, R.Hayakawa, J.Ikeda, S.Sasaki, R.Takahashi, H.Matsuoka, H.Ohno,

H.Hitachi Ltd, Tokyo. This paper appears in: VLSI Technology, 2007 IEEE Symposium on

Publication Date: 12-14 June 2007.

[17]. AVIATION WEEK JANUARY 2009, TOPIC: SPIN STARTS NOW, Pg 78, (Defense

Technology International magazine).

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