SEMINAR REPORT

ON

INTEL’S 3D MICROCHIP WITH 3D TRANSISTOR STRUCTURE

SUBMITTED BY-ANAMIKA YADAV

002208280801-ECE-08

7TH SEM(4TH YEAR)

BHAGWAN PARSHURAM INSTITUTE OF ENGINEERINGPSP-4,Sec-17,Rohini,New Delhi-85

WHAT IS A MICROCHIP?

A Microchip also known as Integrated Circuit or monolithic integrated circuit is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material. Additional materials are deposited and patterned to form interconnections between semiconductor devices.

Integrated circuits are used in virtually all electronic equipment today and have revolutionized the world of electronics. Computers, mobile phones, and other digital appliances are now inextricable parts of the structure of modern societies, made possible by the low cost of production of integrated circuits.

FACTORS AFFECTING MICROCHIP PERFORMANCE

Major Factor that effect the microprocessor performance is the number of transistors fabricated on a single chip. Presently the fastest and best microprocessors in market employ 1 to 2 billion transistors per chip.

Number of transistors that can be fabricated depends upon the transistor size. At present the transistors that are fabricated are 32nm in size, i.e. the length of the transistor(Channel length) is 32nm.

As the transistor size gets smaller, more transistors are fabricated on a single chip thus increasing the processing speed of the transistor and improving its performance. But there is a limitation associated with this-

LIMITATION-As transistors get smaller and smaller, conventional transistors are subject to a problem called leakage. This means that when the transistor is in the "off" state, a small amount of current still flows through the channel. This leads to errors and drains power. It limits the size of the transistor further which it can’t be reduced more and thus transistor performance can’t be improved more.

MOORE’S LAW

Moore’s law is an accurate prediction by Intel co-founder Gordon Moore given in 1965. According to this law on average, the number of transistors on a computer chip doubles every 18month (2 year) and thus the transistor size will exponentially reduce.

That exponential rise in processing power has formed the basis for the steady advances in electronics since, though many in the industry fear that the chipmakers are approaching the limits of their ability to continue the improvements. This law has held true for quite some time, however, physical limits on how small a transistor can become has made adhering to the law more difficult.

INTEL REINVENTS CHIP WITH 3D TRANSISTOR

The 32-nanometer transistor at left is used in Intel’s chips today; the company’s new three-dimensional 22-nanometer transistor is at right. In the new transistor, gates intersect with silicon “fins” that stand up from the chip’s surface and interact with the gate on three sides

Intel advances its manufacturing process every two years, which helps make chips smaller and drives raw system performance while using less power. At an event in San Francisco, Intel announced one of the most important pieces of semiconductor news in many years: the company's upcoming 22nm processors will feature a fundamental change to the design of the most basic building block of every computer chip, the transistor.

Back in the early 2000s, Intel developed a way to build transistors that use a three dimensional switch shape rather than the typical planar shape. Intel has been exploring the new transistor for over a decade. It announced in early May 2011 that it would begin production of its next line of computer chips. The codename for this group of processors is Ivy Bridge. The Ivy Bridge chips will utilize a three dimensional structure (first of its kind) to enhance speed, performance and efficiency. This is important for Smartphone and tablets since they have limited battery capacity. The three dimensional shape of the transistors is very important to the continuance of Moore's law.

CONVENTIONAL PLANAR TRASISTOR AND LEAKAGE CURRENT PROBLEM

In the diagram above, it is a traditional "planar" transistor—the kind that was first invented at the dawn of the microchip era, and which has been the norm up until today's announcement—consists of three main parts: source, drain, and gate.

The device act just like an electrical switch. When a voltage is applied to the metal plate that forms the transistor's gate, a tiny strip of semiconductor material between the source and the drain changes from an insulator into a conductor, thereby turning the switch "on" and allowing current to flow from the source to the drain. When the voltage is removed, current stops flowing or, at least, current is supposed to stop flowing when the switch is off. In reality, trace amounts of current will constantly flow between the source and the drain. This so-called "leakage current" wastes precious power and becomes even more of a problem as transistors get smaller and more numerous.

Let's take a look at a different diagram of the same thing:

That little strip of blue, the inversion layer, is the region of material near the gate that turns into an electrical conductor when exposed to a voltage. Again, the gate is a small metal plate, and when that plate has a voltage applied to it the layer of semiconductor material that's sandwiched right up against it turns into a conductor.

Now, as transistor gates get smaller, inversion layer naturally gets smaller and thus less current is able to squeeze through it. When the gate and inversion layer get really small, as they are at the 22nm feature size, that layer can only let a tiny trickle of electrons flow through when the switch is on. But there's already a tiny trickle of (leakage) current flowing through when the switch is off, so the end result is a switch that looks almost the same when it's off as it does when it's on. That's not good, because flipping the switch "on" and "off" is how the chip transmits the 1's and 0's of binary.

HOW TO FIX LEAKAGE CURRENT PROBLEM IN SMALLER TRANSISTOR SIZE

There are two main was to fix this problem:

1) Reduce the leakage current in OFF state or

2) Force more electrons through inversion layer in ON state.

HOW INTEL FIXED THE PROBLEM

Intel's new design does a bit of both, but I'll focus on option 2, because that explains the majority of what's new and important about this advance.

There are two ways to get more electrons through inversion layer. The first and most obvious approach is to crank up the amount of voltage that we apply to the gate, so that the inversion layer will become even more electrically conductive. That's not ideal, though, because more voltage means more power consumption.

The other approach, which is better, is to find a way to make the inversion layer bigger. Bigger inversion layer could accommodate more electrical current, and it would do it with less voltage—i.e., we don't need to crank the voltage on the gate up quite so high in order to squeeze more conductivity out of the inversion layer, because the layer itself is larger and can transmit more current.

Intel took this second approach, and the chipmaker accomplished this by stretching the gate out into the third dimension thereby inventing all new 3-dimensional transistor structure onto chip.

INTEL’S TRI-GATE 3-DIMENSIONAL TRANSISTOR :

Intel's three-dimensional design has these same basic elements i.e., soure,drain and gate. But instead of being flat, the channel is a raised "fin" of silicon surrounded on three sides by the gate(thus tri-gate transistor). These new transistors are also known as "finFETs". Intel turned to the new design because existing designs have begun running up against a performance roadblock.

In the three-dimensional tri-gate transistor above, there's a lot of gate surface area in contact with the semiconductor material, so there's a lot more of that blue inversion layer for current to flow through. This makes the difference between the transistor "ON" and "OFF" states much larger, which means that the transistor can switch between states much faster while still producing a clear string of ON’s and OFF’s.

Also gate surrounding channel from 3sides allows for a more intimate connection between the gate and the channel, and that in turn enables better control, greatly reducing leakage current.

We could take advantage of this new structure to reduce its power consumption by applying less voltage to the gate. Even with small power supply, it will conduct equal amount of current as in planar 32nm transistor with high supply because of the increased conductivity of the channel.

Sure, the blue inversion layer adjacent to the gate would be less conductive, but there's more of it available to carry electrons, so we can still let the same amount of current through when the switch is on even with smaller size.

The middle part that sticks up there is called a "fin." If Intel wants to stretch the gate and inversion layer sizes out even further, its approach lets it add multiple fins under a single gate, for boosts in performance and/or power at the expense of transistor density.

Intel says the production of the three-dimensional transistors won't require any new manufacturing technologies. Extra etching steps will lead to just a small production cost increase.

WHO ORIGINALLY INVENTED 3D TRANSISTOR

These three-dimensional transistors were first imagined and built by three researchers at the University of California, Berkeley, in the late 1990s, in response to a call from the United States Defense Advanced Research Projects Agency for designs that would allow transistors to scale below 25 nanometers, an order of magnitude smaller than the ones in production at the time.A Berkeley group made up of Hu, Jeffrey Bokor, and Tsu-Jae King Liu first made these transistors, which they called FinFETs, in 1999.

Hu says the Berkeley researchers decided from the start that their new design would have to be compatible with the industry's existing infrastructure, and that has proved to be the case. The main hurdle in getting the technology ready for volume production, says Hu, was likely dealing with reliability: getting the dimensions of the very thin channel under control when billions of them must be made on every single wafer.

Hu says the Berkeley group designed these transistors so that they would not require circuit designers to completely redesign chip architectures. That's part of the reason why Intel can get products out so quickly. Hu's group has been working on circuit-simulation tools for the tri-gate transistors for the past five years.

Still, circuit designers see new opportunities that could open up with these transistors. They offer new ways of tuning the behavior of individual gates, which "gives designers new knobs to play with in order to further improve power efficiency and reliability," says Subhasish Mitra, professor of electrical engineering and computer science at Stanford University. Seeing a totally new transistor go into volume production within the span of about a decade is an

encouraging sign that the industry "is not stale" and that good technology ideas can still make it out of academic labs.

SEMICONDUCTOR MANUFACTURING PROCESSES

10 µm — 1971 3 µm — 1975 1.5 µm — 1982 1 µm — 1985 800 nm (.80 µm) — 1989 600 nm (.60 µm) — 1994 350 nm(.35 µm) — 1995 250 nm (.25 µm) — 1998 180 nm(.18 µm) — 1999 130 nm (.13 µm) — 2000 90 nm — 2002 65 nm — 2006 45 nm — 2008 32 nm — 2010 22 nm — 2011 16 nm — approx. 2013 11 nm — approx. 2015

THE RESULT

Ultimately, the advantage of stretching the gate out into the third dimension are that you can much more easily either boost the chip's frequency or reduce its power, or some mix of the two. This relationship is visually expressed in the graph below; for "gate delay" think "inverse of CPU clockspeed" and you'll get the gist of it.

1. Intel claims that the 22nm tri-gate transistors switch between 18 and 37 percent faster than the 32nm planar ones (depending on the voltage level).

2. Looked at from the voltage side, the new design can reduce active power by up to 50 percent.

3. It's also possible to make tri-gate transistors with more than one silicon channel connected to each gate in order to increase the amount of current that can flow through each transistor, enabling higher performance.

4. Intel will build the new transistors upward, making it possible to squeeze in more transistors while maintaining density and a small chip size.

5. The transistor structure allows Intel to continue the trend of Moore's Law, which calls for doubling the number of transistors every two years.

6. The 3D structure allows Intel to build more contact areas on smaller transistors, which enables more current to flow. That is key to scaling transistor performance.

7. Chips with 3D transistors will be "powerful" on performance and "power-less" on energy consumption.

These are some very significant jumps in performance and efficiency, and they'll go a long way toward making Intel's "x86 in smart phones at 22nm" dreams come true. Once again, Intel has proven that its semiconductor manufacturing prowess is without peer in the industry.