Low power Uart design for serial data communication

Presented By G YASHWANTH

SEMINAR ON

History of UART. Introduction of UART. UART types. UART design and protocol. Results and discussions:- Voltage-Scaling Clock-Gating Multi-Threshold CMOS (MT-CMOS) Complete Power Shutdown Data –Stream Dependent Shutdown Low Transition ASCII (LT-ASCII) Conclusion References

CONTENT

The first UART-like devices (with fixed-length pulses) were rotating mechanical switches (commutators).

The Western made Single-chip UART WD1402A around 1971.

Then Motorola introduced around 1975.

After it National Semiconductor introduced around 1980’s.

HISTORY OF UART

An UART (universal asynchronous receiver / transmitter) performs serial communications.

It Changes incoming parallel information to serial

data.

It Perform all the tasks like timing, parity checking etc.

It is used in conjunction with other communication standards such as EIA RS-232.

INTRODUCTION

UART INTERFACING

RS-232 HARDWARE VIEW

Serial communication on PC compatibles started with the 8250.

New family members introduced like 8250A and 8250B revisions and the 16450.

The 16450 was capable of handling a communication speed of 38.4kbs without problems.

16550 released which contained two on-board FIFO buffers each capable of storing 16 bytes.

UART TYPES

PIN DESCRIPTION

UART BLOCK DIAGRAM(WITH FIFO)

Our basic UART design consists of: two counters a shifter a finite state machine

The first two components CNT12 and CNT16, divide the clock frequency down to the desired data

transmission baud rate.

The finite state machine (FSM) is initially in the start state where it waits for a falling edge of the serial in data to signal in the start of an incoming10-bit word.

UART DESIGN AND PROTOCOL

CNT16 sends its first carry out pulse on its eighth count and remaining pulse signals every sixteen counts.

This makes the transmission rate equal to CLK/192 (12 x 16 = 192).

When the signal is received, the FSM enables the shift register to sample the serial in signal. I

UART DESIGN AND PROTOCOL (cont…)

SERIAL INTERFACE UART

Voltage – Scaling.Clock – gating.Multi-threshold CMOS (MT – CMOS).Complete power shutdown.Data-Stream dependant shutdown.Low transition ASCII ( LT-ASCII).

RESULTS AND DISCUSSIONS

Logic Power vs. Supply Voltage for different operation frequency

Logic Power vs. Operating Frequency in various low power schemes

Disable_Vdd signal generator for MT-CMOS and Vdd-cutoff

Timing Diagram for Disable_Vdd Signal Generator

Vdd cutoff circuit

I/O Power*Probabilty product vs. ASCII character

SUMMARY OF POWER SAVINGS

Low power configurations were examined to minimize the UART power consumption.

Complete Power Shutdown allows zero leakage current for the UART in idle mode.

The idle mode power for the DC-DC converter circuit was seen to be larger than the UART idle power with MT – CMOS.

CONCLUSION

It is more power efficient to implement MT – CMOS rather than complete power shutdown.

Resulted in minimal power consumption was low voltage operation with MT – CMOS and the Low transition ASCII (LT-ASCII) encoding scheme.

CONCLUSION(cont…)

THANK YOU

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