Seminar Abv Fpga Session2 Advanced Debugging With Assertions Rardeishar

8/12/2019 Seminar Abv Fpga Session2 Advanced Debugging With Assertions Rardeishar

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Advanced Debugging

With Assertions

January 2010

Harry D FosterChief Verification Scientist


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Mentor Graphics Company Confidential2

Overview

Understanding the debug challenge

How Questa can help debug assertions

Additional debug techniques


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Debugging is the Bottleneck

Effor t Allocation of Dedicated Ver ification

Engineers by Type of Activity

52%

34%

14%

Verif ication Debug Testbench Development Other


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Traditional Flow Focused on Full ChipBug Rate vs. Team Capacity


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Improved Flow with Sub-system Verif icationBug Rate vs. Team Capacity


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Debug - A Big Challenge

Environments include multiple disciplines

Verilog / VHDL / SystemC and now SystemVerilog

Advanced ver ification techniques improve verification productivity

At the price of debug productivi ty

Debug is 52% of the overall verification cycle*

Ability to create unknown out-of-body code experiences

New verification methodologies require new debug paradigms

* Source: 2008 Farwest Research and Mentor IC/ASIC Functional Verification Study


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Desired State for Debug

Single Environment for Design and Testbench debug

Automation that improves debug productivity

Automatic logging of assertion data, classes

Capabili ties that allow analysis and

quick identification of bugs

Software like debug capabili ties

Enhanced hardware like debug capabili ties

How ?


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Questa Debug ProductivityLeading Assertion and Coverage technology

Native support for both PSL and SVA

High performance assertion engine

Mentors ABV added value

Efficient Debug capabilities for PSL & SVA

Integrated Assertion Browser

View assertions in wave window

Break simulation if error encountered

Interactive and batch mode control

Best root cause analysis

Assertions are recorded in WLF fi le

Linking to dataflow


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Overview





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Debugging Assertions

Assertions are compact code structures

Can be a challenge to write, even more-so to debug

Need good tools to help visualize the assertion

Questa has powerful visualization and debug tools

Analysis pane

Lists all assertions at current hierarchical level and their

statistics

Waveform Viewer

Displays assertions and related signals Clear indication of status: active/inactive/pass/fail

Thread View

Decomposes assertions clause by clause for easy debug


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SystemVerilog lets you capture data at critical points w ithin a

sequence/property using local variables

Call functions/tasks within sequences

Debugging becomes easy with the assertion thread viewer

Debugging Assertions:SVA example with local variables

valid

in

out

EA BF

EB C0

Two threads

property e;

int x;

(valid, x = in) |-> ##5 (out == (x+1));

endproperty


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Questa: Assertion Debug Example

Assume we start with a design and the following assertion:

1. We compile the design & invoke simulator for assertion debug

vlib workvlog +acc=a

vsim assertdebug

propertyp_hs;

@(posedge clk) $rose(REQ) |-> ##[2:4] $rose(GNT);

endproperty

a_hs: assertproperty(p_hs)

else begin $error("%m Failed"); end


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Questa: Starting Window


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Questa: Analysis pane

Expanded view

of assertion a_hs

Asser tion

Fail

Count

Asser tion

Pass

Count

2. The analysis pane is a central location to analyzeand control assertions in your simulation

Enabling

assertionPass/Fail


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3. Add a desired assertion to the waveform window In Analysis pane right click on desired assertion and select:

In Analysis pane right click on desired assertion and select:

Questa: Waveform Setup

Add Wave / Selected Objects

Enable Assertion Thread Viewer


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Questa: Waveform Setup

4. In Waveform Window menu, select:

View / Assertion Debug

5. Run simulation

6. Click on Waveform Window red assertion failure triangle A yellow Cursor appears and the debug pane updates


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Questa: Wave view..

Asser tionStart

Asser tionPass

Asser tionFail

# of active

assertions

Asser tioninactive

Asser tionActive

Asser tion debug pane

gives signal info


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Bring up Assertion Thread View window

In Analysis pane right click on desired assertion and select:

View ATV

From popup, select start-time of failing assertion (390ns here)

Questa: Debug Assertion Threads


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Mentor Graphics Company Confidential

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Questa: Assertion Thread View

Interim Fail butother evaluations

still pending

Expression

matchedThread

finish

Thread

start


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Multiple Threads in Wave Window

Automatic

Thread count

integer

Expand to

see

individual

thread

RMC on start

of thread box

invokes ATV

Blue box

above thread

indicates

start of new

thread

Red triangle

indicates failure(green = pass)


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Advanced Assertion Debug with ATVExpanded

assertion

Green dots indicates

expression is true

Redundant failures:

individual spawned

thread failed but other

threads sti ll active

Red dots indicates

expression is false

Local

variable

pane

Yellow dots indicates

additional thread

spawned


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Selectable ThreadsFailing/Passing

thread

automatically

highlighted

Ability to select

or highlight

threads

individually

Local Variables

update to reflect

thread selection


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ABV Commands

vsim -nosva switch disables assertions during simulation

Assertion TCL commands apply to both PSL and SVA

Examples:

vsim> view assertions

vsim> assertion fail [-recursive] [-enable] [-disable]

[-action continue | break | exit ]

[-limit | none]

[-log on | off]

vsim> assertion pass [-recurs ive] [-enable] [-disable]

[-limit | none][-log on | off]

vsim> assertion report [-number] [-recursive] [-tcl_list]

[-verbose]


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Overview





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Debugging your design

What other debug tasks

contribute to the 52% of

project time attributed

to debug?

Design comprehension

Understanding results

Waveform analysis

Would it help to do this

post-simulation?

E i P D b


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Easing Processes DebugAids design comprehension

View all processes

together regardless

of language

Toggle between

viewing modes

All Windows l inked

to process window

Integral with

SystemC Debug

Interface

Message Viewer


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Message ViewerSee important messages quickly!


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Source Code Annotation

Linked to cursor location in wave window

Linked to dataflow window


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Textual Dataflow: Tracing Signals

Find reader of strb_r

Select Signal

then RMB


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Textual Dataflow: Tracing Signals

Find driver(s) of prdy_r

Select Signal

then RMB


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Drop Source To Waveform

S G


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Wave Window: Signal Grouping

Group signals

under user

defined name

Drag & drop

signals into and

out of group

Drag & drop

group as one

object

Collapse &

expand group

as needed


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Wave Window: Expanded Time

Expand the Wave Window to view all transit ions

during a single time step

Indicates multiple transitions

Blue background indicates

expanded section

Delta-time steps

Optional Post Processing Debug


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Optional Post Processing DebugDebug using familiar techniques post-simulation

No Simulation loaded, post

processing environment

Determine cause of event in

waveform through dataflow

Trace instance to module

Find object in source


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Summary

In this session we

Learned about how new verification

techniques create a new debug

paradigm

Learned new debug techniques that

can ease the assertion learning curve

Learned additional debug techniques

to reduce the verification effort


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Documents

Seminar Abv Fpga Session2 Advanced Debugging With Assertions Rardeishar