Semiconductor Devices and Nanoelectronics - …qli/ECE584/Lecture 1 MOSFET and...Semiconductor Devices and Nanoelectronics Qiliang Li Dept. of Electrical and Computer Engineering George

Semiconductor Devices and

Nanoelectronics

Qiliang Li

Dept. of Electrical and Computer Engineering

George Mason University, Fairfax, VA

[email protected]

Email: [email protected] 1

Content Outline

• Semiconductor materials and the carriers in semiconductors;

• Semiconductor fabrication and devices physics for pn junction, metal-semiconductor junction and MOS structure;

• MOSFET, its basic circuits (inverter, NAND and NOR logic) and memory devices (Flash, SRAM, DRAM and other NVM)

• Concepts in Nanoelectronics


What is semiconductors?

• Their electrical conductivity is between that of

metals (e.g., Al, Au, …) and insulators (e.g.,

SiO2, Al

2O3

and HfO2);

• Semiconductors are the foundation of modern

electronic circuits

• Important concepts: pn junction, transistor (BJT

and MOSFET), solar cell, Light-emitting diode,

digital and analog integrated circuits


The Common Semiconductors

• Conventional semiconductors: Silicon (Si),

germanium (Ge), GaAs, GaN, SiC …

• One dimensional semiconductor: nanowires

and nanotubes

• Two-dimensional semiconductors, e.g., MoS2

• we are always looking for new functional

semiconductor materials


Chapter 1. Electrons and Holes in

Semiconductors

1.1 Si Crystal Structure

• Unit cell of Si is cubic

• Each Si atom has 4

nearest neighbors


5.3 A

1.2 Bond Model of electrons and holes


Si Si Si

Si Si Si

Si Si Si

Si Si Si

Si Si Si

Si Si Si

Si Si Si

Si Si

Si Si Si

Si Si Si

Si Si

Si Si Si

As B

Intrinsic Si

Doped Si

As: group V

B: group III

EION

= 50 mV

Very low


1.3 Energy Band Model

2p

2s

(a) (b)

conduction band)(

(valence band)

Filled lower bands

} Empty upper bands

}

3P

3S

The highest filled band is the valence band

The lowest empty band is the conduction band


1.3 Energy Band Model

Conduction band Ec

Ev

Eg

Band gap

Valence band

� Energy band diagram shows the bottom edge of

conduction band, Ec

, and top edge of valence band, Ev

.

� Ec

and Ev

are separated by the band gap energy, Eg

.


1.4 Energy Band structure

Si band structure

Indirect band gap

6 minimum at <100>



Ge band structure

Indirect band gap

8 minimum at <111>



GaAs band structure

Direct band gap

Common methods:

• Slater-Koster tight-binding method

• Semi Empirical extended Huckel method

(using Huckel molecular orbital theory)

• Density functional theory (DFT) – Local-

Density Approximation (LDA) method

• Density functional theory (DFT) – Generalized

Gradient Approximations (GGA) method


1.5 Calculate the band structure



Use MoS2 monolayer as example:



We used Virtual Nanolab ATK software to calculate it.

Welcome collaboration on the research!

MoS2 band structure

calculated by using

DFT-GGA method

Direct band gap

Eg = 1.79 eV

Effective mass:

ml = 0.59 m0

mt = 0.50 m0

mdos = (6)2/3(mlmtmt)1/3

= 1.75 m0


Chapter 2. Device Fabrication and Physics

2.1 Device

Fabrication

Technology


2.1 Device Fabrication Technology

VLSI (Very Large Scale Integration)ULSI (Ultra Large Scale Integration)GSI (Giga-Scale Integration)

Variations of this versatile technology are

used for flat-panel displays, micro-electro-

mechanical systems (MEMS), and chips for

DNA screening...



Wafer

Oxidation

Lithography

Etching

Annealing &Diffusion

AlSputtering

(0)

Positive resist SiO2

P-Si

P-Si

SiO2

P-Si

Mask

UV

SiO2 SiO2

P-Si

(1)

(2)

(3)

SiO2

UV

Lithography

SiO2 SiO2

SiO2 SiO2

PN+

SiO2 SiO2

PN+

P-Si

SiO2 SiO2

PN+

Mask

Al Resist

(4)

Arsenic implantation

Al

UV

(7)

(5)

(6)

Al

UV

Ion

Implantation

* An example from “Modern Semiconductor Devices for Integrated Circuits” (C. Hu)


Metal etching

CVDnitridedeposition

Lithographyand etching

Back Side milling

Back side metallization

Dicing, wire bonding,and packaging

SiO2 SiO2

PN+

(8)

(9)

SiO2 SiO2

PN+

SiO2 SiO2

PN+

(10)

SiO2 SiO2

PN

+

(11)

Al

Si3N

4

Si3N

4

Si3N

4

Al

Al

Al

Photoresist

SiO2 SiO2

PN+

(12)

SiO2 SiO2

PN+

(13)

Si3N

4

Si3N

4

Al

Al

Au

Au

wire

Plastic package

metal leads


* An example from “Modern Semiconductor Devices for Integrated Circuits” (C. Hu)


2.2 pn Junction

On the P-side of the depletion layer, ρ = –qNa

On theN-side, ρ = qNd

s

aqN

dx

d

ε−=E

)()(1

xxqN

CxqN

xP

s

a

s

a −=+−=εεE

)()(N

s

d xxqN

x -=εE

N P

Depletion Layer Neutral Region

xn

0 xp

x x

p xn

qNd

–qNa

x

E

xn xp

ρ

0

Neutral Region

N

N

N P

P

P

Electric Field


2.2 pn Junction

On the P-side,

Arbitrarily choose the voltage atx = xP asV = 0.

On the N-side,

2)(2

)( xxqN

xV Ps

a −=ε

2)(2

)( Ns

d xxqN

DxV −−=ε

2)(2 N

s

dbi xx

qN −−=ε

φ

x

E

xn xp

Ec

Ef

Ev

φbi, built-in potential

0

xn

xp

x

φbiV

N

N

P

P

Electric Field and potential


V is continuous atx = 0

If Na >> Nd , as in a P+N junction,

What about a N+P junction?

wheredensity dopant lighterNNN ad

1111 ≈+=

+==−

da

bisdepNP NNq

Wxx112 φε

Nd

bisdep x

qNW ≈= φε2

qNW bisdep φε2=

N P

Depletion Layer Neutral Region

–xn

0 xp

Neutral Region

0≅=adNP

NNxx| | | |

PN

2.2 pn JunctionDepletion layer width


(b) reverse-biased

qV

Ec

EcEfn

Ev

qφbi + qV Efp

Ev

2.2 pn Junction

qN

barrier potential

qN

VW srbis

dep

⋅=+= εφε 2|)|(2

+ –V

N P

Reverse-Biased

dep

sdep W

ACε=Reverse biased PN

junction is a capacitor.

222

2

2

)(21

AqN

V

A

W

C S

bi

s

dep

dep εφ

ε+==

Vr

1/Cdep

2

Increasing reverse bias

Slope = 2/qNεsA2

– φbi

Capacitance data

How to minimize the

junction capacitance?


2.2 pn Junction - breakdown2/1

|)|(2

)0(

+==

rbis

p VqN φεEEEEEEEEPeak electric field and

breakdown voltage: bi

critsB

qNV φε −=

2

2EEEE

Empty StatesFilled States-

Ev

Ec

V/cm106≈=

critp EE

pεeG J / H−=

Tunneling Breaking

EcEfn

Ec

Ev

Efp

originalelectron

electron-holepair generation

Impack ionization � avalanche breakdown

daB N

1

N

1

N

1V +=∝Basis for tunneling FET for smaller

subthreshold swing


2.2 pn Junction – forward bias

Minority carrier injection

)1()()( 00 −=−≡′ kTqVPPPP ennxnxn

)1()()( 00 −=−≡′ kTqVNNNN eppxpxp

( )P

LxxkTqVP xxeenxn nP <−=′ − ,)1()( //

0

( )N

LxxkTqVN xxeepxp pN >−=′ −− ,)1()( //

0

L: diffusion length ~ 10 um, depending on N

xJ

enL

Dqp

L

DqxJxJ kTVq

Pn

nN

p

pPnPNpN

allat

)1()()(current Total 00

=

−

+=+=


2.2 pn Junction – Solar Cell

)/ln( 2idpoc nGN

q

kTV τ=

GAqLAJI ppsc == )0(

NP+

Isc

0x

* “Modern Semiconductor Devices for Integrated Circuits” (C. Hu)


2.2 pn Junction –LED

)(

24.1

energy photon

24.1 m) ( h wavelengtLED

eVEg

≈=µ

Direct band gap

Example: GaAs

Direct

recombination is

efficient as k

conservation is

satisfied.

Indirect band gap

Example: Si

Direct

recombination is

rare as k

conservation is not

satisfied


2.3 Metal-Semiconductor Junction

Two kinds of metal-semiconductor contacts:

• Rectifying Schottky diodes: metal on lightly doped silicon

•Low-resistance ohmic contacts: metal on heavily doped silicon

V

I

Reverse bias Forward bias


MetalDepletion

layerNeutral region

qφBn

Ec

Ec

Ef

Ef

Ev

EvqφBp

N-Si

P-Si


Schottky Barrier

• Schottky barrier height, φB , is a function of the metal material.

• φB is the most important parameter. The sum of qφBn

and qφBp is equal to Eg .


qφBn Ec

Ev

Ef

E0

qψM

χSi = 4.05 eV

Vacuum level,

+ −−−−

A high density of energy

states in the bandgap at the

metal-semiconductor

interface pins Ef

to a narrow

range and φBn

is typically 0.4

to 0.9 V.

Silicide ErSi1.7 HfSi MoSi2 ZrSi2 TiSi2 CoSi2 WSi2 NiSi2 Pd2Si PtSi

φ Bn (V) 0.28 0.45 0.55 0.55 0.61 0.65 0.67 0.67 0.75 0.87

φ Bp (V) 0.55 0.49 0.45 0.45 0.43 0.43 0.35 0.23

φBn

φBp


φBn + φBp ≈ Eg

Silicide-Si contact:



2.4 Metal-Oxide-Semiconductor Capacitor

SiO2

metal

gate

Si body

Vg

gate

P-body

N+

MOS capacitor MOS transistor

Vg

SiO2

N+


E0 : Vacuum levelE0 – Ef : Work functionE0 –Ec : Electron affinitySi/SiO2 energy barrier

sgfbV ψψ −=

χSiO2=0.95 eV

9 eV

Ec, Ef

Ev

Ec

Ev

Ef

3.1 eV q ψs= χSi + (Ec–Ef) qψg χSi

0

3.1 eV

Vfb

N+ -poly-Si P-body

4.8 eV

=4.05eV

Ec

Ev

SiO2

The band is flat at the flat band voltage.

q

2.4 MOS – flat-band condition


2.4 MOS – surface accumulation

oxsfbg VVV ++= φ3.1eV

Ec ,E f

Ev E

0

Ec

Ef

Ev

M O S

qVg

Vox

qφs

Make Vg < Vfb

sφ is negligible whenthe surface is in accumulation.

φφφφs : surface potential, band bendingVox: voltage across the oxide


fbgox VVV −=

)( fbgoxacc VVCQ −−=

oxsox CQV /−=

oxaccox CQV /−=Gauss’s Law

Vg <Vt

2.4 MOS – surface accumulation

Many reported nanowire / nanotube FET is actually operated in

accumulation mode


2.4 MOS – surface depletion (Vg > Vfb)

ox

ssa

ox

depa

ox

dep

ox

sox C

qN

C

WqN

C

Q

C

QV

φε2==−=−=

Ec,E f

Ev

E c

EfEv

M O S

qVg

depletion

region

qφs

Wdep

qVox

----

SiO2

gate

P-Si body

+ + + + + +

- - - - - - -

V- - - - - - -

depletion layercharge, Q

dep

- - - - - - -

ox

ssasfboxsfbg C

qNVVVV

φεφφ

2++=++= φ

s



2.4 MOS – surface inversion

Ec,Ef

M O S

Ev

Ef

Ei

Ec

AB

C =qφφφφΒΒΒΒ

Ev

DqVg

= qVt

φφφφst

Threshold of inversion:ns = Na , or

(Ec–Ef)surface= (Ef – Ev)bulk , or

� A=B, andC = D

==

i

aBst n

N

q

kTln22φφ

=

−

=−−=

i

a

a

v

i

vbulkvf

gB n

N

q

kT

N

N

q

kT

n

N

q

kTEE

Eq lnlnln|)(

2φ

ox

BsaBfbgt C

qNVthresholdatVV

φεφ

222 ++==At threshold:


2.4 MOS – Threshold Voltage

Tox = 20nm

Vt(V

), N

+ −g

ate

/P-b

ody

Vt(

V),

P+−g

ate

/N-b

ody

Body Doping Density (cm-3)

ox

BssubBfbt C

qNVV

φεφ

222 ±±= + for P-body,

– for N-body



2.4 MOS – Capacitance vs. Voltage

g

s

g

g

dV

dQ

dV

dQC −==

Qs

0Vg

accumulationregime

depletionregime

inversionregime

Qinv

C

Vfb Vt

Cox

accumulation depletion inversion

Vg

Vt

Vfb

slope = − Cox


2.4 MOS – Capacitance vs. Voltage

depox CCC

111 +=

sa

fbg

ox qN

VV

CC ε)(211

2

−+=

CCox

accumulation depletion inversion

VgVfb Vt

In the depletion regime:


Capacitor and Transistor CV (or HF and LF CV)

电子有足够时间response

• /* Lines with '/*' as first entry are ignored */

• eoxr = 3.9 /* Relative dielectric constant for insulator */ 你用的材料的介电参

数，如果不是氧化硅的要改

• esr = 11.8 /* Relative dielectric constant for semiconductor */ 衬底材料的介

电参数，如果不是硅的要改

• ni = 1.44e10 /* Intrinsic carrier density */ 这是硅的intrinsic carrier density，

如果不是硅的要改

• nc = 2.80e19 /* Conduction band density of states */这是硅的导带 carrier

density，如果不是硅的要改

• nv = 1.04e19 /* Valence band density of states */这是硅的价带 carrier density，如果

不是硅的要改

• ego = 1.17 /* Extrapolated T=0 semiconductor band gap */这是硅的禁

带宽度（温度为0时的带宽）

• alf1 = 4.73e-4 /* Temperature corfficient of band gap -- form eg = ego - alf1*T^2/(T

+ to1) */这是温度对能带Eg的影响，材料不同而有所不同，不过，这是微调，在很多情

况下，不太重要。

• to1 = 636. /* Coefficient for temperature dependancy of band gap */

同上，你可以看到，硅和GaAs就有些不同。


2.4 MOS: C-V Curve Fitting

CVC is a open source software (by NCSU) for CV fitting


Chapter 3. Introduction of MOSFET and its

applications

The MOSFET (MOS Field-Effect Transistor) is the building block of Gb memory chips, GHz microprocessors, analog, and RF circuits.

Match the following MOSFET characteristics with their applications:

• small size• high speed• low power• high gain


3.1 Introduction to the MOSFET

Basic MOSFET structure and IV characteristics

+ +


3.2 Complementary MOSFETs Technology

When Vg = Vdd , the NFET is on and the PFET is off. When Vg = 0, the PFET is on and the NFET is off.

nFET pFET



Static Complementary CMOS

VDD

F(In1,In2,…InN)

In1

In2

InN

In1

In2

InN

PUN

PDN

PMOS only

NMOS only

PUN and PDN are dual logic networks


3.3 CMOS (Complementary MOS) Inverter

A CMOS inverter is made of a PFET pull-up device and a NFET pull-down device. Vout = ? if Vin = 0 V.

C:

Vin

Vdd

PFET

NFET

0V 0V

S

D

D

S

Vout

etc.) (of interconnect, capacitance


CMOS Inverter--voltage transfer curve

Vin (V)

Vout (V)

0 0.5 1.0 1.5 2.0

0.5

1.0

2.0

1.5

Vdd

Vdd


Inverter Speed – propagation delay

delaynpropagatio:dτ

C C

V1

V2

V3

Vdd

...........

............

Vdd

0

V2

V1

t

V32τ

d

To measure the speed

onN

dd

onP

dd

d

I

CVdelaydownpull

I

CVdelayuppull

delayuppull

delaydownpull

2

2

)

(2

1

≈−

≈−

−

−≡

+τ


3.3 CMOS NOR Gate

Try not to stack PMOS?


3.3 CMOS NAND Gate


-0.5

0

0.5

1

1.5

2

2.5

3

0 100 200 300 400

A=B=1→0

A=1, B=1→0

A=1 →0, B=1

time [ps]

Vo

lta

ge

[V

]

Input DataPattern

Delay(psec)

A=B=0→1 69

A=1, B=0→1 62

A= 0→1, B=1 50

A=B=1→0 35

A=1, B=1→0 76

A= 1→0, B=1 57

NMOS = 0.5µm/0.25 µm

PMOS = 0.75µm/0.25 µm

CL

= 100 fF

3.3 CMOS NAND Gate - Timing


3.4 Master-Slave Register

QM

Q

D

CLK

T2I2

T1I1

I3 T4I5

T3I4

I6

Multiplexer-based latch pair


3.5 SRAM

MMMM1111MMMM2222

MMMM3333MMMM4444

MMMM5555

MMMM6666

“HI” “HI” “HI” “HI”

(LOW)(LOW)(LOW)(LOW)

“LOW” “LOW” “LOW” “LOW”

(HI)(HI)(HI)(HI)

VVVVdddddddd

BLBLBLBL BLCBLCBLCBLC

WLWLWLWL>Fastest among all memories.

>Totally CMOS compatible.

>Cost per bit is the highest--

uses 6 transistors to store one

bit of data.


3.6 DRAM

•DRAM capacitor can

only hold the data

(charge) for a limited

time because of leakage

current.

Bit-line 1

Word-line 1

Bit-line 2

Word-line 2

•Needs refresh.

•Needs ~10fF C in a small

and shrinking area -- for

refresh time and error rate.


3.7 Nonvolatile Memory

Flash or SONOS memory

Phase change memory

Resistive memory (RRAM)

Molecular memory

The current challenge (opportunity) is to find excellent

electrically accessible NVM for CPU.


3.8 Concepts in MOSFET

• The leakage current that flows at Vg<Vt is called the

subthreshold current.

90nm technology. Gate length: 45nm

Intel, T. Ghani et al., IEDM 2003

I ds( µ

A/µ

m)

Vgs

VtVt

• The current at Vgs=0 and Vds=Vdd is called Ioff.

Subthreshold Current


Subthreshold Leakage Current

( ) / kTVqkTq

s

gss een

dsI

ηϕ /constant/ kTqV gseη/∝∝∝∝ +

Cdepϕs

Cox

VG

dep

oxeC

C

η = 1 +

• Subthreshold current changes 10x for η·60mVchange in Vg. Reminder: 60mV is (ln10)·kT/q

•Subthreshold swing, S : the change in Vgscorresponding to 10x change in subthreshold current. S = η·60mV,typically 80-100mV / dec

kTqV gseη/∝

dsI


Subthreshold Leakage Current

is determined only by Vt and

subthreshold swing.

• Practical definition of Vt : the Vgs at which Ids= 100nA×W/L

=> ( ) kTVVq tge

L

W

subthresholdI

/100

− ( ) SVVtg

L

W /10100

−××=××nA )( ≈ η

Vgs

Log (Ids)

Vt

100×W/L(nA)

Vds=Vdd

Ioff

W SV t

L

/10100−

××Ioff (nA) =

1/S


Subthreshold Swing

• Smaller S is desirable(lower Ioff for a given Vt). Minimum possible value of S is 60mV/dec.

• How do we reduce swing?• Thinner Tox => larger Coxe

• Lower substrate doping => smaller Cdep

• Lower temperature

• Limitations• Thinner Tox ― oxide breakdown reliability or oxide leakage

current • Lower substrate doping ― doping is not a free parameter but

set by Vt.

+⋅=

oxe

dep

C

CmVS 160

++⋅=

oxe

sdep

C

ddQCmVS

φ/160 int

Effect of Interface States �


3.9 Major Challenges in MOSFET

Threshold Voltage (Vt) Roll-off

65nm technology. EOT=1.2nm, Vdd

=1V

* K. Goto et al., (Fujitsu) IEDM 2003

• Vt roll-off : Vt decreases with decreasing Lg.

• It determines the minimum acceptable Lgbecause Ioff is too large if Vt becomes too small.

• Question: Why data is plotted against Lg, not L?

Answer: L is difficult to measure. Lg is. Also, Lg is the quantity that manufacturing engineers can control directly.

0.01 0.1 1-0.25

-0.20

-0.15

-0.10

-0.05

0.00

Vds = 50mV Vds = 1.0V

Symbols: TCADLines: Model

Vt R

oll-o

ff (V

)

Lg (um)


• Vds dependence

Energy-Band Diagram from Source to Drain

• L dependence

long channel

Vds

short channel

source/channel barrier

Vgs

log(Ids)

Vds

long channel

short channel

Vds=0

Vds=VddVds=Vdd

Vds

=0

DIBL: Drain Induced Barrier

Lowering

GIDL: gate induced drain

leakage


Vt

Roll-off – Simple Capacitance Model

As the channel length is

reduced, drain to channel

distance is reduced� Cd

increases

oxe

ddslongtt C

CVVV ⋅−= −

Vds helps Vgs to invert the surface, therefore

Due to built-in potential between N-

channel and N+ drain & source

( )oxe

ddslongtt C

CVVV ⋅+−= − 4.0

( )3

l/

where

4.0

jdepoxd

Ldslongtt

XWTl

eVVV d

≈

⋅+−= −−

• 2-D Poisson Eq. solution shows that Cd is an exponential function of L.

Cd

n+ Xj

P-Sub

Coxe

Wdep

Tox

Vgs

Vds

That is why we need to shrink Tox

, body thickness, junction depth!

We need 2D materials like graphene and MoS2


Chapter 4. Concepts in Nanoelectronic

Materials and DevicesInternational Technology Roadmap for Semiconductors

Year of Shipment 2003 2005 2007 2010 2013

Technology Node (nm) 90 65 45 32 22

Lg (nm) (HP/LSTP) 37/65 26/45 22/37 16/25 13/20

EOTe(nm) (HP/LSTP) 1.9/2.8 1.8/2.5 1.2/1.9 0.9/1.6 0.9/1.4

VDD (HP/LSTP) 1.2/1.2 1.1/1.1 1.0/1.1 1.0/1.0 0.9/0.9

Ion,HP (µA/µm) 1100 1210 1500 1820 2200

Ioff,HP (µA/µm) 0.15 0.34 0.61 0.84 0.37

Ion,LSTP (µA/µm) 440 465 540 540 540

Ioff,LSTP (µA/µm) 1e-5 1e-5 3e-5 3e-5 2e-5

Strained Silicon High-k/Metal-GateWet Lithography

New Structure• Vdd is reduced at each node to contain power consumption •Tox is reduced to raise Ion and retain good transistor behaviors• HP: High performance; LSTP: Low stand-by power


4.1 Strained Silicon: example of innovations

The electron and hole mobility can be raised by carefully

designed mechanical strain.

N-type Si

Trenches filled with epitaxial SiGe

Gate

S D

Mechanical strain

Strained Si technology has been used in microprocessor.


4.2 MOSFET with Metal Source/Drain

To unleash the potentials of Schottky S/D MOSFET, a low-Schottky junction is needed for NFETs and low- for PFET.

Bnφ

Bpφ


4.3 Single-Electron Transistor

• Adding gate control on a Coulomb-Blockade

structure – single-electron tunneling transistor

or simply single-electron transistor (SET)

Vg > 0 will depress the Fermi level, Ef

Vg < 0 will raise Ef

• Above, below and lie up with Ef of right/left side


* “Fundamentals of Nanoelectronics” (G. Hanson)


The net charge on the island:



Solved:


An electron tunnel into the island from b, the change of stored energy is


Similarly for an

electron from island to

Junction a:


Assume initially island is charge neutral

(n=0), an electron tunnels into the island

through junction b

I > 0



Now the island is has one electron (n=1), the electron

tunnels off from the island into junction a:

I > 0



To observe a current from junction b to a, both

condition need to be met:

Current > 0



Coulomb diamonds

Charge stability diagram

Shaded regions: no tunneling is

allowed



Other SET and FET structures

Carbon nanotube FET

• Tunneling theory: with a focus on resonant

tunneling

• Coulomb blockade (basis for SET)

• Ballistic transport

• Spin transport and spintronics

• Topological insulator

• 2D materials: graphene and MoS2


Other concepts in nanoelectronics

Documents

Semiconductor Devices and Nanoelectronics - …qli/ECE584/Lecture 1 MOSFET and...Semiconductor Devices and Nanoelectronics Qiliang Li Dept. of Electrical and Computer Engineering George